Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6189420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29549785

1

T1

43

T2

41

T3

857

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13646305	1			T1	27		T2	29		T3	216
values[0x0]	10834380	1			T1	17		T2	10		T3	327
values[0x1]	11258520	1			T1	13		T2	19		T3	345

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4703815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31035390

1

T1

45

T2

41

T3

876

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34900	1			T16	698		T17	698		T18	698
valid_sources[0x01]	277200	1			T16	5544		T17	5544		T18	5544
valid_sources[0x02]	115140	1			T25	128		T31	128		T34	128
valid_sources[0x03]	106940	1			T3	167		T19	167		T20	167
valid_sources[0x04]	186700	1			T16	3734		T17	3734		T18	3734
valid_sources[0x05]	112780	1			T7	5		T9	5		T10	17
valid_sources[0x06]	133430	1			T4	19		T5	19		T6	19
valid_sources[0x07]	440300	1			T16	8806		T17	8806		T18	8806
valid_sources[0x08]	107600	1			T16	2152		T17	2152		T18	2152
valid_sources[0x09]	80000	1			T16	1600		T17	1600		T18	1600
valid_sources[0x0a]	146090	1			T25	128		T31	128		T34	128
valid_sources[0x0b]	232750	1			T16	4655		T17	4655		T18	4655
valid_sources[0x0c]	126950	1			T16	2539		T17	2539		T18	2539
valid_sources[0x0d]	162900	1			T16	3258		T17	3258		T18	3258
valid_sources[0x0e]	95350	1			T16	1907		T17	1907		T18	1907
valid_sources[0x0f]	23190	1			T10	7		T11	7		T40	7
valid_sources[0x10]	35600	1			T16	712		T17	712		T18	712
valid_sources[0x11]	71245	1			T7	5		T9	5		T10	79
valid_sources[0x12]	92190	1			T25	128		T31	128		T34	128
valid_sources[0x13]	103700	1			T16	2074		T17	2074		T18	2074
valid_sources[0x14]	276550	1			T16	5531		T17	5531		T18	5531
valid_sources[0x15]	101650	1			T16	2033		T17	2033		T18	2033
valid_sources[0x16]	159430	1			T27	4		T37	4		T42	4
valid_sources[0x17]	66200	1			T16	1324		T17	1324		T18	1324
valid_sources[0x18]	46275	1			T7	5		T9	5		T16	925
valid_sources[0x19]	69240	1			T25	128		T31	128		T34	128
valid_sources[0x1a]	229700	1			T16	4594		T17	4594		T18	4594
valid_sources[0x1b]	156150	1			T16	3123		T17	3123		T18	3123
valid_sources[0x1c]	77600	1			T16	1552		T17	1552		T18	1552
valid_sources[0x1d]	64860	1			T4	20		T5	20		T27	8
valid_sources[0x1e]	123625	1			T7	5		T9	5		T16	2472
valid_sources[0x1f]	33400	1			T16	668		T17	668		T18	668
valid_sources[0x20]	35450	1			T4	60		T5	60		T6	60
valid_sources[0x21]	34850	1			T16	697		T17	697		T18	697
valid_sources[0x22]	71950	1			T16	1439		T17	1439		T18	1439
valid_sources[0x23]	198150	1			T16	3963		T17	3963		T18	3963
valid_sources[0x24]	72600	1			T16	1452		T17	1452		T18	1452
valid_sources[0x25]	80550	1			T16	1611		T17	1611		T18	1611
valid_sources[0x26]	18100	1			T16	362		T17	362		T18	362
valid_sources[0x27]	127000	1			T16	2540		T17	2540		T18	2540
valid_sources[0x28]	38300	1			T16	766		T17	766		T18	766
valid_sources[0x29]	46950	1			T16	939		T17	939		T18	939
valid_sources[0x2a]	60200	1			T16	1204		T17	1204		T18	1204
valid_sources[0x2b]	114800	1			T16	2296		T17	2296		T18	2296
valid_sources[0x2c]	93070	1			T27	1		T37	1		T42	1
valid_sources[0x2d]	33150	1			T16	663		T17	663		T18	663
valid_sources[0x2e]	211475	1			T7	5		T9	5		T16	4229
valid_sources[0x2f]	67720	1			T27	11		T37	11		T42	11
valid_sources[0x30]	86340	1			T10	2		T11	2		T40	2
valid_sources[0x31]	223950	1			T16	4479		T17	4479		T18	4479
valid_sources[0x32]	115250	1			T16	2305		T17	2305		T18	2305
valid_sources[0x33]	69535	1			T7	5		T9	5		T27	28
valid_sources[0x34]	76500	1			T4	20		T5	20		T6	20
valid_sources[0x35]	89300	1			T16	1786		T17	1786		T18	1786
valid_sources[0x36]	218450	1			T16	4369		T17	4369		T18	4369
valid_sources[0x37]	264100	1			T4	10		T5	10		T27	30
valid_sources[0x38]	159105	1			T7	5		T9	5		T4	19
valid_sources[0x39]	74830	1			T1	9		T32	9		T33	9
valid_sources[0x3a]	50425	1			T7	5		T9	5		T4	20
valid_sources[0x3b]	37700	1			T16	754		T17	754		T18	754
valid_sources[0x3c]	260350	1			T16	5207		T17	5207		T18	5207
valid_sources[0x3d]	73600	1			T16	1472		T17	1472		T18	1472
valid_sources[0x3e]	6555	1			T7	5		T9	5		T27	4
valid_sources[0x3f]	37890	1			T25	128		T31	128		T34	128
valid_sources[0x40]	138900	1			T16	2778		T17	2778		T18	2778
valid_sources[0x41]	65400	1			T16	1308		T17	1308		T18	1308
valid_sources[0x42]	32650	1			T4	20		T5	20		T6	20
valid_sources[0x43]	187550	1			T16	3751		T17	3751		T18	3751
valid_sources[0x44]	39650	1			T16	793		T17	793		T18	793
valid_sources[0x45]	31200	1			T16	624		T17	624		T18	624
valid_sources[0x46]	65100	1			T16	1302		T17	1302		T18	1302
valid_sources[0x47]	155650	1			T16	3113		T17	3113		T18	3113
valid_sources[0x48]	212400	1			T16	4248		T17	4248		T18	4248
valid_sources[0x49]	137200	1			T4	20		T5	20		T6	20
valid_sources[0x4a]	116500	1			T16	2330		T17	2330		T18	2330
valid_sources[0x4b]	159925	1			T7	5		T9	5		T16	3198
valid_sources[0x4c]	120400	1			T16	2408		T17	2408		T18	2408
valid_sources[0x4d]	55440	1			T25	128		T31	128		T34	128
valid_sources[0x4e]	288150	1			T16	5763		T17	5763		T18	5763
valid_sources[0x4f]	148880	1			T1	9		T32	9		T33	9
valid_sources[0x50]	85350	1			T16	1707		T17	1707		T18	1707
valid_sources[0x51]	59150	1			T16	1183		T17	1183		T18	1183
valid_sources[0x52]	243100	1			T16	4862		T17	4862		T18	4862
valid_sources[0x53]	129925	1			T7	5		T9	5		T16	2598
valid_sources[0x54]	76790	1			T27	12		T37	12		T42	12
valid_sources[0x55]	104700	1			T16	2094		T17	2094		T18	2094
valid_sources[0x56]	87250	1			T16	1745		T17	1745		T18	1745
valid_sources[0x57]	151600	1			T16	3032		T17	3032		T18	3032
valid_sources[0x58]	178000	1			T16	3560		T17	3560		T18	3560
valid_sources[0x59]	17550	1			T10	5		T11	5		T40	5
valid_sources[0x5a]	69835	1			T36	7		T55	7		T16	1396
valid_sources[0x5b]	112255	1			T7	5		T9	5		T25	256
valid_sources[0x5c]	75500	1			T16	1510		T17	1510		T18	1510
valid_sources[0x5d]	73500	1			T16	1470		T17	1470		T18	1470
valid_sources[0x5e]	149300	1			T16	2986		T17	2986		T18	2986
valid_sources[0x5f]	153890	1			T27	2		T37	2		T42	2
valid_sources[0x60]	35240	1			T27	7		T37	7		T42	7
valid_sources[0x61]	146710	1			T27	13		T37	13		T42	13
valid_sources[0x62]	60340	1			T25	128		T31	128		T34	128
valid_sources[0x63]	90300	1			T16	1806		T17	1806		T18	1806
valid_sources[0x64]	47650	1			T16	953		T17	953		T18	953
valid_sources[0x65]	40565	1			T7	5		T9	5		T10	7
valid_sources[0x66]	59650	1			T16	1193		T17	1193		T18	1193
valid_sources[0x67]	42950	1			T16	859		T17	859		T18	859
valid_sources[0x68]	82485	1			T36	7		T55	7		T16	1649
valid_sources[0x69]	167590	1			T25	128		T31	128		T34	128
valid_sources[0x6a]	95800	1			T16	1916		T17	1916		T18	1916
valid_sources[0x6b]	79400	1			T16	1588		T17	1588		T18	1588
valid_sources[0x6c]	167880	1			T3	49		T19	49		T20	49
valid_sources[0x6d]	65650	1			T4	20		T5	20		T6	20
valid_sources[0x6e]	5625	1			T7	5		T9	5		T16	112
valid_sources[0x6f]	50890	1			T25	128		T31	128		T34	128
valid_sources[0x70]	157425	1			T7	5		T9	5		T16	3148
valid_sources[0x71]	88100	1			T16	1762		T17	1762		T18	1762
valid_sources[0x72]	334850	1			T4	20		T5	20		T6	20
valid_sources[0x73]	86140	1			T3	82		T19	82		T20	82
valid_sources[0x74]	88975	1			T7	5		T9	5		T27	5
valid_sources[0x75]	46600	1			T16	932		T17	932		T18	932
valid_sources[0x76]	69275	1			T7	5		T9	5		T16	1385
valid_sources[0x77]	74480	1			T27	39		T37	39		T42	39
valid_sources[0x78]	153675	1			T7	5		T9	5		T16	3073
valid_sources[0x79]	128450	1			T16	2569		T17	2569		T18	2569
valid_sources[0x7a]	210260	1			T27	3		T37	3		T42	3
valid_sources[0x7b]	59850	1			T16	1197		T17	1197		T18	1197
valid_sources[0x7c]	79450	1			T16	1589		T17	1589		T18	1589
valid_sources[0x7d]	50575	1			T7	5		T9	5		T16	1011
valid_sources[0x7e]	1176125	1			T7	5		T9	5		T16	23522
valid_sources[0x7f]	162900	1			T16	3258		T17	3258		T18	3258
valid_sources[0x80]	20630	1			T4	19		T5	19		T6	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8002900

1

T1

16

T2

12

T3

215

values[0x0]

all_enables

biggest_size

10786960

1

T1

16

T2

10

T3

327

values[0x1]

all_enables

biggest_size

10759925

1

T1

11

T2

19

T3

315