Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.52			90.52

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_chk.u_chk	90.52			90.52

---

Module Instance : tb.dut.u_reg.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.52			90.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.52			90.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	232	210	90.52
Total Bits 0->1	116	105	90.52
Total Bits 1->0	116	105	90.52

Ports	4	2	50.00
Port Bits	232	210	90.52
Port Bits 0->1	116	105	90.52
Port Bits 1->0	116	105	90.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[43:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
data_o[49:47]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[53]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
data_o[56:54]	No	No		No		OUTPUT
syndrome_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
err_o[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range