9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | gpio_smoke | 1.630s | 203.392us | 49 | 50 | 98.00 |
| gpio_smoke_no_pullup_pulldown | 1.420s | 1.006ms | 48 | 50 | 96.00 | ||
| gpio_smoke_en_cdc_prim | 1.460s | 316.737us | 50 | 50 | 100.00 | ||
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.380s | 408.603us | 50 | 50 | 100.00 | ||
| V1 | csr_hw_reset | gpio_csr_hw_reset | 0.660s | 27.801us | 5 | 5 | 100.00 |
| V1 | csr_rw | gpio_csr_rw | 0.640s | 11.902us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | gpio_csr_bit_bash | 3.350s | 376.188us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | gpio_csr_aliasing | 0.850s | 130.757us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.530s | 30.838us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.640s | 11.902us | 20 | 20 | 100.00 |
| gpio_csr_aliasing | 0.850s | 130.757us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 252 | 255 | 98.82 | |||
| V2 | direct_and_masked_out | gpio_random_dout_din | 1.540s | 68.865us | 50 | 50 | 100.00 |
| gpio_random_dout_din_no_pullup_pulldown | 1.300s | 161.474us | 48 | 50 | 96.00 | ||
| V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.950s | 58.997us | 48 | 50 | 96.00 |
| V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.450s | 429.184us | 48 | 50 | 96.00 |
| V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.410s | 520.333us | 47 | 50 | 94.00 |
| V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.490s | 168.212us | 48 | 50 | 96.00 |
| V2 | noise_filter_stress | gpio_filter_stress | 27.920s | 1.681ms | 47 | 50 | 94.00 |
| V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 5.830s | 442.277us | 47 | 50 | 94.00 |
| V2 | full_random | gpio_full_random | 1.060s | 77.061us | 48 | 50 | 96.00 |
| V2 | stress_all | gpio_stress_all | 3.859m | 24.685ms | 49 | 50 | 98.00 |
| V2 | alert_test | gpio_alert_test | 0.670s | 80.126us | 49 | 50 | 98.00 |
| V2 | intr_test | gpio_intr_test | 0.700s | 14.528us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | gpio_tl_errors | 3.070s | 132.422us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | gpio_tl_errors | 3.070s | 132.422us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | gpio_csr_rw | 0.640s | 11.902us | 20 | 20 | 100.00 |
| gpio_same_csr_outstanding | 1.010s | 43.585us | 20 | 20 | 100.00 | ||
| gpio_csr_aliasing | 0.850s | 130.757us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.660s | 27.801us | 5 | 5 | 100.00 | ||
| V2 | tl_d_partial_access | gpio_csr_rw | 0.640s | 11.902us | 20 | 20 | 100.00 |
| gpio_same_csr_outstanding | 1.010s | 43.585us | 20 | 20 | 100.00 | ||
| gpio_csr_aliasing | 0.850s | 130.757us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.660s | 27.801us | 5 | 5 | 100.00 | ||
| V2 | TOTAL | 619 | 640 | 96.72 | |||
| V2S | tl_intg_err | gpio_tl_intg_err | 1.420s | 237.689us | 20 | 20 | 100.00 |
| gpio_sec_cm | 0.920s | 89.071us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.420s | 237.689us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 38.710m | 528.018ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 946 | 970 | 97.53 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 7 | 77.78 |
| V2 | 14 | 14 | 4 | 28.57 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.06 | 99.10 | 100.00 | -- | 99.80 | 99.68 | 100.00 |
Exit reason: Error: User command failed Job returned non-zero exit code has 24 failures:
Test gpio_intr_rand_pgm has 2 failures.
22.gpio_intr_rand_pgm.85904535116210114750737001322016529350910097259867008160474507123032597859135
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/22.gpio_intr_rand_pgm/latest/run.log
[make]: simulate
cd /workspace/22.gpio_intr_rand_pgm/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861697855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2861697855
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
32.gpio_intr_rand_pgm.60524944698905362011315365759843030490361429909734666153922559719630503844367
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/32.gpio_intr_rand_pgm/latest/run.log
[make]: simulate
cd /workspace/32.gpio_intr_rand_pgm/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197564943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.197564943
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test gpio_intr_with_filter_rand_intr_event has 2 failures.
22.gpio_intr_with_filter_rand_intr_event.82989167651523177292852697680973127851596104140343039380140084119668052142516
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/22.gpio_intr_with_filter_rand_intr_event/latest/run.log
[make]: simulate
cd /workspace/22.gpio_intr_with_filter_rand_intr_event/latest && /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557763508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3557763508
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
31.gpio_intr_with_filter_rand_intr_event.104120562083031192608413541921324027099839135750501683310488554287354998331288
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/31.gpio_intr_with_filter_rand_intr_event/latest/run.log
[make]: simulate
cd /workspace/31.gpio_intr_with_filter_rand_intr_event/latest && /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636472728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1636472728
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test gpio_rand_intr_trigger has 3 failures.
23.gpio_rand_intr_trigger.114598206257273228263715785757243353755383619651549515641499299734723657844747
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/23.gpio_rand_intr_trigger/latest/run.log
[make]: simulate
cd /workspace/23.gpio_rand_intr_trigger/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214971403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.2214971403
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
33.gpio_rand_intr_trigger.3952129343889458189521576718392244335867609199784026641279887777274818963140
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/33.gpio_rand_intr_trigger/latest/run.log
[make]: simulate
cd /workspace/33.gpio_rand_intr_trigger/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353061060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.3353061060
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test gpio_dout_din_regs_random_rw has 2 failures.
24.gpio_dout_din_regs_random_rw.36294113053278877487764762370217328280931241284925378256093935513345221539316
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/24.gpio_dout_din_regs_random_rw/latest/run.log
[make]: simulate
cd /workspace/24.gpio_dout_din_regs_random_rw/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253024244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3253024244
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
34.gpio_dout_din_regs_random_rw.107286132367986978343007311002574754484887004666673824549826359416647669263826
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/34.gpio_dout_din_regs_random_rw/latest/run.log
[make]: simulate
cd /workspace/34.gpio_dout_din_regs_random_rw/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423795154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2423795154
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test gpio_smoke has 1 failures.
26.gpio_smoke.99516537726194828359168937544050309817886476422558593211182306910478197093196
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/26.gpio_smoke/latest/run.log
[make]: simulate
cd /workspace/26.gpio_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468718924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3468718924
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:30 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 7 more tests.