Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6137486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28882868

1

T1

169

T11

264

T12

95

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13625991	1			T1	40		T11	99		T12	48
values[0x0]	10491980	1			T1	63		T11	97		T12	27
values[0x1]	10902383	1			T1	89		T11	99		T12	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4680472	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30339882

1

T1

184

T11

268

T12

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	129940	1			T13	1		T2	1		T16	1
valid_sources[0x01]	126579	1			T13	5		T14	10		T15	1
valid_sources[0x02]	136257	1			T13	1		T16	4		T3	8
valid_sources[0x03]	131990	1			T1	6		T13	5		T14	9
valid_sources[0x04]	128593	1			T2	1		T16	2		T32	2
valid_sources[0x05]	129915	1			T73	2		T21	13		T77	2
valid_sources[0x06]	126586	1			T16	4		T3	2		T32	1
valid_sources[0x07]	134044	1			T1	3		T12	1		T16	2
valid_sources[0x08]	134103	1			T16	1		T3	6		T20	2
valid_sources[0x09]	134241	1			T12	1		T13	3		T3	7
valid_sources[0x0a]	127708	1			T12	1		T14	6		T15	1
valid_sources[0x0b]	131009	1			T13	2		T16	1		T3	4
valid_sources[0x0c]	134866	1			T1	15		T13	5		T16	5
valid_sources[0x0d]	130853	1			T12	1		T13	4		T14	3
valid_sources[0x0e]	131263	1			T13	1		T16	4		T77	1
valid_sources[0x0f]	128756	1			T13	11		T16	1		T32	2
valid_sources[0x10]	135601	1			T11	141		T12	1		T14	1
valid_sources[0x11]	135979	1			T1	1		T12	2		T14	13
valid_sources[0x12]	133270	1			T14	3		T15	1		T16	2
valid_sources[0x13]	131570	1			T13	1		T16	3		T32	1
valid_sources[0x14]	249346	1			T13	10		T16	3		T3	7
valid_sources[0x15]	133586	1			T12	1		T2	1		T16	2
valid_sources[0x16]	131357	1			T11	7		T13	4		T16	3
valid_sources[0x17]	136103	1			T2	1		T16	2		T17	50
valid_sources[0x18]	133882	1			T13	1		T16	3		T20	1
valid_sources[0x19]	129162	1			T12	1		T13	2		T16	3
valid_sources[0x1a]	135922	1			T1	2		T2	1		T16	3
valid_sources[0x1b]	134273	1			T14	5		T16	3		T32	2
valid_sources[0x1c]	132265	1			T12	1		T16	2		T76	6
valid_sources[0x1d]	131576	1			T1	18		T13	5		T3	1
valid_sources[0x1e]	132420	1			T14	32		T16	3		T3	6
valid_sources[0x1f]	130031	1			T1	2		T14	26		T16	2
valid_sources[0x20]	133945	1			T12	1		T13	1		T16	1
valid_sources[0x21]	130022	1			T13	1		T16	2		T32	1
valid_sources[0x22]	133134	1			T12	2		T13	3		T2	2
valid_sources[0x23]	124683	1			T12	2		T13	1		T16	1
valid_sources[0x24]	128425	1			T13	3		T2	2		T16	3
valid_sources[0x25]	126537	1			T16	1		T3	12		T5	1
valid_sources[0x26]	271566	1			T16	1		T3	6		T5	1
valid_sources[0x27]	127959	1			T16	1		T3	1		T32	1
valid_sources[0x28]	125189	1			T1	2		T12	1		T16	1
valid_sources[0x29]	135472	1			T13	5		T14	7		T2	1
valid_sources[0x2a]	136017	1			T14	5		T16	2		T77	1
valid_sources[0x2b]	137606	1			T16	1		T32	2		T5	1
valid_sources[0x2c]	128027	1			T13	8		T16	2		T32	1
valid_sources[0x2d]	135741	1			T12	1		T13	3		T14	8
valid_sources[0x2e]	134345	1			T16	4		T32	2		T29	4
valid_sources[0x2f]	142109	1			T16	3		T3	3		T32	4
valid_sources[0x30]	132892	1			T13	1		T14	1		T16	1
valid_sources[0x31]	129062	1			T12	1		T14	5		T3	1
valid_sources[0x32]	185378	1			T1	16		T16	4		T4	5
valid_sources[0x33]	268292	1			T16	5		T73	1		T77	1
valid_sources[0x34]	133619	1			T12	2		T16	3		T3	1
valid_sources[0x35]	127822	1			T12	1		T14	3		T16	2
valid_sources[0x36]	147869	1			T13	2		T2	1		T16	2
valid_sources[0x37]	130118	1			T13	2		T2	1		T16	4
valid_sources[0x38]	136443	1			T13	1		T16	2		T76	2
valid_sources[0x39]	135392	1			T11	85		T13	2		T14	5
valid_sources[0x3a]	133854	1			T13	5		T16	1		T5	2
valid_sources[0x3b]	131577	1			T1	1		T12	1		T16	3
valid_sources[0x3c]	132500	1			T12	1		T13	4		T14	3
valid_sources[0x3d]	137773	1			T13	6		T16	6		T3	4
valid_sources[0x3e]	144780	1			T13	3		T14	14		T2	1
valid_sources[0x3f]	146939	1			T13	2		T14	4		T18	4
valid_sources[0x40]	127670	1			T14	3		T16	2		T73	2
valid_sources[0x41]	132892	1			T14	2		T16	2		T24	20
valid_sources[0x42]	124955	1			T13	3		T14	41		T16	3
valid_sources[0x43]	126186	1			T13	4		T16	3		T32	1
valid_sources[0x44]	193627	1			T13	2		T16	2		T3	2
valid_sources[0x45]	138795	1			T13	1		T14	5		T16	1
valid_sources[0x46]	135383	1			T1	9		T11	7		T14	16
valid_sources[0x47]	123239	1			T14	3		T16	5		T3	2
valid_sources[0x48]	133065	1			T16	3		T3	1		T77	1
valid_sources[0x49]	138977	1			T12	1		T13	9		T14	6
valid_sources[0x4a]	133522	1			T1	4		T13	1		T14	2
valid_sources[0x4b]	145841	1			T16	1		T32	3		T4	1
valid_sources[0x4c]	132851	1			T13	2		T16	3		T32	4
valid_sources[0x4d]	123577	1			T21	4		T25	3		T22	1
valid_sources[0x4e]	130335	1			T12	1		T14	2		T16	3
valid_sources[0x4f]	141248	1			T1	5		T2	1		T16	3
valid_sources[0x50]	124056	1			T1	1		T12	3		T14	9
valid_sources[0x51]	124575	1			T15	1		T16	4		T5	8
valid_sources[0x52]	138150	1			T16	1		T3	1		T78	1
valid_sources[0x53]	133476	1			T1	15		T12	3		T13	8
valid_sources[0x54]	132564	1			T13	1		T2	1		T16	2
valid_sources[0x55]	133344	1			T13	6		T14	4		T16	3
valid_sources[0x56]	123869	1			T13	1		T14	4		T16	5
valid_sources[0x57]	140300	1			T14	5		T16	3		T29	3
valid_sources[0x58]	128676	1			T12	1		T14	8		T16	2
valid_sources[0x59]	123275	1			T13	1		T3	8		T4	1
valid_sources[0x5a]	190467	1			T2	2		T16	1		T3	4
valid_sources[0x5b]	127277	1			T16	3		T21	1		T77	1
valid_sources[0x5c]	129309	1			T12	1		T16	1		T3	6
valid_sources[0x5d]	131867	1			T16	6		T32	2		T98	1
valid_sources[0x5e]	130110	1			T12	1		T13	8		T32	3
valid_sources[0x5f]	133022	1			T13	1		T16	2		T24	20
valid_sources[0x60]	124932	1			T13	2		T14	5		T2	2
valid_sources[0x61]	132304	1			T13	2		T2	3		T16	1
valid_sources[0x62]	126555	1			T16	2		T3	2		T32	2
valid_sources[0x63]	127453	1			T15	1		T16	1		T20	1
valid_sources[0x64]	130187	1			T1	4		T13	4		T14	1
valid_sources[0x65]	127553	1			T12	1		T16	1		T32	3
valid_sources[0x66]	131268	1			T16	1		T73	1		T78	1
valid_sources[0x67]	142906	1			T12	1		T15	1		T16	1
valid_sources[0x68]	133489	1			T14	2		T15	2		T16	3
valid_sources[0x69]	131117	1			T13	3		T14	8		T16	4
valid_sources[0x6a]	135486	1			T13	1		T16	2		T32	1
valid_sources[0x6b]	140052	1			T16	1		T73	1		T32	1
valid_sources[0x6c]	136169	1			T12	2		T14	28		T15	1
valid_sources[0x6d]	130151	1			T12	2		T13	3		T15	1
valid_sources[0x6e]	128482	1			T1	1		T12	2		T13	3
valid_sources[0x6f]	132354	1			T16	2		T24	20		T78	1
valid_sources[0x70]	143095	1			T12	1		T16	3		T22	1
valid_sources[0x71]	127343	1			T32	1		T29	2		T83	1
valid_sources[0x72]	130347	1			T15	1		T16	4		T3	5
valid_sources[0x73]	135886	1			T1	2		T13	1		T2	1
valid_sources[0x74]	140657	1			T1	3		T13	5		T16	5
valid_sources[0x75]	123084	1			T13	1		T14	2		T16	1
valid_sources[0x76]	140560	1			T1	2		T12	2		T13	3
valid_sources[0x77]	132036	1			T1	1		T12	1		T16	4
valid_sources[0x78]	140856	1			T1	6		T16	2		T3	2
valid_sources[0x79]	127034	1			T15	1		T78	6		T25	1
valid_sources[0x7a]	131794	1			T13	3		T15	1		T16	2
valid_sources[0x7b]	133535	1			T13	3		T2	1		T25	10
valid_sources[0x7c]	132156	1			T12	1		T13	2		T16	2
valid_sources[0x7d]	129767	1			T1	2		T16	4		T32	1
valid_sources[0x7e]	124099	1			T12	1		T13	1		T16	4
valid_sources[0x7f]	136949	1			T13	1		T16	2		T3	7
valid_sources[0x80]	132561	1			T11	55		T13	1		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7983950

1

T1

39

T11

69

T12

48

values[0x0]

all_enables

biggest_size

10450484

1

T1

62

T11

97

T12

27

values[0x1]

all_enables

biggest_size

10448434

1

T1

68

T11

98

T12

20