Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	320955900	0	0	0
ctrl_en_input_filter_rd_A	320955900	334169	0	0
intr_ctrl_en_falling_rd_A	320955900	351541	0	0
intr_ctrl_en_lvlhigh_rd_A	320955900	334351	0	0
intr_ctrl_en_lvllow_rd_A	320955900	350315	0	0
intr_ctrl_en_rising_rd_A	320955900	334689	0	0
intr_enable_rd_A	320955900	335239	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	334169	0	0
T1	5064	20	0	0
T2	1376	10	0	0
T3	7220	53	0	0
T4	0	14	0	0
T5	0	84	0	0
T6	0	116	0	0
T7	0	6	0	0
T8	0	3	0	0
T9	0	13	0	0
T10	0	92	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	351541	0	0
T1	5064	6	0	0
T2	1376	13	0	0
T3	7220	65	0	0
T4	0	1	0	0
T5	0	117	0	0
T6	0	61	0	0
T7	0	1	0	0
T8	0	13	0	0
T9	0	21	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	0	0	0
T18	0	2	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	334351	0	0
T1	5064	27	0	0
T2	1376	14	0	0
T3	7220	92	0	0
T4	0	18	0	0
T5	0	122	0	0
T6	0	40	0	0
T7	0	12	0	0
T8	0	3	0	0
T9	0	10	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	0	0	0
T19	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	350315	0	0
T1	5064	27	0	0
T2	1376	16	0	0
T3	7220	90	0	0
T4	0	5	0	0
T5	0	107	0	0
T6	0	62	0	0
T7	0	7	0	0
T8	0	1	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	0	0	0
T18	0	3	0	0
T19	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	334689	0	0
T1	5064	10	0	0
T2	1376	11	0	0
T3	7220	52	0	0
T4	0	4	0	0
T5	0	100	0	0
T6	0	70	0	0
T7	0	24	0	0
T8	0	8	0	0
T9	0	5	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	0	0	0
T19	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320955900	335239	0	0
T1	5064	21	0	0
T2	1376	14	0	0
T3	7220	80	0	0
T4	0	8	0	0
T5	0	136	0	0
T11	2851	0	0	0
T12	1052	0	0	0
T13	1781	0	0	0
T14	3286	0	0	0
T15	1245	0	0	0
T16	4954	0	0	0
T17	1936	32	0	0
T20	0	8	0	0
T21	0	26	0	0
T22	0	1	0	0
T23	0	3	0	0