Line Coverage for Module :
gpio
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 8 | 8 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 99 | 8 | 8 | 100.00 |
ALWAYS | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
63 |
1 |
1 |
66 |
1 |
1 |
67 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
|
|
|
MISSING_ELSE |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
108 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
149 |
1 |
1 |
Cond Coverage for Module :
gpio
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 149
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T14,T36 |
1 | 0 | Covered | T20,T21,T22 |
1 | 1 | Covered | T20,T14,T36 |
Toggle Coverage for Module :
gpio
| Total | Covered | Percent |
Totals |
30 |
30 |
100.00 |
Total Bits |
588 |
588 |
100.00 |
Total Bits 0->1 |
294 |
294 |
100.00 |
Total Bits 1->0 |
294 |
294 |
100.00 |
| | | |
Ports |
30 |
30 |
100.00 |
Port Bits |
588 |
588 |
100.00 |
Port Bits 0->1 |
294 |
294 |
100.00 |
Port Bits 1->0 |
294 |
294 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
rst_ni |
Yes |
Yes |
T12,T3,T17 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T21,T25,T27 |
Yes |
T21,T25,T27 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T21,T23,T24 |
Yes |
T21,T23,T24 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T12,T28,T29 |
Yes |
T12,T28,T29 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T21,*T22,*T23 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T21,T23,T24 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T21,*T22,*T23 |
Yes |
T20,T21,T22 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
OUTPUT |
intr_gpio_o[31:0] |
Yes |
Yes |
T21,T23,T24 |
Yes |
T21,T23,T24 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T20,T14,T36 |
Yes |
T20,T14,T36 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T20,T21,T22 |
Yes |
T20,T21,T22 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T20,T14,T36 |
Yes |
T20,T14,T36 |
OUTPUT |
cio_gpio_i[31:0] |
Yes |
Yes |
T21,T22,T23 |
Yes |
T21,T22,T23 |
INPUT |
cio_gpio_o[31:0] |
Yes |
Yes |
T22,T1,T2 |
Yes |
T22,T1,T2 |
OUTPUT |
cio_gpio_en_o[31:0] |
Yes |
Yes |
T22,T1,T2 |
Yes |
T22,T1,T2 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
gpio
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
IF |
99 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (reg2hw.direct_out.qe)
-3-: 80 if (reg2hw.masked_out_upper.data.qe)
-4-: 84 if (reg2hw.masked_out_lower.data.qe)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T20,T21,T22 |
0 |
1 |
- |
- |
Covered |
T22,T1,T2 |
0 |
0 |
1 |
- |
Covered |
T22,T1,T2 |
0 |
0 |
0 |
1 |
Covered |
T22,T1,T2 |
0 |
0 |
0 |
0 |
Covered |
T20,T21,T22 |
LineNo. Expression
-1-: 99 if ((!rst_ni))
-2-: 101 if (reg2hw.direct_oe.qe)
-3-: 103 if (reg2hw.masked_oe_upper.data.qe)
-4-: 107 if (reg2hw.masked_oe_lower.data.qe)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T20,T21,T22 |
0 |
1 |
- |
- |
Covered |
T22,T24,T25 |
0 |
0 |
1 |
- |
Covered |
T22,T1,T2 |
0 |
0 |
0 |
1 |
Covered |
T22,T1,T2 |
0 |
0 |
0 |
0 |
Covered |
T20,T21,T22 |
Assert Coverage for Module :
gpio
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138924673 |
138599942 |
0 |
0 |
T1 |
25248 |
25148 |
0 |
0 |
T2 |
20621 |
20551 |
0 |
0 |
T20 |
1007 |
927 |
0 |
0 |
T21 |
13748 |
13678 |
0 |
0 |
T22 |
5119 |
5050 |
0 |
0 |
T23 |
70751 |
70653 |
0 |
0 |
T24 |
5360 |
5292 |
0 |
0 |
T25 |
3169 |
3094 |
0 |
0 |
T26 |
66442 |
66347 |
0 |
0 |
T27 |
3271 |
3208 |
0 |
0 |
CioGpioEnOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138924673 |
138599942 |
0 |
0 |
T1 |
25248 |
25148 |
0 |
0 |
T2 |
20621 |
20551 |
0 |
0 |
T20 |
1007 |
927 |
0 |
0 |
T21 |
13748 |
13678 |
0 |
0 |
T22 |
5119 |
5050 |
0 |
0 |
T23 |
70751 |
70653 |
0 |
0 |
T24 |
5360 |
5292 |
0 |
0 |
T25 |
3169 |
3094 |
0 |
0 |
T26 |
66442 |
66347 |
0 |
0 |
T27 |
3271 |
3208 |
0 |
0 |
CioGpioOKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138924673 |
138599942 |
0 |
0 |
T1 |
25248 |
25148 |
0 |
0 |
T2 |
20621 |
20551 |
0 |
0 |
T20 |
1007 |
927 |
0 |
0 |
T21 |
13748 |
13678 |
0 |
0 |
T22 |
5119 |
5050 |
0 |
0 |
T23 |
70751 |
70653 |
0 |
0 |
T24 |
5360 |
5292 |
0 |
0 |
T25 |
3169 |
3094 |
0 |
0 |
T26 |
66442 |
66347 |
0 |
0 |
T27 |
3271 |
3208 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138924673 |
100 |
0 |
0 |
T29 |
464356 |
0 |
0 |
0 |
T33 |
7339 |
30 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
0 |
10 |
0 |
0 |
T42 |
0 |
30 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
3266 |
0 |
0 |
0 |
T45 |
2639 |
0 |
0 |
0 |
T46 |
3879 |
0 |
0 |
0 |
T47 |
10390 |
0 |
0 |
0 |
T48 |
3561 |
0 |
0 |
0 |
T49 |
3796 |
0 |
0 |
0 |
T50 |
5921 |
0 |
0 |
0 |
T51 |
14179 |
0 |
0 |
0 |
IntrGpioKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138924673 |
138599942 |
0 |
0 |
T1 |
25248 |
25148 |
0 |
0 |
T2 |
20621 |
20551 |
0 |
0 |
T20 |
1007 |
927 |
0 |
0 |
T21 |
13748 |
13678 |
0 |
0 |
T22 |
5119 |
5050 |
0 |
0 |
T23 |
70751 |
70653 |
0 |
0 |
T24 |
5360 |
5292 |
0 |
0 |
T25 |
3169 |
3094 |
0 |
0 |
T26 |
66442 |
66347 |
0 |
0 |
T27 |
3271 |
3208 |
0 |
0 |