Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	139494100	0	0	0
ctrl_en_input_filter_rd_A	139494100	63529	0	0
intr_ctrl_en_falling_rd_A	139494100	64397	0	0
intr_ctrl_en_lvlhigh_rd_A	139494100	62969	0	0
intr_ctrl_en_lvllow_rd_A	139494100	64117	0	0
intr_ctrl_en_rising_rd_A	139494100	63243	0	0
intr_enable_rd_A	139494100	64563	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	63529	0	0
T1	25248	183	0	0
T2	20621	134	0	0
T3	403552	1315	0	0
T4	0	2591	0	0
T5	0	3	0	0
T6	0	1665	0	0
T7	0	95	0	0
T8	0	3	0	0
T9	0	125	0	0
T10	0	2793	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	64397	0	0
T1	25248	140	0	0
T2	20621	103	0	0
T3	403552	1181	0	0
T4	0	2476	0	0
T5	0	15	0	0
T6	0	1524	0	0
T7	0	107	0	0
T9	0	109	0	0
T10	0	2546	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0
T18	0	4561	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	62969	0	0
T1	25248	194	0	0
T2	20621	114	0	0
T3	403552	1390	0	0
T4	0	2536	0	0
T6	0	1654	0	0
T7	0	127	0	0
T8	0	9	0	0
T9	0	102	0	0
T10	0	2490	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0
T19	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	64117	0	0
T1	25248	131	0	0
T2	20621	63	0	0
T3	403552	1362	0	0
T4	0	2632	0	0
T5	0	1	0	0
T6	0	1674	0	0
T7	0	128	0	0
T8	0	8	0	0
T9	0	113	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0
T19	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	63243	0	0
T1	25248	162	0	0
T2	20621	78	0	0
T3	403552	1271	0	0
T4	0	2499	0	0
T6	0	1774	0	0
T7	0	110	0	0
T8	0	3	0	0
T9	0	100	0	0
T10	0	2765	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0
T19	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139494100	64563	0	0
T1	25248	174	0	0
T2	20621	93	0	0
T3	403552	1225	0	0
T4	0	2497	0	0
T6	0	1760	0	0
T7	0	112	0	0
T8	0	7	0	0
T9	0	185	0	0
T10	0	2569	0	0
T11	6320	0	0	0
T12	275905	0	0	0
T13	3106	0	0	0
T14	838	0	0	0
T15	6743	0	0	0
T16	5628	0	0	0
T17	542498	0	0	0
T19	0	4	0	0