Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3023531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13521247

1

T26

293

T27

695

T28

521

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6606181	1			T26	107		T27	837		T28	603
values[0x0]	4883059	1			T26	119		T27	143		T28	101
values[0x1]	5055538	1			T26	123		T27	147		T28	110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2323278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14221500

1

T26

299

T27

783

T28

586

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62990	1			T27	10		T1	683		T11	1
valid_sources[0x01]	60769	1			T27	8		T28	4		T1	654
valid_sources[0x02]	61772	1			T28	4		T1	697		T11	1
valid_sources[0x03]	72280	1			T27	3		T28	3		T30	1
valid_sources[0x04]	57033	1			T27	1		T28	6		T30	1
valid_sources[0x05]	60522	1			T27	1		T28	2		T1	635
valid_sources[0x06]	52072	1			T27	5		T28	3		T1	636
valid_sources[0x07]	57757	1			T27	7		T1	605		T14	3
valid_sources[0x08]	65447	1			T27	10		T28	4		T30	1
valid_sources[0x09]	56143	1			T27	4		T28	1		T1	617
valid_sources[0x0a]	56559	1			T27	1		T28	2		T1	605
valid_sources[0x0b]	62279	1			T28	5		T1	691		T14	5
valid_sources[0x0c]	59578	1			T27	9		T1	691		T11	1
valid_sources[0x0d]	57049	1			T28	1		T1	576		T14	5
valid_sources[0x0e]	54450	1			T28	3		T1	675		T14	2
valid_sources[0x0f]	52163	1			T27	1		T28	1		T30	10
valid_sources[0x10]	59234	1			T27	2		T28	6		T1	649
valid_sources[0x11]	54924	1			T27	10		T28	2		T30	1
valid_sources[0x12]	55622	1			T27	1		T1	633		T11	2
valid_sources[0x13]	54035	1			T27	2		T28	3		T1	607
valid_sources[0x14]	56130	1			T27	4		T28	4		T30	1
valid_sources[0x15]	58463	1			T28	2		T1	710		T11	3
valid_sources[0x16]	58163	1			T27	9		T28	1		T1	655
valid_sources[0x17]	67545	1			T28	3		T1	675		T11	1
valid_sources[0x18]	55802	1			T27	4		T28	7		T1	617
valid_sources[0x19]	62341	1			T27	4		T28	6		T1	661
valid_sources[0x1a]	59347	1			T27	2		T1	634		T11	1
valid_sources[0x1b]	65065	1			T28	1		T1	670		T11	2
valid_sources[0x1c]	61548	1			T27	10		T28	3		T1	656
valid_sources[0x1d]	56324	1			T27	12		T28	1		T1	678
valid_sources[0x1e]	64603	1			T27	4		T28	4		T1	670
valid_sources[0x1f]	57886	1			T27	2		T28	3		T1	686
valid_sources[0x20]	54696	1			T27	12		T28	3		T1	648
valid_sources[0x21]	55758	1			T27	6		T28	2		T1	597
valid_sources[0x22]	62671	1			T27	4		T28	5		T30	1
valid_sources[0x23]	60081	1			T27	2		T28	3		T30	2
valid_sources[0x24]	69929	1			T28	3		T30	1		T1	682
valid_sources[0x25]	70769	1			T27	19		T28	2		T1	648
valid_sources[0x26]	55379	1			T28	2		T1	665		T14	2
valid_sources[0x27]	64519	1			T27	2		T28	6		T30	1
valid_sources[0x28]	53999	1			T27	2		T28	1		T1	640
valid_sources[0x29]	68944	1			T27	7		T28	1		T1	680
valid_sources[0x2a]	65333	1			T27	15		T28	7		T1	650
valid_sources[0x2b]	56435	1			T27	3		T28	3		T1	644
valid_sources[0x2c]	60362	1			T27	1		T28	6		T1	692
valid_sources[0x2d]	55109	1			T27	4		T28	4		T1	675
valid_sources[0x2e]	59979	1			T27	8		T28	6		T30	1
valid_sources[0x2f]	60422	1			T27	2		T28	5		T1	683
valid_sources[0x30]	51646	1			T28	2		T1	640		T11	1
valid_sources[0x31]	62967	1			T27	3		T28	6		T1	651
valid_sources[0x32]	63346	1			T27	5		T28	2		T1	636
valid_sources[0x33]	151598	1			T28	3		T1	684		T11	1
valid_sources[0x34]	64960	1			T27	3		T28	3		T1	643
valid_sources[0x35]	58271	1			T28	8		T1	667		T14	2
valid_sources[0x36]	70210	1			T27	2		T28	2		T30	1
valid_sources[0x37]	55772	1			T27	1		T28	3		T1	654
valid_sources[0x38]	59762	1			T28	7		T1	676		T11	1
valid_sources[0x39]	56122	1			T27	10		T28	3		T1	629
valid_sources[0x3a]	61557	1			T26	349		T27	6		T28	2
valid_sources[0x3b]	60351	1			T27	11		T28	1		T1	639
valid_sources[0x3c]	52041	1			T27	7		T28	1		T1	625
valid_sources[0x3d]	57821	1			T27	1		T28	2		T30	1
valid_sources[0x3e]	57279	1			T27	4		T28	2		T1	702
valid_sources[0x3f]	53903	1			T27	1		T28	4		T30	1
valid_sources[0x40]	53769	1			T27	2		T28	4		T30	1
valid_sources[0x41]	54124	1			T27	14		T28	5		T1	684
valid_sources[0x42]	56833	1			T27	1		T28	3		T1	664
valid_sources[0x43]	62269	1			T27	5		T28	3		T1	666
valid_sources[0x44]	59849	1			T27	6		T28	6		T1	657
valid_sources[0x45]	54851	1			T27	14		T28	4		T1	652
valid_sources[0x46]	54157	1			T27	13		T28	3		T30	1
valid_sources[0x47]	62840	1			T28	3		T1	700		T11	1
valid_sources[0x48]	59208	1			T27	5		T28	3		T1	604
valid_sources[0x49]	85320	1			T27	3		T28	5		T30	1
valid_sources[0x4a]	60745	1			T28	5		T1	641		T14	3
valid_sources[0x4b]	59625	1			T27	4		T28	8		T30	1
valid_sources[0x4c]	56192	1			T27	6		T28	3		T1	671
valid_sources[0x4d]	62486	1			T27	1		T28	4		T1	671
valid_sources[0x4e]	55065	1			T27	7		T28	2		T1	680
valid_sources[0x4f]	54837	1			T27	7		T28	2		T30	1
valid_sources[0x50]	66839	1			T27	1		T28	7		T30	1
valid_sources[0x51]	54496	1			T27	5		T1	662		T11	1
valid_sources[0x52]	67646	1			T27	1		T28	2		T1	653
valid_sources[0x53]	66069	1			T27	7		T28	2		T30	2
valid_sources[0x54]	60351	1			T28	3		T1	624		T11	1
valid_sources[0x55]	53547	1			T27	7		T28	3		T1	718
valid_sources[0x56]	59787	1			T27	8		T28	5		T1	650
valid_sources[0x57]	61575	1			T27	4		T28	1		T1	596
valid_sources[0x58]	61198	1			T28	3		T1	669		T11	2
valid_sources[0x59]	52733	1			T27	3		T28	4		T1	642
valid_sources[0x5a]	56328	1			T27	12		T28	4		T1	611
valid_sources[0x5b]	173387	1			T27	7		T28	1		T1	619
valid_sources[0x5c]	59551	1			T27	1		T1	640		T14	9
valid_sources[0x5d]	57283	1			T27	12		T28	2		T30	1
valid_sources[0x5e]	60546	1			T27	6		T28	5		T1	618
valid_sources[0x5f]	61915	1			T27	5		T28	2		T1	620
valid_sources[0x60]	58186	1			T28	3		T1	634		T11	2
valid_sources[0x61]	53609	1			T27	5		T28	1		T1	631
valid_sources[0x62]	59323	1			T27	1		T28	3		T1	698
valid_sources[0x63]	163365	1			T27	4		T28	1		T29	181
valid_sources[0x64]	64545	1			T27	5		T28	2		T1	629
valid_sources[0x65]	58360	1			T27	8		T28	3		T30	1
valid_sources[0x66]	65701	1			T27	4		T28	3		T1	661
valid_sources[0x67]	59675	1			T27	10		T28	2		T1	604
valid_sources[0x68]	59507	1			T27	1		T28	7		T1	620
valid_sources[0x69]	63397	1			T27	9		T28	3		T1	650
valid_sources[0x6a]	69386	1			T28	4		T30	1		T1	657
valid_sources[0x6b]	70625	1			T27	3		T28	3		T1	687
valid_sources[0x6c]	62210	1			T27	15		T28	2		T1	620
valid_sources[0x6d]	74512	1			T27	5		T28	3		T30	1
valid_sources[0x6e]	57077	1			T27	7		T28	1		T1	693
valid_sources[0x6f]	53755	1			T27	2		T28	1		T1	630
valid_sources[0x70]	72489	1			T27	11		T28	7		T1	641
valid_sources[0x71]	131564	1			T28	1		T30	5		T1	692
valid_sources[0x72]	56180	1			T27	8		T28	6		T1	658
valid_sources[0x73]	63050	1			T28	5		T30	2		T1	655
valid_sources[0x74]	46124	1			T28	3		T30	1		T1	648
valid_sources[0x75]	70615	1			T27	2		T28	8		T1	610
valid_sources[0x76]	56903	1			T30	1		T1	644		T11	1
valid_sources[0x77]	68239	1			T28	2		T30	1		T1	678
valid_sources[0x78]	62141	1			T27	7		T28	7		T1	731
valid_sources[0x79]	136157	1			T28	2		T1	654		T14	4
valid_sources[0x7a]	63446	1			T28	3		T1	594		T11	1
valid_sources[0x7b]	58901	1			T27	3		T28	2		T1	671
valid_sources[0x7c]	58838	1			T27	2		T28	1		T1	654
valid_sources[0x7d]	56847	1			T28	1		T1	634		T14	2
valid_sources[0x7e]	56835	1			T27	2		T28	9		T1	663
valid_sources[0x7f]	53082	1			T27	2		T30	1		T1	671
valid_sources[0x80]	56798	1			T27	2		T28	5		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3790644

1

T26

51

T27

405

T28

310

values[0x0]

all_enables

biggest_size

4865526

1

T26

119

T27

143

T28

101

values[0x1]

all_enables

biggest_size

4865077

1

T26

123

T27

147

T28

110