Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	143486621	0	0	0
ctrl_en_input_filter_rd_A	143486621	69288	0	0
intr_ctrl_en_falling_rd_A	143486621	70024	0	0
intr_ctrl_en_lvlhigh_rd_A	143486621	68886	0	0
intr_ctrl_en_lvllow_rd_A	143486621	70267	0	0
intr_ctrl_en_rising_rd_A	143486621	67493	0	0
intr_enable_rd_A	143486621	68179	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	69288	0	0
T1	195697	5187	0	0
T2	0	13113	0	0
T3	0	5226	0	0
T4	0	37	0	0
T5	0	5539	0	0
T6	0	45	0	0
T7	0	266	0	0
T8	0	6419	0	0
T9	0	1854	0	0
T10	0	4	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	70024	0	0
T1	195697	4892	0	0
T2	0	13657	0	0
T3	0	5213	0	0
T4	0	75	0	0
T5	0	5497	0	0
T6	0	32	0	0
T7	0	334	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	68886	0	0
T1	195697	5131	0	0
T2	0	13087	0	0
T3	0	5456	0	0
T4	0	94	0	0
T5	0	5475	0	0
T6	0	31	0	0
T7	0	355	0	0
T8	0	6233	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0
T22	0	6	0	0
T23	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	70267	0	0
T1	195697	4853	0	0
T2	0	14167	0	0
T3	0	5055	0	0
T4	0	87	0	0
T5	0	5440	0	0
T6	0	35	0	0
T7	0	285	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0
T23	0	5	0	0
T24	0	14	0	0
T25	0	8	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	67493	0	0
T1	195697	5099	0	0
T2	0	13172	0	0
T3	0	5075	0	0
T4	0	42	0	0
T5	0	5346	0	0
T6	0	30	0	0
T7	0	284	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0
T21	0	1	0	0
T23	0	6	0	0
T25	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143486621	68179	0	0
T1	195697	4956	0	0
T2	0	12680	0	0
T3	0	5265	0	0
T4	0	55	0	0
T5	0	5268	0	0
T6	0	61	0	0
T7	0	294	0	0
T11	1890	0	0	0
T12	1016	0	0	0
T13	3267	0	0	0
T14	6796	0	0	0
T15	5210	0	0	0
T16	4118	0	0	0
T17	3414	0	0	0
T18	4875	0	0	0
T19	5045	0	0	0
T22	0	3	0	0
T23	0	4	0	0
T24	0	2	0	0