Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : gpio
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.56 99.06 99.24 100.00 99.80 99.68


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_filter[0].u_filter 100.00 100.00 100.00 100.00
gen_filter[10].u_filter 100.00 100.00 100.00 100.00
gen_filter[11].u_filter 100.00 100.00 100.00 100.00
gen_filter[12].u_filter 100.00 100.00 100.00 100.00
gen_filter[13].u_filter 100.00 100.00 100.00 100.00
gen_filter[14].u_filter 100.00 100.00 100.00 100.00
gen_filter[15].u_filter 100.00 100.00 100.00 100.00
gen_filter[16].u_filter 100.00 100.00 100.00 100.00
gen_filter[17].u_filter 100.00 100.00 100.00 100.00
gen_filter[18].u_filter 100.00 100.00 100.00 100.00
gen_filter[19].u_filter 100.00 100.00 100.00 100.00
gen_filter[1].u_filter 100.00 100.00 100.00 100.00
gen_filter[20].u_filter 100.00 100.00 100.00 100.00
gen_filter[21].u_filter 100.00 100.00 100.00 100.00
gen_filter[22].u_filter 100.00 100.00 100.00 100.00
gen_filter[23].u_filter 100.00 100.00 100.00 100.00
gen_filter[24].u_filter 100.00 100.00 100.00 100.00
gen_filter[25].u_filter 100.00 100.00 100.00 100.00
gen_filter[26].u_filter 100.00 100.00 100.00 100.00
gen_filter[27].u_filter 100.00 100.00 100.00 100.00
gen_filter[28].u_filter 100.00 100.00 100.00 100.00
gen_filter[29].u_filter 100.00 100.00 100.00 100.00
gen_filter[2].u_filter 100.00 100.00 100.00 100.00
gen_filter[30].u_filter 100.00 100.00 100.00 100.00
gen_filter[31].u_filter 100.00 100.00 100.00 100.00
gen_filter[3].u_filter 100.00 100.00 100.00 100.00
gen_filter[4].u_filter 100.00 100.00 100.00 100.00
gen_filter[5].u_filter 100.00 100.00 100.00 100.00
gen_filter[6].u_filter 100.00 100.00 100.00 100.00
gen_filter[7].u_filter 100.00 100.00 100.00 100.00
gen_filter[8].u_filter 100.00 100.00 100.00 100.00
gen_filter[9].u_filter 100.00 100.00 100.00 100.00
gpio_csr_assert 85.71 85.71
intr_hw 100.00 100.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 99.03 97.69 98.53 100.00 98.95 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : gpio
Line No.TotalCoveredPercent
TOTAL3232100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7211100.00
ALWAYS7688100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
ALWAYS9988100.00
ALWAYS11611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
63 1 1
66 1 1
67 1 1
69 1 1
70 1 1
72 1 1
76 1 1
77 1 1
78 1 1
79 1 1
80 1 1
81 1 1
84 1 1
85 1 1
MISSING_ELSE
92 1 1
93 1 1
95 1 1
99 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
116 1 1
137 1 1
138 1 1
139 1 1
140 1 1
142 1 1
149 1 1


Cond Coverage for Module : gpio
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       149
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT33,T34,T35
10CoveredT22,T23,T1
11CoveredT33,T34,T35

Toggle Coverage for Module : gpio
TotalCoveredPercent
Totals 30 30 100.00
Total Bits 588 588 100.00
Total Bits 0->1 294 294 100.00
Total Bits 1->0 294 294 100.00

Ports 30 30 100.00
Port Bits 588 588 100.00
Port Bits 0->1 294 294 100.00
Port Bits 1->0 294 294 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
rst_ni Yes Yes T11,T12,T2 Yes T22,T23,T1 INPUT
tl_i.d_ready Yes Yes T22,T1,T11 Yes T22,T23,T1 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T23,T1,T11 Yes T23,T1,T11 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_mask[3:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_address[31:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_source[7:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_size[1:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_i.a_valid Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
tl_o.a_ready Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
tl_o.d_error Yes Yes T24,T25,T26 Yes T24,T25,T26 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T22,*T23,*T1 Yes T22,T23,T1 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T22,T1,T11 Yes T22,T23,T1 OUTPUT
tl_o.d_size[1:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T22,*T23,*T1 Yes T22,T23,T1 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
intr_gpio_o[31:0] Yes Yes T23,T1,T11 Yes T23,T1,T11 OUTPUT
alert_rx_i[0].ack_n Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
alert_rx_i[0].ack_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T22,T23,T1 Yes T22,T23,T1 OUTPUT
alert_tx_o[0].alert_p Yes Yes T33,T34,T35 Yes T33,T34,T35 OUTPUT
cio_gpio_i[31:0] Yes Yes T22,T23,T1 Yes T22,T23,T1 INPUT
cio_gpio_o[31:0] Yes Yes T22,T1,T11 Yes T22,T1,T11 OUTPUT
cio_gpio_en_o[31:0] Yes Yes T22,T1,T11 Yes T22,T1,T11 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : gpio
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 76 5 5 100.00
IF 99 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 78 if (reg2hw.direct_out.qe) -3-: 80 if (reg2hw.masked_out_upper.data.qe) -4-: 84 if (reg2hw.masked_out_lower.data.qe)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T22,T23,T1
0 1 - - Covered T22,T1,T11
0 0 1 - Covered T22,T1,T11
0 0 0 1 Covered T22,T1,T11
0 0 0 0 Covered T22,T23,T1


LineNo. Expression -1-: 99 if ((!rst_ni)) -2-: 101 if (reg2hw.direct_oe.qe) -3-: 103 if (reg2hw.masked_oe_upper.data.qe) -4-: 107 if (reg2hw.masked_oe_lower.data.qe)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T22,T23,T1
0 1 - - Covered T22,T23,T1
0 0 1 - Covered T22,T1,T11
0 0 0 1 Covered T22,T1,T11
0 0 0 0 Covered T22,T23,T1


Assert Coverage for Module : gpio
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 190881473 190536369 0 0
CioGpioEnOKnown 190881473 190536369 0 0
CioGpioOKnown 190881473 190536369 0 0
FpvSecCmRegWeOnehotCheck_A 190881473 100 0 0
IntrGpioKnown 190881473 190536369 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190881473 190536369 0 0
T1 45842 45789 0 0
T2 5394 4195 0 0
T11 773461 769680 0 0
T12 2770 2487 0 0
T13 5131 5078 0 0
T14 2750 2677 0 0
T15 6285 6228 0 0
T16 3372 2545 0 0
T22 5238 5172 0 0
T23 6246 6170 0 0

CioGpioEnOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 190881473 190536369 0 0
T1 45842 45789 0 0
T2 5394 4195 0 0
T11 773461 769680 0 0
T12 2770 2487 0 0
T13 5131 5078 0 0
T14 2750 2677 0 0
T15 6285 6228 0 0
T16 3372 2545 0 0
T22 5238 5172 0 0
T23 6246 6170 0 0

CioGpioOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 190881473 190536369 0 0
T1 45842 45789 0 0
T2 5394 4195 0 0
T11 773461 769680 0 0
T12 2770 2487 0 0
T13 5131 5078 0 0
T14 2750 2677 0 0
T15 6285 6228 0 0
T16 3372 2545 0 0
T22 5238 5172 0 0
T23 6246 6170 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190881473 100 0 0
T30 9942 30 0 0
T31 0 30 0 0
T32 0 10 0 0
T41 0 10 0 0
T42 0 20 0 0
T43 3355 0 0 0
T44 39156 0 0 0
T45 1080 0 0 0
T46 963 0 0 0
T47 1258 0 0 0
T48 2681 0 0 0
T49 2228 0 0 0
T50 14114 0 0 0
T51 7875 0 0 0

IntrGpioKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 190881473 190536369 0 0
T1 45842 45789 0 0
T2 5394 4195 0 0
T11 773461 769680 0 0
T12 2770 2487 0 0
T13 5131 5078 0 0
T14 2750 2677 0 0
T15 6285 6228 0 0
T16 3372 2545 0 0
T22 5238 5172 0 0
T23 6246 6170 0 0

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