Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	191406615	0	0	0
ctrl_en_input_filter_rd_A	191406615	89908	0	0
intr_ctrl_en_falling_rd_A	191406615	91950	0	0
intr_ctrl_en_lvlhigh_rd_A	191406615	88699	0	0
intr_ctrl_en_lvllow_rd_A	191406615	89909	0	0
intr_ctrl_en_rising_rd_A	191406615	89305	0	0
intr_enable_rd_A	191406615	88575	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	89908	0	0
T1	45842	252	0	0
T2	5394	3	0	0
T3	0	4	0	0
T4	0	2452	0	0
T5	0	99	0	0
T6	0	3346	0	0
T7	0	16	0	0
T8	0	190	0	0
T9	0	71	0	0
T10	0	103	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	91950	0	0
T1	45842	210	0	0
T2	5394	0	0	0
T4	0	2641	0	0
T5	0	126	0	0
T6	0	3707	0	0
T7	0	4	0	0
T8	0	231	0	0
T9	0	130	0	0
T10	0	114	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0
T19	0	145	0	0
T20	0	3	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	88699	0	0
T1	45842	201	0	0
T2	5394	7	0	0
T4	0	2528	0	0
T5	0	111	0	0
T6	0	3501	0	0
T7	0	2	0	0
T8	0	180	0	0
T9	0	155	0	0
T10	0	126	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0
T19	0	150	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	89909	0	0
T1	45842	177	0	0
T2	5394	0	0	0
T4	0	2248	0	0
T5	0	130	0	0
T6	0	3627	0	0
T7	0	2	0	0
T8	0	241	0	0
T9	0	124	0	0
T10	0	43	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0
T19	0	142	0	0
T20	0	7	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	89305	0	0
T1	45842	236	0	0
T2	5394	0	0	0
T4	0	2356	0	0
T5	0	114	0	0
T6	0	3501	0	0
T7	0	1	0	0
T8	0	224	0	0
T9	0	174	0	0
T10	0	92	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0
T19	0	155	0	0
T20	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191406615	88575	0	0
T1	45842	209	0	0
T2	5394	2	0	0
T4	0	2411	0	0
T5	0	87	0	0
T6	0	3370	0	0
T8	0	158	0	0
T9	0	104	0	0
T10	0	109	0	0
T11	773461	0	0	0
T12	2770	0	0	0
T13	5131	0	0	0
T14	2750	0	0	0
T15	6285	0	0	0
T16	3372	0	0	0
T17	5466	0	0	0
T18	9325	0	0	0
T19	0	106	0	0
T21	0	79	0	0