Unified Coverage Report :: Module :: gpio

Module : gpio

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	99.06	99.24	100.00		99.80	99.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_filter[0].u_filter	100.00	100.00	100.00			100.00
gen_filter[10].u_filter	100.00	100.00	100.00			100.00
gen_filter[11].u_filter	100.00	100.00	100.00			100.00
gen_filter[12].u_filter	100.00	100.00	100.00			100.00
gen_filter[13].u_filter	100.00	100.00	100.00			100.00
gen_filter[14].u_filter	100.00	100.00	100.00			100.00
gen_filter[15].u_filter	100.00	100.00	100.00			100.00
gen_filter[16].u_filter	100.00	100.00	100.00			100.00
gen_filter[17].u_filter	100.00	100.00	100.00			100.00
gen_filter[18].u_filter	100.00	100.00	100.00			100.00
gen_filter[19].u_filter	100.00	100.00	100.00			100.00
gen_filter[1].u_filter	100.00	100.00	100.00			100.00
gen_filter[20].u_filter	100.00	100.00	100.00			100.00
gen_filter[21].u_filter	100.00	100.00	100.00			100.00
gen_filter[22].u_filter	100.00	100.00	100.00			100.00
gen_filter[23].u_filter	100.00	100.00	100.00			100.00
gen_filter[24].u_filter	100.00	100.00	100.00			100.00
gen_filter[25].u_filter	100.00	100.00	100.00			100.00
gen_filter[26].u_filter	100.00	100.00	100.00			100.00
gen_filter[27].u_filter	100.00	100.00	100.00			100.00
gen_filter[28].u_filter	100.00	100.00	100.00			100.00
gen_filter[29].u_filter	100.00	100.00	100.00			100.00
gen_filter[2].u_filter	100.00	100.00	100.00			100.00
gen_filter[30].u_filter	100.00	100.00	100.00			100.00
gen_filter[31].u_filter	100.00	100.00	100.00			100.00
gen_filter[3].u_filter	100.00	100.00	100.00			100.00
gen_filter[4].u_filter	100.00	100.00	100.00			100.00
gen_filter[5].u_filter	100.00	100.00	100.00			100.00
gen_filter[6].u_filter	100.00	100.00	100.00			100.00
gen_filter[7].u_filter	100.00	100.00	100.00			100.00
gen_filter[8].u_filter	100.00	100.00	100.00			100.00
gen_filter[9].u_filter	100.00	100.00	100.00			100.00
gpio_csr_assert	85.71						85.71
intr_hw	100.00	100.00				100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.03	97.69	98.53	100.00		98.95	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : gpio

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	8	8	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	99	8	8	100.00
ALWAYS	116	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	149	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
63	1	1
66	1	1
67	1	1
69	1	1
70	1	1
72	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
84	1	1
85	1	1
			MISSING_ELSE
92	1	1
93	1	1
95	1	1
99	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
108	1	1
			MISSING_ELSE
116	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
149	1	1

---

Cond Coverage for Module : gpio

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       149
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T24,T25,T26
1	1	Covered	T37,T38,T39

---

Toggle Coverage for Module : gpio

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	588	588	100.00
Total Bits 0->1	294	294	100.00
Total Bits 1->0	294	294	100.00

Ports	30	30	100.00
Port Bits	588	588	100.00
Port Bits 0->1	294	294	100.00
Port Bits 1->0	294	294	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
rst_ni	Yes	Yes	T27,T28,T22	Yes	T24,T25,T26	INPUT
tl_i.d_ready	Yes	Yes	T1,T11,T15	Yes	T24,T25,T26	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T12,T15,T19	Yes	T12,T15,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_address[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_source[7:0]	Yes	Yes	T24,T26,T1	Yes	T24,T26,T1	INPUT
tl_i.a_size[1:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_i.a_valid	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
tl_o.a_ready	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T24,*T25,*T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T24,T26,T1	Yes	T24,T26,T1	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T24,*T25,*T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
intr_gpio_o[31:0]	Yes	Yes	T24,T26,T1	Yes	T24,T26,T1	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
cio_gpio_i[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cio_gpio_o[31:0]	Yes	Yes	T25,T26,T1	Yes	T25,T26,T1	OUTPUT
cio_gpio_en_o[31:0]	Yes	Yes	T25,T26,T1	Yes	T25,T26,T1	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : gpio

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	76	5	5	100.00
IF	99	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (reg2hw.direct_out.qe)
-3-:	80	if (reg2hw.masked_out_upper.data.qe)
-4-:	84	if (reg2hw.masked_out_lower.data.qe)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T24,T25,T26
0	1	-	-	Covered	T25,T26,T1
0	0	1	-	Covered	T25,T26,T1
0	0	0	1	Covered	T25,T26,T1
0	0	0	0	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	99	if ((!rst_ni))
-2-:	101	if (reg2hw.direct_oe.qe)
-3-:	103	if (reg2hw.masked_oe_upper.data.qe)
-4-:	107	if (reg2hw.masked_oe_lower.data.qe)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T24,T25,T26
0	1	-	-	Covered	T24,T25,T26
0	0	1	-	Covered	T25,T26,T1
0	0	0	1	Covered	T25,T26,T1
0	0	0	0	Covered	T24,T25,T26

---

Assert Coverage for Module : gpio

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	183862744	183539245	0	0
CioGpioEnOKnown	183862744	183539245	0	0
CioGpioOKnown	183862744	183539245	0	0
FpvSecCmRegWeOnehotCheck_A	183862744	90	0	0
IntrGpioKnown	183862744	183539245	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183862744	183539245	0	0
T1	34952	34884	0	0
T11	3001	2941	0	0
T12	3284	3204	0	0
T13	3172	3104	0	0
T14	2341	2269	0	0
T15	5327	5272	0	0
T16	9699	9603	0	0
T24	4630	4559	0	0
T25	1887	1789	0	0
T26	4076	4023	0	0

CioGpioEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	183862744	183539245	0	0
T1	34952	34884	0	0
T11	3001	2941	0	0
T12	3284	3204	0	0
T13	3172	3104	0	0
T14	2341	2269	0	0
T15	5327	5272	0	0
T16	9699	9603	0	0
T24	4630	4559	0	0
T25	1887	1789	0	0
T26	4076	4023	0	0

CioGpioOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	183862744	183539245	0	0
T1	34952	34884	0	0
T11	3001	2941	0	0
T12	3284	3204	0	0
T13	3172	3104	0	0
T14	2341	2269	0	0
T15	5327	5272	0	0
T16	9699	9603	0	0
T24	4630	4559	0	0
T25	1887	1789	0	0
T26	4076	4023	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183862744	90	0	0
T3	41497	0	0	0
T34	10576	10	0	0
T35	0	30	0	0
T36	0	30	0	0
T47	0	10	0	0
T48	0	10	0	0
T49	5371	0	0	0
T50	2338	0	0	0
T51	3876	0	0	0
T52	331447	0	0	0
T53	6894	0	0	0
T54	397157	0	0	0
T55	9170	0	0	0
T56	2580	0	0	0

IntrGpioKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	183862744	183539245	0	0
T1	34952	34884	0	0
T11	3001	2941	0	0
T12	3284	3204	0	0
T13	3172	3104	0	0
T14	2341	2269	0	0
T15	5327	5272	0	0
T16	9699	9603	0	0
T24	4630	4559	0	0
T25	1887	1789	0	0
T26	4076	4023	0	0