Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	184369046	0	0	0
ctrl_en_input_filter_rd_A	184369046	109902	0	0
intr_ctrl_en_falling_rd_A	184369046	115119	0	0
intr_ctrl_en_lvlhigh_rd_A	184369046	107842	0	0
intr_ctrl_en_lvllow_rd_A	184369046	115013	0	0
intr_ctrl_en_rising_rd_A	184369046	108699	0	0
intr_enable_rd_A	184369046	109933	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	109902	0	0
T1	34952	190	0	0
T2	0	6457	0	0
T3	0	334	0	0
T4	0	386	0	0
T5	0	4786	0	0
T6	0	7	0	0
T7	0	431	0	0
T8	0	68	0	0
T9	0	25229	0	0
T10	0	1707	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	115119	0	0
T1	34952	148	0	0
T2	0	6320	0	0
T3	0	268	0	0
T4	0	370	0	0
T5	0	5036	0	0
T6	0	3	0	0
T7	0	479	0	0
T8	0	97	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0
T20	0	7	0	0
T21	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	107842	0	0
T1	34952	206	0	0
T2	0	6304	0	0
T3	0	226	0	0
T4	0	290	0	0
T5	0	4682	0	0
T7	0	379	0	0
T8	0	101	0	0
T9	0	25066	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0
T20	0	2	0	0
T22	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	115013	0	0
T1	34952	210	0	0
T2	0	6555	0	0
T3	0	316	0	0
T4	0	333	0	0
T5	0	4747	0	0
T7	0	477	0	0
T8	0	57	0	0
T9	0	28593	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0
T20	0	2	0	0
T21	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	108699	0	0
T1	34952	163	0	0
T2	0	6000	0	0
T3	0	243	0	0
T4	0	332	0	0
T5	0	4908	0	0
T6	0	2	0	0
T7	0	401	0	0
T8	0	168	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0
T21	0	1	0	0
T23	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184369046	109933	0	0
T1	34952	266	0	0
T2	0	6339	0	0
T3	0	281	0	0
T4	0	326	0	0
T5	0	4995	0	0
T7	0	488	0	0
T8	0	127	0	0
T9	0	25033	0	0
T10	0	1798	0	0
T11	3001	0	0	0
T12	3284	0	0	0
T13	3172	0	0	0
T14	2341	0	0	0
T15	5327	0	0	0
T16	9699	0	0	0
T17	6610	0	0	0
T18	4069	0	0	0
T19	70537	0	0	0
T23	0	5	0	0