Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1357334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4835078

1

T23

390

T24

180

T25

246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2762651	1			T23	110		T24	70		T25	49
values[0x0]	1710460	1			T23	159		T24	52		T25	98
values[0x1]	1719301	1			T23	173		T24	80		T25	121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1077128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5115284

1

T23

401

T24

185

T25

247

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19542	1			T23	2		T27	1		T28	1
valid_sources[0x01]	19429	1			T23	3		T24	2		T26	7
valid_sources[0x02]	22073	1			T23	3		T27	4		T28	3
valid_sources[0x03]	22004	1			T23	2		T24	1		T27	2
valid_sources[0x04]	21581	1			T23	3		T29	2		T33	26
valid_sources[0x05]	23170	1			T23	1		T28	1		T31	1
valid_sources[0x06]	19564	1			T24	2		T27	1		T29	1
valid_sources[0x07]	20350	1			T23	2		T26	3		T27	3
valid_sources[0x08]	21212	1			T24	1		T33	19		T59	1
valid_sources[0x09]	22414	1			T24	1		T33	20		T59	9
valid_sources[0x0a]	20608	1			T23	2		T28	1		T33	21
valid_sources[0x0b]	20682	1			T23	4		T28	1		T29	1
valid_sources[0x0c]	22513	1			T23	4		T27	1		T29	2
valid_sources[0x0d]	23646	1			T23	4		T28	1		T33	12
valid_sources[0x0e]	28119	1			T27	2		T29	1		T33	10
valid_sources[0x0f]	162360	1			T23	2		T24	1		T29	1
valid_sources[0x10]	20645	1			T23	4		T24	1		T28	1
valid_sources[0x11]	27863	1			T23	3		T33	9		T48	1
valid_sources[0x12]	25469	1			T23	1		T24	2		T27	2
valid_sources[0x13]	20642	1			T27	3		T33	22		T48	1
valid_sources[0x14]	20003	1			T23	1		T26	8		T27	2
valid_sources[0x15]	23827	1			T23	3		T24	1		T27	4
valid_sources[0x16]	23378	1			T23	1		T33	16		T59	3
valid_sources[0x17]	20707	1			T23	1		T28	1		T33	8
valid_sources[0x18]	22071	1			T23	3		T24	1		T27	1
valid_sources[0x19]	79900	1			T23	2		T27	1		T33	36
valid_sources[0x1a]	19648	1			T23	2		T24	1		T28	1
valid_sources[0x1b]	22669	1			T23	2		T24	1		T33	32
valid_sources[0x1c]	21440	1			T23	4		T24	1		T27	2
valid_sources[0x1d]	24142	1			T23	2		T27	1		T28	2
valid_sources[0x1e]	20066	1			T24	2		T27	1		T28	1
valid_sources[0x1f]	23575	1			T23	1		T28	1		T33	12
valid_sources[0x20]	20361	1			T24	1		T28	2		T33	38
valid_sources[0x21]	23468	1			T23	1		T24	1		T33	26
valid_sources[0x22]	20091	1			T23	1		T28	1		T33	17
valid_sources[0x23]	18981	1			T23	5		T24	2		T27	1
valid_sources[0x24]	21437	1			T23	2		T33	23		T48	3
valid_sources[0x25]	20536	1			T23	1		T28	1		T33	22
valid_sources[0x26]	21929	1			T23	1		T29	1		T33	23
valid_sources[0x27]	20938	1			T23	1		T25	5		T27	1
valid_sources[0x28]	31234	1			T23	1		T26	3		T29	1
valid_sources[0x29]	24150	1			T23	2		T27	4		T28	1
valid_sources[0x2a]	23909	1			T23	2		T25	35		T26	1
valid_sources[0x2b]	20542	1			T23	1		T33	37		T60	1
valid_sources[0x2c]	20851	1			T23	3		T24	1		T28	1
valid_sources[0x2d]	19845	1			T23	1		T27	4		T28	1
valid_sources[0x2e]	20004	1			T23	2		T24	1		T28	1
valid_sources[0x2f]	21301	1			T23	3		T27	1		T28	1
valid_sources[0x30]	18960	1			T23	3		T29	1		T33	9
valid_sources[0x31]	20239	1			T23	2		T26	4		T29	3
valid_sources[0x32]	20712	1			T23	1		T29	2		T33	23
valid_sources[0x33]	24524	1			T23	1		T24	1		T28	4
valid_sources[0x34]	20602	1			T24	1		T29	2		T31	1
valid_sources[0x35]	20100	1			T23	2		T24	1		T27	2
valid_sources[0x36]	18629	1			T27	1		T33	17		T35	9
valid_sources[0x37]	20340	1			T23	2		T29	1		T33	8
valid_sources[0x38]	19382	1			T23	1		T24	1		T26	8
valid_sources[0x39]	20646	1			T24	1		T28	2		T29	1
valid_sources[0x3a]	21926	1			T23	2		T24	1		T27	1
valid_sources[0x3b]	22458	1			T23	1		T25	25		T28	1
valid_sources[0x3c]	19714	1			T24	1		T25	13		T33	28
valid_sources[0x3d]	20644	1			T23	1		T33	15		T60	5
valid_sources[0x3e]	21627	1			T23	2		T24	2		T27	3
valid_sources[0x3f]	24752	1			T28	2		T33	35		T59	6
valid_sources[0x40]	26308	1			T23	5		T24	2		T26	1
valid_sources[0x41]	20553	1			T24	1		T28	2		T33	11
valid_sources[0x42]	20183	1			T23	2		T33	17		T35	30
valid_sources[0x43]	24201	1			T23	3		T28	2		T33	16
valid_sources[0x44]	20474	1			T24	3		T29	1		T33	11
valid_sources[0x45]	21474	1			T23	2		T24	3		T26	6
valid_sources[0x46]	56676	1			T23	6		T33	27		T59	6
valid_sources[0x47]	20534	1			T23	2		T25	17		T29	2
valid_sources[0x48]	19752	1			T23	3		T24	2		T28	1
valid_sources[0x49]	19657	1			T23	2		T24	1		T26	7
valid_sources[0x4a]	49825	1			T23	6		T24	1		T26	12
valid_sources[0x4b]	22463	1			T23	1		T24	3		T27	3
valid_sources[0x4c]	20634	1			T23	1		T24	1		T27	1
valid_sources[0x4d]	21401	1			T24	1		T27	2		T33	5
valid_sources[0x4e]	21484	1			T23	1		T24	2		T27	1
valid_sources[0x4f]	21276	1			T24	2		T27	2		T33	16
valid_sources[0x50]	24109	1			T23	1		T27	2		T28	1
valid_sources[0x51]	20610	1			T26	2		T28	4		T33	4
valid_sources[0x52]	22069	1			T23	1		T29	1		T33	7
valid_sources[0x53]	19964	1			T24	2		T25	10		T33	23
valid_sources[0x54]	20672	1			T26	6		T33	32		T60	2
valid_sources[0x55]	23379	1			T23	3		T29	1		T33	18
valid_sources[0x56]	23865	1			T23	2		T24	1		T29	1
valid_sources[0x57]	24169	1			T27	2		T28	3		T33	10
valid_sources[0x58]	20175	1			T23	2		T24	2		T28	3
valid_sources[0x59]	20309	1			T23	4		T27	1		T28	2
valid_sources[0x5a]	22063	1			T23	1		T33	23		T48	1
valid_sources[0x5b]	25324	1			T23	1		T24	1		T27	1
valid_sources[0x5c]	20668	1			T26	1		T27	1		T28	1
valid_sources[0x5d]	25004	1			T23	1		T27	1		T28	3
valid_sources[0x5e]	22450	1			T23	1		T33	25		T60	1
valid_sources[0x5f]	19199	1			T23	1		T26	10		T27	3
valid_sources[0x60]	20701	1			T23	1		T24	1		T33	25
valid_sources[0x61]	21670	1			T23	5		T27	5		T29	1
valid_sources[0x62]	20962	1			T23	4		T24	2		T29	2
valid_sources[0x63]	26283	1			T23	2		T24	2		T27	1
valid_sources[0x64]	24463	1			T23	4		T24	3		T32	1
valid_sources[0x65]	22204	1			T23	3		T24	1		T29	2
valid_sources[0x66]	21315	1			T23	1		T24	1		T27	2
valid_sources[0x67]	24124	1			T23	2		T24	1		T28	3
valid_sources[0x68]	23601	1			T23	2		T28	1		T29	1
valid_sources[0x69]	19952	1			T26	5		T31	1		T33	7
valid_sources[0x6a]	21401	1			T23	1		T26	1		T27	1
valid_sources[0x6b]	20768	1			T24	1		T33	21		T59	1
valid_sources[0x6c]	23333	1			T23	2		T24	2		T28	1
valid_sources[0x6d]	25493	1			T23	1		T24	1		T27	1
valid_sources[0x6e]	22287	1			T23	3		T24	3		T26	6
valid_sources[0x6f]	21045	1			T23	4		T28	2		T29	6
valid_sources[0x70]	20050	1			T23	2		T28	1		T29	3
valid_sources[0x71]	25610	1			T27	1		T29	1		T33	27
valid_sources[0x72]	21662	1			T23	1		T27	1		T28	1
valid_sources[0x73]	20248	1			T23	2		T33	21		T59	4
valid_sources[0x74]	20094	1			T23	5		T24	1		T28	2
valid_sources[0x75]	21287	1			T23	2		T24	2		T29	1
valid_sources[0x76]	21702	1			T27	3		T28	1		T33	11
valid_sources[0x77]	19525	1			T23	4		T24	1		T33	28
valid_sources[0x78]	20992	1			T29	1		T33	24		T59	6
valid_sources[0x79]	31105	1			T23	1		T24	1		T29	1
valid_sources[0x7a]	21041	1			T23	1		T24	1		T26	8
valid_sources[0x7b]	20516	1			T24	3		T27	2		T28	1
valid_sources[0x7c]	20253	1			T23	4		T24	1		T26	12
valid_sources[0x7d]	24806	1			T23	2		T24	2		T26	5
valid_sources[0x7e]	19683	1			T23	1		T25	9		T27	1
valid_sources[0x7f]	26164	1			T23	3		T27	1		T28	1
valid_sources[0x80]	19239	1			T23	4		T24	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1422426

1

T23

58

T24

48

T25

27

values[0x0]

all_enables

biggest_size

1708610

1

T23

159

T24

52

T25

98

values[0x1]

all_enables

biggest_size

1704042

1

T23

173

T24

80

T25

121