Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	49494228	0	0	0
ctrl_en_input_filter_rd_A	49494228	53613	0	0
intr_ctrl_en_falling_rd_A	49494228	52971	0	0
intr_ctrl_en_lvlhigh_rd_A	49494228	53027	0	0
intr_ctrl_en_lvllow_rd_A	49494228	53513	0	0
intr_ctrl_en_rising_rd_A	49494228	53551	0	0
intr_enable_rd_A	49494228	53916	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	53613	0	0
T1	41688	209	0	0
T2	0	322	0	0
T3	0	1	0	0
T4	0	220	0	0
T5	0	539	0	0
T6	0	1380	0	0
T7	0	6	0	0
T8	0	3448	0	0
T9	0	712	0	0
T10	0	93	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	52971	0	0
T1	41688	187	0	0
T2	0	328	0	0
T4	0	275	0	0
T5	0	416	0	0
T6	0	1318	0	0
T8	0	3517	0	0
T9	0	579	0	0
T10	0	106	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0
T20	0	1628	0	0
T21	0	2297	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	53027	0	0
T1	41688	139	0	0
T2	0	257	0	0
T3	0	1	0	0
T4	0	205	0	0
T5	0	551	0	0
T6	0	1267	0	0
T8	0	3320	0	0
T9	0	785	0	0
T10	0	158	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0
T22	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	53513	0	0
T1	41688	150	0	0
T2	0	250	0	0
T4	0	333	0	0
T5	0	436	0	0
T6	0	1332	0	0
T8	0	3731	0	0
T9	0	669	0	0
T10	0	119	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0
T20	0	1632	0	0
T21	0	2181	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	53551	0	0
T1	41688	254	0	0
T2	0	379	0	0
T4	0	276	0	0
T5	0	400	0	0
T6	0	1374	0	0
T7	0	2	0	0
T8	0	3283	0	0
T9	0	758	0	0
T10	0	123	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0
T20	0	1461	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49494228	53916	0	0
T1	41688	215	0	0
T2	0	300	0	0
T4	0	201	0	0
T5	0	493	0	0
T6	0	1396	0	0
T7	0	7	0	0
T8	0	3404	0	0
T9	0	703	0	0
T10	0	144	0	0
T11	8742	0	0	0
T12	1298	0	0	0
T13	2460	0	0	0
T14	8391	0	0	0
T15	3359	0	0	0
T16	2281	0	0	0
T17	2078	0	0	0
T18	2170	0	0	0
T19	5642	0	0	0
T20	0	1572	0	0