Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1307954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4559045

1

T33

445

T34

292

T35

425

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2650299	1			T33	137		T34	145		T35	96
values[0x0]	1601949	1			T33	179		T34	118		T35	188
values[0x1]	1614751	1			T33	187		T34	102		T35	186

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1039954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4827045

1

T33

456

T34

307

T35

431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22773	1			T34	1		T35	1		T23	3
valid_sources[0x01]	18978	1			T34	1		T35	1		T38	2
valid_sources[0x02]	19687	1			T33	1		T35	2		T37	1
valid_sources[0x03]	21877	1			T34	1		T35	2		T37	2
valid_sources[0x04]	21582	1			T33	2		T34	2		T35	3
valid_sources[0x05]	18958	1			T33	2		T35	8		T37	1
valid_sources[0x06]	21403	1			T34	1		T35	4		T37	2
valid_sources[0x07]	23712	1			T35	6		T23	5		T26	2
valid_sources[0x08]	21452	1			T34	1		T35	1		T37	1
valid_sources[0x09]	23779	1			T33	7		T34	1		T35	1
valid_sources[0x0a]	18661	1			T33	2		T34	2		T35	1
valid_sources[0x0b]	21428	1			T33	6		T34	3		T35	2
valid_sources[0x0c]	19365	1			T34	1		T35	1		T38	1
valid_sources[0x0d]	19967	1			T34	1		T35	1		T37	2
valid_sources[0x0e]	20579	1			T33	12		T34	2		T35	3
valid_sources[0x0f]	19870	1			T34	4		T35	3		T37	1
valid_sources[0x10]	20409	1			T34	4		T35	1		T37	3
valid_sources[0x11]	21293	1			T33	2		T34	5		T37	3
valid_sources[0x12]	23579	1			T33	6		T34	2		T35	3
valid_sources[0x13]	18856	1			T34	1		T35	4		T38	1
valid_sources[0x14]	19326	1			T33	10		T35	3		T38	2
valid_sources[0x15]	20300	1			T33	1		T34	3		T35	3
valid_sources[0x16]	20450	1			T33	2		T34	1		T35	5
valid_sources[0x17]	25267	1			T34	1		T35	1		T37	1
valid_sources[0x18]	23604	1			T35	4		T20	1		T26	2
valid_sources[0x19]	20033	1			T33	7		T34	2		T37	1
valid_sources[0x1a]	18944	1			T33	5		T34	1		T35	2
valid_sources[0x1b]	20049	1			T35	1		T38	3		T21	13
valid_sources[0x1c]	22740	1			T34	3		T35	3		T37	1
valid_sources[0x1d]	113616	1			T33	1		T34	2		T35	1
valid_sources[0x1e]	22513	1			T34	3		T35	2		T38	1
valid_sources[0x1f]	21077	1			T33	1		T34	1		T35	6
valid_sources[0x20]	20365	1			T34	1		T35	2		T37	1
valid_sources[0x21]	20270	1			T33	2		T34	2		T35	2
valid_sources[0x22]	18073	1			T34	4		T35	2		T38	2
valid_sources[0x23]	23541	1			T34	2		T35	4		T37	2
valid_sources[0x24]	23353	1			T33	2		T34	3		T35	2
valid_sources[0x25]	19961	1			T33	6		T34	2		T35	4
valid_sources[0x26]	20132	1			T35	4		T38	1		T23	11
valid_sources[0x27]	19416	1			T35	2		T38	2		T21	72
valid_sources[0x28]	20180	1			T34	1		T35	1		T38	2
valid_sources[0x29]	45245	1			T34	2		T35	1		T20	1
valid_sources[0x2a]	20706	1			T34	1		T35	1		T37	3
valid_sources[0x2b]	25086	1			T33	7		T34	1		T35	2
valid_sources[0x2c]	20053	1			T37	3		T38	3		T23	1
valid_sources[0x2d]	25344	1			T35	3		T37	1		T38	5
valid_sources[0x2e]	22531	1			T37	1		T38	1		T21	11
valid_sources[0x2f]	18898	1			T34	3		T35	1		T37	1
valid_sources[0x30]	24660	1			T33	4		T34	3		T37	1
valid_sources[0x31]	19512	1			T33	1		T38	3		T21	3
valid_sources[0x32]	19733	1			T35	1		T37	1		T38	4
valid_sources[0x33]	19305	1			T33	1		T35	1		T37	1
valid_sources[0x34]	22757	1			T34	2		T37	2		T38	1
valid_sources[0x35]	20014	1			T34	2		T35	2		T38	1
valid_sources[0x36]	19762	1			T34	1		T35	2		T37	2
valid_sources[0x37]	19063	1			T35	3		T37	1		T38	1
valid_sources[0x38]	19376	1			T34	2		T35	3		T37	3
valid_sources[0x39]	19446	1			T33	1		T34	1		T38	1
valid_sources[0x3a]	23287	1			T34	7		T35	1		T37	2
valid_sources[0x3b]	23083	1			T37	2		T23	7		T26	1
valid_sources[0x3c]	20014	1			T35	2		T37	1		T38	2
valid_sources[0x3d]	22892	1			T33	2		T37	2		T38	2
valid_sources[0x3e]	21674	1			T34	1		T35	1		T38	3
valid_sources[0x3f]	19086	1			T34	5		T35	5		T37	2
valid_sources[0x40]	20817	1			T33	2		T34	2		T37	4
valid_sources[0x41]	18860	1			T33	6		T35	1		T37	2
valid_sources[0x42]	25977	1			T34	1		T35	1		T37	1
valid_sources[0x43]	20945	1			T33	17		T34	1		T35	1
valid_sources[0x44]	20753	1			T33	7		T34	1		T35	1
valid_sources[0x45]	22162	1			T34	3		T35	2		T38	3
valid_sources[0x46]	21849	1			T34	2		T35	3		T38	1
valid_sources[0x47]	19308	1			T33	7		T34	3		T37	1
valid_sources[0x48]	21660	1			T35	9		T37	1		T38	2
valid_sources[0x49]	21041	1			T37	2		T38	1		T23	7
valid_sources[0x4a]	21998	1			T35	1		T37	2		T38	1
valid_sources[0x4b]	18618	1			T35	2		T23	14		T28	3
valid_sources[0x4c]	21446	1			T35	4		T38	1		T20	4
valid_sources[0x4d]	19808	1			T34	1		T35	2		T37	1
valid_sources[0x4e]	19124	1			T34	7		T23	8		T26	1
valid_sources[0x4f]	19987	1			T34	2		T35	1		T37	2
valid_sources[0x50]	21946	1			T33	1		T37	1		T23	5
valid_sources[0x51]	19598	1			T33	6		T35	2		T37	2
valid_sources[0x52]	19218	1			T34	3		T35	6		T38	1
valid_sources[0x53]	18873	1			T34	2		T35	1		T37	3
valid_sources[0x54]	19954	1			T37	2		T38	2		T23	11
valid_sources[0x55]	21711	1			T34	2		T35	5		T37	3
valid_sources[0x56]	19686	1			T34	1		T38	1		T23	9
valid_sources[0x57]	18595	1			T37	1		T38	2		T23	2
valid_sources[0x58]	20703	1			T35	4		T38	1		T23	9
valid_sources[0x59]	20036	1			T34	1		T38	4		T20	4
valid_sources[0x5a]	21791	1			T35	4		T23	3		T27	3
valid_sources[0x5b]	19954	1			T33	1		T34	3		T35	4
valid_sources[0x5c]	18777	1			T33	1		T35	1		T37	2
valid_sources[0x5d]	19995	1			T33	2		T34	1		T35	2
valid_sources[0x5e]	21359	1			T34	1		T35	1		T23	10
valid_sources[0x5f]	25397	1			T34	6		T35	3		T37	2
valid_sources[0x60]	27970	1			T23	4		T26	2		T27	4
valid_sources[0x61]	18412	1			T38	3		T23	7		T26	1
valid_sources[0x62]	19590	1			T33	1		T37	4		T38	1
valid_sources[0x63]	19528	1			T37	2		T23	10		T26	1
valid_sources[0x64]	21260	1			T38	3		T23	13		T26	1
valid_sources[0x65]	19150	1			T33	32		T34	1		T38	2
valid_sources[0x66]	26478	1			T33	8		T35	2		T37	1
valid_sources[0x67]	20962	1			T34	1		T35	2		T38	4
valid_sources[0x68]	19692	1			T34	1		T35	4		T37	2
valid_sources[0x69]	19823	1			T35	2		T37	1		T38	1
valid_sources[0x6a]	21115	1			T34	1		T35	2		T37	1
valid_sources[0x6b]	19325	1			T35	1		T37	1		T38	2
valid_sources[0x6c]	21278	1			T33	10		T34	3		T23	14
valid_sources[0x6d]	23157	1			T33	4		T35	1		T37	1
valid_sources[0x6e]	22803	1			T33	2		T35	2		T21	9
valid_sources[0x6f]	19655	1			T34	1		T37	2		T23	1
valid_sources[0x70]	18283	1			T34	1		T35	1		T20	1
valid_sources[0x71]	20216	1			T34	2		T35	4		T37	1
valid_sources[0x72]	21127	1			T34	3		T35	5		T37	1
valid_sources[0x73]	21130	1			T33	11		T34	2		T35	2
valid_sources[0x74]	22216	1			T33	11		T34	1		T35	2
valid_sources[0x75]	25816	1			T37	1		T38	1		T23	1
valid_sources[0x76]	23954	1			T33	7		T35	2		T37	1
valid_sources[0x77]	19983	1			T35	2		T20	1		T21	4
valid_sources[0x78]	19052	1			T33	5		T34	1		T38	1
valid_sources[0x79]	21416	1			T34	1		T37	2		T38	4
valid_sources[0x7a]	21779	1			T35	1		T37	3		T38	1
valid_sources[0x7b]	24799	1			T33	6		T34	3		T35	1
valid_sources[0x7c]	18836	1			T37	1		T38	2		T23	5
valid_sources[0x7d]	22655	1			T33	6		T34	2		T35	4
valid_sources[0x7e]	19459	1			T33	2		T34	2		T35	2
valid_sources[0x7f]	19266	1			T34	2		T35	1		T38	1
valid_sources[0x80]	19759	1			T33	3		T35	6		T38	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1356348

1

T33

79

T34

72

T35

51

values[0x0]

all_enables

biggest_size

1600391

1

T33

179

T34

118

T35

188

values[0x1]

all_enables

biggest_size

1602306

1

T33

187

T34

102

T35

186