Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	50174481	0	0	0
ctrl_en_input_filter_rd_A	50174481	87607	0	0
intr_ctrl_en_falling_rd_A	50174481	86727	0	0
intr_ctrl_en_lvlhigh_rd_A	50174481	88868	0	0
intr_ctrl_en_lvllow_rd_A	50174481	87490	0	0
intr_ctrl_en_rising_rd_A	50174481	87427	0	0
intr_enable_rd_A	50174481	88211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	87607	0	0
T1	25859	174	0	0
T2	0	269	0	0
T3	0	174	0	0
T4	0	46	0	0
T5	0	324	0	0
T6	0	47	0	0
T7	0	3	0	0
T8	0	2956	0	0
T9	0	2705	0	0
T10	0	3278	0	0
T11	1187	0	0	0
T12	2124	0	0	0
T13	4340	0	0	0
T14	3698	0	0	0
T15	6044	0	0	0
T16	6146	0	0	0
T17	8808	0	0	0
T18	763	0	0	0
T19	1213	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	86727	0	0
T1	0	194	0	0
T2	0	246	0	0
T3	0	227	0	0
T4	0	32	0	0
T5	0	284	0	0
T6	0	103	0	0
T8	0	2676	0	0
T9	0	3034	0	0
T10	0	3148	0	0
T20	5570	14	0	0
T21	7267	0	0	0
T22	18000	0	0	0
T23	8000	0	0	0
T24	1449	0	0	0
T25	2922	0	0	0
T26	5115	0	0	0
T27	3204	0	0	0
T28	2163	0	0	0
T29	5042	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	88868	0	0
T1	0	186	0	0
T2	0	301	0	0
T3	0	97	0	0
T4	0	47	0	0
T5	0	348	0	0
T6	0	55	0	0
T7	0	3	0	0
T8	0	3098	0	0
T20	5570	5	0	0
T21	7267	0	0	0
T22	18000	0	0	0
T23	8000	0	0	0
T24	1449	0	0	0
T25	2922	0	0	0
T26	5115	0	0	0
T27	3204	0	0	0
T28	2163	0	0	0
T29	5042	0	0	0
T30	0	5	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	87490	0	0
T1	25859	139	0	0
T2	0	280	0	0
T3	0	204	0	0
T4	0	60	0	0
T5	0	255	0	0
T6	0	39	0	0
T8	0	3051	0	0
T9	0	2858	0	0
T10	0	3391	0	0
T11	1187	0	0	0
T12	2124	0	0	0
T13	4340	0	0	0
T14	3698	0	0	0
T15	6044	0	0	0
T16	6146	0	0	0
T17	8808	0	0	0
T18	763	0	0	0
T19	1213	0	0	0
T31	0	251	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	87427	0	0
T1	25859	233	0	0
T2	0	221	0	0
T3	0	187	0	0
T4	0	59	0	0
T5	0	329	0	0
T6	0	94	0	0
T7	0	3	0	0
T8	0	2768	0	0
T9	0	2935	0	0
T11	1187	0	0	0
T12	2124	0	0	0
T13	4340	0	0	0
T14	3698	0	0	0
T15	6044	0	0	0
T16	6146	0	0	0
T17	8808	0	0	0
T18	763	0	0	0
T19	1213	0	0	0
T32	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50174481	88211	0	0
T1	25859	204	0	0
T2	0	219	0	0
T3	0	150	0	0
T4	0	50	0	0
T5	0	284	0	0
T6	0	61	0	0
T7	0	11	0	0
T8	0	2866	0	0
T9	0	2828	0	0
T10	0	3301	0	0
T11	1187	0	0	0
T12	2124	0	0	0
T13	4340	0	0	0
T14	3698	0	0	0
T15	6044	0	0	0
T16	6146	0	0	0
T17	8808	0	0	0
T18	763	0	0	0
T19	1213	0	0	0