Unified Coverage Report :: Module

Module : gpio

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00		100.00	100.00

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	99.04	99.24	100.00		99.80	99.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_filter[0].u_filter	100.00	100.00	100.00			100.00
gen_filter[10].u_filter	100.00	100.00	100.00			100.00
gen_filter[11].u_filter	100.00	100.00	100.00			100.00
gen_filter[12].u_filter	100.00	100.00	100.00			100.00
gen_filter[13].u_filter	100.00	100.00	100.00			100.00
gen_filter[14].u_filter	100.00	100.00	100.00			100.00
gen_filter[15].u_filter	100.00	100.00	100.00			100.00
gen_filter[16].u_filter	100.00	100.00	100.00			100.00
gen_filter[17].u_filter	100.00	100.00	100.00			100.00
gen_filter[18].u_filter	100.00	100.00	100.00			100.00
gen_filter[19].u_filter	100.00	100.00	100.00			100.00
gen_filter[1].u_filter	100.00	100.00	100.00			100.00
gen_filter[20].u_filter	100.00	100.00	100.00			100.00
gen_filter[21].u_filter	100.00	100.00	100.00			100.00
gen_filter[22].u_filter	100.00	100.00	100.00			100.00
gen_filter[23].u_filter	100.00	100.00	100.00			100.00
gen_filter[24].u_filter	100.00	100.00	100.00			100.00
gen_filter[25].u_filter	100.00	100.00	100.00			100.00
gen_filter[26].u_filter	100.00	100.00	100.00			100.00
gen_filter[27].u_filter	100.00	100.00	100.00			100.00
gen_filter[28].u_filter	100.00	100.00	100.00			100.00
gen_filter[29].u_filter	100.00	100.00	100.00			100.00
gen_filter[2].u_filter	100.00	100.00	100.00			100.00
gen_filter[30].u_filter	100.00	100.00	100.00			100.00
gen_filter[31].u_filter	100.00	100.00	100.00			100.00
gen_filter[3].u_filter	100.00	100.00	100.00			100.00
gen_filter[4].u_filter	100.00	100.00	100.00			100.00
gen_filter[5].u_filter	100.00	100.00	100.00			100.00
gen_filter[6].u_filter	100.00	100.00	100.00			100.00
gen_filter[7].u_filter	100.00	100.00	100.00			100.00
gen_filter[8].u_filter	100.00	100.00	100.00			100.00
gen_filter[9].u_filter	100.00	100.00	100.00			100.00
gpio_csr_assert	85.71						85.71
intr_hw	100.00	100.00				100.00	100.00
tlul_assert_device	100.00						100.00
u_reg	99.03	97.69	98.53	100.00		98.95	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : gpio

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	8	8	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	99	8	8	100.00
ALWAYS	116	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	149	1	1	100.00



62                        assign hw2reg.data_in.de = 1'b1;
63         1/1            assign hw2reg.data_in.d  = data_in_d;
           Tests:       T25 T26 T27 
64                      
65                        // GPIO_OUT
66         1/1            assign cio_gpio_o                     = cio_gpio_q;
           Tests:       T25 T26 T27 
67         1/1            assign cio_gpio_en_o                  = cio_gpio_en_q;
           Tests:       T25 T26 T27 
68                      
69         1/1            assign hw2reg.direct_out.d            = cio_gpio_q;
           Tests:       T25 T26 T27 
70         1/1            assign hw2reg.masked_out_upper.data.d = cio_gpio_q[31:16];
           Tests:       T25 T26 T27 
71                        assign hw2reg.masked_out_upper.mask.d = 16'h 0;
72         1/1            assign hw2reg.masked_out_lower.data.d = cio_gpio_q[15:0];
           Tests:       T25 T26 T27 
73                        assign hw2reg.masked_out_lower.mask.d = 16'h 0;
74                      
75                        always_ff @(posedge clk_i or negedge rst_ni) begin
76         1/1              if (!rst_ni) begin
           Tests:       T25 T26 T27 
77         1/1                cio_gpio_q  <= '0;
           Tests:       T25 T26 T27 
78         1/1              end else if (reg2hw.direct_out.qe) begin
           Tests:       T25 T26 T27 
79         1/1                cio_gpio_q <= reg2hw.direct_out.q;
           Tests:       T25 T26 T27 
80         1/1              end else if (reg2hw.masked_out_upper.data.qe) begin
           Tests:       T25 T26 T27 
81         1/1                cio_gpio_q[31:16] <=
           Tests:       T25 T26 T27 
82                              ( reg2hw.masked_out_upper.mask.q & reg2hw.masked_out_upper.data.q) |
83                              (~reg2hw.masked_out_upper.mask.q & cio_gpio_q[31:16]);
84         1/1              end else if (reg2hw.masked_out_lower.data.qe) begin
           Tests:       T25 T26 T27 
85         1/1                cio_gpio_q[15:0] <=
           Tests:       T25 T26 T27 
86                              ( reg2hw.masked_out_lower.mask.q & reg2hw.masked_out_lower.data.q) |
87                              (~reg2hw.masked_out_lower.mask.q & cio_gpio_q[15:0]);
88                          end
                        MISSING_ELSE
89                        end
90                      
91                        // GPIO OE
92         1/1            assign hw2reg.direct_oe.d = cio_gpio_en_q;
           Tests:       T25 T26 T27 
93         1/1            assign hw2reg.masked_oe_upper.data.d = cio_gpio_en_q[31:16];
           Tests:       T25 T26 T27 
94                        assign hw2reg.masked_oe_upper.mask.d = 16'h 0;
95         1/1            assign hw2reg.masked_oe_lower.data.d = cio_gpio_en_q[15:0];
           Tests:       T25 T26 T27 
96                        assign hw2reg.masked_oe_lower.mask.d = 16'h 0;
97                      
98                        always_ff @(posedge clk_i or negedge rst_ni) begin
99         1/1              if (!rst_ni) begin
           Tests:       T25 T26 T27 
100        1/1                cio_gpio_en_q  <= '0;
           Tests:       T25 T26 T27 
101        1/1              end else if (reg2hw.direct_oe.qe) begin
           Tests:       T25 T26 T27 
102        1/1                cio_gpio_en_q <= reg2hw.direct_oe.q;
           Tests:       T25 T26 T27 
103        1/1              end else if (reg2hw.masked_oe_upper.data.qe) begin
           Tests:       T25 T26 T27 
104        1/1                cio_gpio_en_q[31:16] <=
           Tests:       T25 T26 T27 
105                             ( reg2hw.masked_oe_upper.mask.q & reg2hw.masked_oe_upper.data.q) |
106                             (~reg2hw.masked_oe_upper.mask.q & cio_gpio_en_q[31:16]);
107        1/1              end else if (reg2hw.masked_oe_lower.data.qe) begin
           Tests:       T25 T26 T27 
108        1/1                cio_gpio_en_q[15:0] <=
           Tests:       T25 T26 T27 
109                             ( reg2hw.masked_oe_lower.mask.q & reg2hw.masked_oe_lower.data.q) |
110                             (~reg2hw.masked_oe_lower.mask.q & cio_gpio_en_q[15:0]);
111                         end
                        MISSING_ELSE
112                       end
113                     
114                       logic [31:0] data_in_q;
115                       always_ff @(posedge clk_i) begin
116        1/1              data_in_q <= data_in_d;
           Tests:       T25 T26 T27 
117                       end
118                     
119                       logic [31:0] event_intr_rise, event_intr_fall, event_intr_actlow, event_intr_acthigh;
120                       logic [31:0] event_intr_combined;
121                     
122                       // instantiate interrupt hardware primitive
123                       prim_intr_hw #(.Width(32)) intr_hw (
124                         .clk_i,
125                         .rst_ni,
126                         .event_intr_i           (event_intr_combined),
127                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
128                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.q),
129                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.qe),
130                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.q),
131                         .hw2reg_intr_state_de_o (hw2reg.intr_state.de),
132                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.d),
133                         .intr_o                 (intr_gpio_o)
134                       );
135                     
136                       // detect four possible individual interrupts
137        1/1            assign event_intr_rise    = (~data_in_q &  data_in_d) & reg2hw.intr_ctrl_en_rising.q;
           Tests:       T25 T26 T27 
138        1/1            assign event_intr_fall    = ( data_in_q & ~data_in_d) & reg2hw.intr_ctrl_en_falling.q;
           Tests:       T25 T26 T27 
139        1/1            assign event_intr_acthigh =                data_in_d  & reg2hw.intr_ctrl_en_lvlhigh.q;
           Tests:       T25 T26 T27 
140        1/1            assign event_intr_actlow  =               ~data_in_d  & reg2hw.intr_ctrl_en_lvllow.q;
           Tests:       T25 T26 T27 
141                     
142        1/1            assign event_intr_combined = event_intr_rise   |
           Tests:       T25 T26 T27 
143                                                    event_intr_fall   |
144                                                    event_intr_actlow |
145                                                    event_intr_acthigh;
146                     
147                       // Alerts
148                       logic [NumAlerts-1:0] alert_test, alerts;
149        1/1            assign alert_test = {
           Tests:       T25 T26 T27

Cond Coverage for Module : gpio

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       149
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T25,T26,T27
1	1	Covered	T47,T48,T49

Toggle Coverage for Module : gpio

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	588	588	100.00
Total Bits 0->1	294	294	100.00
Total Bits 1->0	294	294	100.00


Ports	30	30	100.00
Port Bits	588	588	100.00
Port Bits 0->1	294	294	100.00
Port Bits 1->0	294	294	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
rst_ni	Yes	Yes	T28,T34,T44	Yes	T25,T26,T27	INPUT
tl_i.d_ready	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T25,T33,T42	Yes	T25,T33,T42	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_address[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_source[7:0]	Yes	Yes	T25,T28,T29	Yes	T25,T28,T29	INPUT
tl_i.a_size[1:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_i.a_valid	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
tl_o.a_ready	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T25,T26,*T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T25,T26,*T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_gpio_o[31:0]	Yes	Yes	T28,T29,T32	Yes	T28,T29,T32	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T47,T44,T48	Yes	T47,T44,T48	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T47,T44,T48	Yes	T47,T44,T48	OUTPUT
cio_gpio_i[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
cio_gpio_o[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
cio_gpio_en_o[31:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : gpio

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	76	5	5	100.00
IF	99	5	5	100.00



76             if (!rst_ni) begin
               -1-  
77               cio_gpio_q  <= '0;
                 ==>
78             end else if (reg2hw.direct_out.qe) begin
                        -2-  
79               cio_gpio_q <= reg2hw.direct_out.q;
                 ==>
80             end else if (reg2hw.masked_out_upper.data.qe) begin
                        -3-  
81               cio_gpio_q[31:16] <=
                 ==>
82                 ( reg2hw.masked_out_upper.mask.q & reg2hw.masked_out_upper.data.q) |
83                 (~reg2hw.masked_out_upper.mask.q & cio_gpio_q[31:16]);
84             end else if (reg2hw.masked_out_lower.data.qe) begin
                        -4-  
85               cio_gpio_q[15:0] <=
                 ==>
86                 ( reg2hw.masked_out_lower.mask.q & reg2hw.masked_out_lower.data.q) |
87                 (~reg2hw.masked_out_lower.mask.q & cio_gpio_q[15:0]);
88             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T25,T26,T27
0	1	-	-	Covered	T25,T26,T27
0	0	1	-	Covered	T25,T26,T27
0	0	0	1	Covered	T25,T26,T27
0	0	0	0	Covered	T25,T26,T27



99             if (!rst_ni) begin
               -1-  
100              cio_gpio_en_q  <= '0;
                 ==>
101            end else if (reg2hw.direct_oe.qe) begin
                        -2-  
102              cio_gpio_en_q <= reg2hw.direct_oe.q;
                 ==>
103            end else if (reg2hw.masked_oe_upper.data.qe) begin
                        -3-  
104              cio_gpio_en_q[31:16] <=
                 ==>
105                ( reg2hw.masked_oe_upper.mask.q & reg2hw.masked_oe_upper.data.q) |
106                (~reg2hw.masked_oe_upper.mask.q & cio_gpio_en_q[31:16]);
107            end else if (reg2hw.masked_oe_lower.data.qe) begin
                        -4-  
108              cio_gpio_en_q[15:0] <=
                 ==>
109                ( reg2hw.masked_oe_lower.mask.q & reg2hw.masked_oe_lower.data.q) |
110                (~reg2hw.masked_oe_lower.mask.q & cio_gpio_en_q[15:0]);
111            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T25,T26,T27
0	1	-	-	Covered	T25,T26,T27
0	0	1	-	Covered	T25,T26,T27
0	0	0	1	Covered	T25,T26,T27
0	0	0	0	Covered	T25,T26,T27

Assert Coverage for Module : gpio

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	48793606	48455041	0	0
CioGpioEnOKnown	48793606	48455041	0	0
CioGpioOKnown	48793606	48455041	0	0
FpvSecCmRegWeOnehotCheck_A	48793606	120	0	0
IntrGpioKnown	48793606	48455041	0	0

AlertsKnown_A

Name	Attempts	Real Successes
Total	48793606	48455041
T25	3991	3891
T26	3828	3742
T27	3364	3278
T28	4205	2541
T29	3326	3227
T30	5953	5868
T31	2188	2120
T32	2366	2295
T33	5011	4934
T34	3216	2142

CioGpioEnOKnown

Name	Attempts	Real Successes
Total	48793606	48455041
T25	3991	3891
T26	3828	3742
T27	3364	3278
T28	4205	2541
T29	3326	3227
T30	5953	5868
T31	2188	2120
T32	2366	2295
T33	5011	4934
T34	3216	2142

CioGpioOKnown

Name	Attempts	Real Successes
Total	48793606	48455041
T25	3991	3891
T26	3828	3742
T27	3364	3278
T28	4205	2541
T29	3326	3227
T30	5953	5868
T31	2188	2120
T32	2366	2295
T33	5011	4934
T34	3216	2142

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes
Total	48793606	120
T35	2564	0
T42	3301	0
T44	6681	10
T45	0	20
T46	0	30
T48	1043	0
T55	5639	0
T56	0	30
T57	0	30
T58	1732	0
T59	3571	0
T60	3698	0
T61	9611	0
T62	8954	0

IntrGpioKnown

Name	Attempts	Real Successes
Total	48793606	48455041
T25	3991	3891
T26	3828	3742
T27	3364	3278
T28	4205	2541
T29	3326	3227
T30	5953	5868
T31	2188	2120
T32	2366	2295
T33	5011	4934
T34	3216	2142