Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	49332238	0	0	0
ctrl_en_input_filter_rd_A	49332238	45634	0	0
intr_ctrl_en_falling_rd_A	49332238	45933	0	0
intr_ctrl_en_lvlhigh_rd_A	49332238	45725	0	0
intr_ctrl_en_lvllow_rd_A	49332238	46510	0	0
intr_ctrl_en_rising_rd_A	49332238	45517	0	0
intr_enable_rd_A	49332238	45113	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	45634	0	0
T1	26351	184	0	0
T2	0	56	0	0
T3	0	26	0	0
T4	0	11	0	0
T5	0	381	0	0
T6	0	5	0	0
T7	0	969	0	0
T8	0	508	0	0
T9	0	311	0	0
T10	0	83	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	45933	0	0
T1	26351	212	0	0
T2	0	51	0	0
T3	0	55	0	0
T4	0	8	0	0
T5	0	322	0	0
T7	0	988	0	0
T8	0	496	0	0
T9	0	182	0	0
T10	0	81	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0
T20	0	13	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	45725	0	0
T1	26351	212	0	0
T2	0	48	0	0
T3	0	57	0	0
T5	0	229	0	0
T7	0	964	0	0
T8	0	373	0	0
T9	0	205	0	0
T10	0	112	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0
T21	0	3	0	0
T22	0	1320	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	46510	0	0
T1	26351	195	0	0
T2	0	53	0	0
T3	0	28	0	0
T5	0	299	0	0
T7	0	1072	0	0
T8	0	483	0	0
T9	0	154	0	0
T10	0	60	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0
T22	0	1327	0	0
T23	0	2746	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	45517	0	0
T1	26351	236	0	0
T2	0	29	0	0
T3	0	37	0	0
T5	0	254	0	0
T6	0	8	0	0
T7	0	984	0	0
T8	0	381	0	0
T9	0	206	0	0
T10	0	80	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0
T22	0	1435	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49332238	45113	0	0
T1	26351	263	0	0
T2	0	69	0	0
T3	0	24	0	0
T4	0	2	0	0
T5	0	310	0	0
T7	0	758	0	0
T8	0	494	0	0
T9	0	238	0	0
T11	5716	0	0	0
T12	5728	0	0	0
T13	12167	0	0	0
T14	7203	0	0	0
T15	1947	0	0	0
T16	1672	0	0	0
T17	2900	0	0	0
T18	4328	0	0	0
T19	7477	0	0	0
T20	0	2	0	0
T24	0	6	0	0