Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3427739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15216589

1

T24

7

T25

1652

T26

331

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7481624	1			T24	1		T25	2564		T26	143
values[0x0]	5486292	1			T24	5		T25	179		T26	115
values[0x1]	5676412	1			T24	11		T25	180		T26	133

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2634733	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16009595

1

T24

9

T25

1908

T26

338

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65711	1			T25	26		T12	1		T13	12
valid_sources[0x01]	67267	1			T25	16		T13	7		T14	8
valid_sources[0x02]	68780	1			T25	2		T12	1		T13	1
valid_sources[0x03]	70956	1			T25	3		T26	1		T13	18
valid_sources[0x04]	64670	1			T25	1		T26	1		T12	1
valid_sources[0x05]	64771	1			T25	7		T26	3		T12	1
valid_sources[0x06]	67428	1			T26	1		T12	1		T13	7
valid_sources[0x07]	67183	1			T25	7		T14	6		T19	3
valid_sources[0x08]	65234	1			T25	5		T26	3		T12	3
valid_sources[0x09]	64550	1			T24	1		T25	9		T12	1
valid_sources[0x0a]	63685	1			T25	4		T12	3		T15	4
valid_sources[0x0b]	67681	1			T25	42		T12	5		T13	3
valid_sources[0x0c]	71971	1			T12	2		T13	2		T14	3
valid_sources[0x0d]	76687	1			T25	11		T12	2		T13	8
valid_sources[0x0e]	65416	1			T25	12		T12	3		T13	9
valid_sources[0x0f]	66841	1			T25	18		T26	1		T12	1
valid_sources[0x10]	71337	1			T25	4		T12	2		T14	2
valid_sources[0x11]	66323	1			T25	11		T26	1		T13	1
valid_sources[0x12]	65918	1			T24	1		T25	5		T26	5
valid_sources[0x13]	63960	1			T25	17		T26	3		T12	3
valid_sources[0x14]	66732	1			T25	12		T12	3		T13	48
valid_sources[0x15]	72669	1			T25	13		T12	5		T13	10
valid_sources[0x16]	67957	1			T25	10		T13	14		T42	2
valid_sources[0x17]	66741	1			T25	26		T12	2		T13	3
valid_sources[0x18]	70077	1			T24	1		T25	18		T26	5
valid_sources[0x19]	66949	1			T25	3		T26	1		T12	1
valid_sources[0x1a]	67566	1			T12	4		T14	2		T15	3
valid_sources[0x1b]	68158	1			T12	3		T13	8		T14	4
valid_sources[0x1c]	74210	1			T12	2		T13	16		T15	3
valid_sources[0x1d]	64198	1			T25	10		T26	1		T13	1
valid_sources[0x1e]	72433	1			T25	27		T26	6		T12	4
valid_sources[0x1f]	67617	1			T24	1		T25	30		T12	3
valid_sources[0x20]	67592	1			T25	32		T26	2		T12	2
valid_sources[0x21]	67061	1			T26	4		T12	3		T13	7
valid_sources[0x22]	70068	1			T25	26		T26	3		T12	1
valid_sources[0x23]	68114	1			T25	5		T12	1		T13	12
valid_sources[0x24]	66800	1			T25	32		T12	4		T13	1
valid_sources[0x25]	64992	1			T25	7		T13	5		T14	1
valid_sources[0x26]	65080	1			T25	6		T12	2		T13	12
valid_sources[0x27]	66622	1			T25	16		T26	1		T15	2
valid_sources[0x28]	65556	1			T24	1		T25	4		T12	2
valid_sources[0x29]	66398	1			T25	6		T12	1		T13	7
valid_sources[0x2a]	64550	1			T25	16		T26	3		T12	3
valid_sources[0x2b]	64920	1			T25	1		T15	4		T19	3
valid_sources[0x2c]	69497	1			T25	11		T12	2		T13	12
valid_sources[0x2d]	67748	1			T24	1		T25	21		T26	3
valid_sources[0x2e]	72061	1			T24	1		T25	22		T12	2
valid_sources[0x2f]	174791	1			T25	5		T12	2		T13	6
valid_sources[0x30]	65877	1			T25	8		T26	1		T12	2
valid_sources[0x31]	68122	1			T25	6		T12	2		T13	3
valid_sources[0x32]	67799	1			T26	4		T12	2		T13	6
valid_sources[0x33]	72830	1			T24	1		T25	6		T12	1
valid_sources[0x34]	63473	1			T25	25		T26	2		T12	3
valid_sources[0x35]	68274	1			T25	6		T26	2		T12	7
valid_sources[0x36]	72466	1			T26	2		T13	5		T14	2
valid_sources[0x37]	65375	1			T12	4		T13	5		T14	3
valid_sources[0x38]	65927	1			T25	12		T26	2		T12	2
valid_sources[0x39]	66196	1			T25	4		T26	2		T12	1
valid_sources[0x3a]	144406	1			T26	2		T12	1		T13	2
valid_sources[0x3b]	72793	1			T25	5		T26	1		T12	6
valid_sources[0x3c]	69595	1			T25	30		T26	2		T12	5
valid_sources[0x3d]	65650	1			T25	28		T12	1		T13	10
valid_sources[0x3e]	66938	1			T25	5		T13	10		T14	1
valid_sources[0x3f]	70577	1			T26	1		T12	4		T13	4
valid_sources[0x40]	67970	1			T25	26		T12	1		T13	7
valid_sources[0x41]	135618	1			T25	7		T26	5		T12	2
valid_sources[0x42]	68487	1			T25	17		T26	6		T12	3
valid_sources[0x43]	94724	1			T25	4		T13	11		T14	2
valid_sources[0x44]	65565	1			T25	1		T12	5		T13	13
valid_sources[0x45]	67439	1			T25	32		T13	18		T15	2
valid_sources[0x46]	66734	1			T25	7		T12	4		T13	9
valid_sources[0x47]	66170	1			T25	35		T13	4		T14	1
valid_sources[0x48]	68939	1			T25	9		T26	3		T12	1
valid_sources[0x49]	101814	1			T25	2		T12	1		T13	2
valid_sources[0x4a]	69285	1			T25	14		T12	1		T13	16
valid_sources[0x4b]	76004	1			T12	4		T13	4		T15	6
valid_sources[0x4c]	68993	1			T24	1		T26	2		T13	20
valid_sources[0x4d]	70296	1			T25	1		T12	3		T13	15
valid_sources[0x4e]	71787	1			T25	10		T14	6		T15	1
valid_sources[0x4f]	70287	1			T12	3		T13	1		T14	1
valid_sources[0x50]	112620	1			T25	27		T12	1		T13	5
valid_sources[0x51]	67148	1			T25	26		T26	2		T13	10
valid_sources[0x52]	68955	1			T26	2		T12	1		T13	3
valid_sources[0x53]	66720	1			T25	1		T12	3		T19	1
valid_sources[0x54]	66700	1			T25	5		T26	3		T12	3
valid_sources[0x55]	66540	1			T25	1		T12	2		T13	1
valid_sources[0x56]	64482	1			T25	20		T26	8		T12	1
valid_sources[0x57]	67300	1			T25	6		T12	1		T13	6
valid_sources[0x58]	70385	1			T25	4		T26	5		T13	2
valid_sources[0x59]	67964	1			T25	7		T13	2		T19	6
valid_sources[0x5a]	72841	1			T25	10		T26	4		T12	2
valid_sources[0x5b]	67392	1			T25	14		T26	1		T12	2
valid_sources[0x5c]	146617	1			T25	15		T12	1		T13	3
valid_sources[0x5d]	66915	1			T25	3		T12	1		T13	15
valid_sources[0x5e]	70691	1			T25	2		T12	3		T13	3
valid_sources[0x5f]	68208	1			T25	4		T26	8		T12	2
valid_sources[0x60]	69008	1			T25	1		T26	2		T12	1
valid_sources[0x61]	67322	1			T25	27		T13	6		T27	1992
valid_sources[0x62]	67275	1			T25	17		T26	2		T12	1
valid_sources[0x63]	68046	1			T25	3		T12	5		T13	1
valid_sources[0x64]	66130	1			T25	2		T13	4		T15	1
valid_sources[0x65]	115253	1			T25	36		T12	1		T14	3
valid_sources[0x66]	68758	1			T25	36		T12	2		T14	3
valid_sources[0x67]	67177	1			T25	31		T26	1		T12	2
valid_sources[0x68]	70929	1			T25	32		T26	4		T12	2
valid_sources[0x69]	65613	1			T25	5		T19	3		T45	5
valid_sources[0x6a]	66025	1			T25	2		T12	2		T13	10
valid_sources[0x6b]	66284	1			T25	11		T26	6		T12	1
valid_sources[0x6c]	68633	1			T25	14		T12	1		T13	4
valid_sources[0x6d]	67460	1			T25	1		T12	1		T13	5
valid_sources[0x6e]	64028	1			T25	14		T26	5		T12	1
valid_sources[0x6f]	66835	1			T25	8		T12	3		T13	21
valid_sources[0x70]	63775	1			T25	9		T26	4		T12	1
valid_sources[0x71]	66578	1			T24	1		T25	7		T14	1
valid_sources[0x72]	68585	1			T25	29		T26	3		T12	1
valid_sources[0x73]	64456	1			T25	21		T12	2		T13	1
valid_sources[0x74]	75043	1			T12	2		T13	14		T14	4
valid_sources[0x75]	71792	1			T25	12		T13	6		T19	4
valid_sources[0x76]	67839	1			T25	16		T12	1		T13	6
valid_sources[0x77]	70020	1			T26	7		T12	1		T13	3
valid_sources[0x78]	65902	1			T25	1		T12	2		T13	1
valid_sources[0x79]	66219	1			T25	14		T13	9		T14	1
valid_sources[0x7a]	72066	1			T12	1		T14	3		T15	6
valid_sources[0x7b]	70038	1			T25	1		T26	4		T13	4
valid_sources[0x7c]	68249	1			T12	1		T13	3		T14	1
valid_sources[0x7d]	67866	1			T25	18		T12	3		T13	4
valid_sources[0x7e]	107650	1			T25	24		T26	4		T12	2
valid_sources[0x7f]	65165	1			T25	26		T12	5		T13	5
valid_sources[0x80]	67373	1			T25	23		T26	2		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4283476

1

T25

1293

T26

83

T1

24294

values[0x0]

all_enables

biggest_size

5467212

1

T24

3

T25

179

T26

115

values[0x1]

all_enables

biggest_size

5465901

1

T24

4

T25

180

T26

133