Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1464181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5163837

1

T25

36

T26

107

T27

168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2969165	1			T25	22		T26	19		T27	173
values[0x0]	1823858	1			T25	14		T26	40		T27	41
values[0x1]	1834995	1			T25	11		T26	58		T27	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1163543	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5464475

1

T25

38

T26

107

T27

187

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19296	1			T27	2		T28	1		T30	1
valid_sources[0x01]	20385	1			T27	3		T29	5		T33	3
valid_sources[0x02]	20615	1			T26	1		T27	1		T29	2
valid_sources[0x03]	22226	1			T28	1		T31	1		T32	5
valid_sources[0x04]	21482	1			T27	2		T29	3		T30	2
valid_sources[0x05]	23515	1			T28	2		T29	2		T31	11
valid_sources[0x06]	19738	1			T27	1		T28	1		T29	8
valid_sources[0x07]	19565	1			T27	4		T28	1		T1	1
valid_sources[0x08]	20211	1			T27	1		T1	2		T11	1
valid_sources[0x09]	20888	1			T26	1		T28	1		T32	11
valid_sources[0x0a]	20806	1			T26	1		T27	2		T28	2
valid_sources[0x0b]	20494	1			T27	2		T31	1		T33	5
valid_sources[0x0c]	19360	1			T27	3		T28	2		T1	7
valid_sources[0x0d]	20428	1			T28	1		T33	23		T1	12
valid_sources[0x0e]	19843	1			T27	2		T28	1		T30	3
valid_sources[0x0f]	23040	1			T27	1		T12	6		T19	2
valid_sources[0x10]	19487	1			T26	1		T27	1		T29	6
valid_sources[0x11]	19807	1			T27	1		T29	6		T30	1
valid_sources[0x12]	19754	1			T26	3		T28	3		T1	1
valid_sources[0x13]	20055	1			T27	1		T28	3		T31	1
valid_sources[0x14]	20432	1			T26	1		T27	2		T28	1
valid_sources[0x15]	20544	1			T30	3		T32	1		T1	3
valid_sources[0x16]	21114	1			T26	2		T27	1		T28	2
valid_sources[0x17]	26408	1			T26	2		T28	1		T29	10
valid_sources[0x18]	21135	1			T27	1		T28	1		T29	1
valid_sources[0x19]	119615	1			T27	1		T28	2		T29	1
valid_sources[0x1a]	20221	1			T28	1		T29	1		T30	2
valid_sources[0x1b]	21419	1			T28	1		T1	12		T12	1
valid_sources[0x1c]	20445	1			T28	1		T29	6		T31	8
valid_sources[0x1d]	20170	1			T26	1		T27	2		T28	1
valid_sources[0x1e]	20957	1			T28	2		T31	10		T32	4
valid_sources[0x1f]	19607	1			T26	1		T27	1		T29	1
valid_sources[0x20]	24656	1			T26	2		T27	1		T28	2
valid_sources[0x21]	21929	1			T26	1		T27	1		T29	6
valid_sources[0x22]	19402	1			T27	1		T28	1		T30	6
valid_sources[0x23]	19728	1			T27	1		T28	2		T31	7
valid_sources[0x24]	19637	1			T27	2		T28	1		T32	3
valid_sources[0x25]	20058	1			T27	3		T28	2		T29	4
valid_sources[0x26]	19581	1			T27	2		T28	1		T29	2
valid_sources[0x27]	20264	1			T27	2		T28	1		T1	1
valid_sources[0x28]	19880	1			T27	2		T28	1		T30	3
valid_sources[0x29]	19459	1			T27	1		T28	1		T31	3
valid_sources[0x2a]	21131	1			T26	1		T27	1		T28	1
valid_sources[0x2b]	20835	1			T27	2		T30	6		T31	5
valid_sources[0x2c]	23370	1			T26	1		T27	1		T28	3
valid_sources[0x2d]	19924	1			T27	2		T28	3		T29	4
valid_sources[0x2e]	23822	1			T26	1		T27	1		T29	3
valid_sources[0x2f]	21543	1			T27	5		T29	3		T32	1
valid_sources[0x30]	20430	1			T28	1		T29	2		T30	2
valid_sources[0x31]	22391	1			T27	1		T28	1		T30	1
valid_sources[0x32]	19788	1			T26	1		T27	3		T28	4
valid_sources[0x33]	20852	1			T28	1		T1	5		T12	17
valid_sources[0x34]	20878	1			T26	1		T27	1		T28	1
valid_sources[0x35]	167755	1			T26	2		T28	3		T29	5
valid_sources[0x36]	57264	1			T27	3		T28	1		T30	1
valid_sources[0x37]	19848	1			T27	1		T28	1		T31	3
valid_sources[0x38]	20376	1			T27	1		T29	4		T31	1
valid_sources[0x39]	117771	1			T26	1		T28	1		T29	2
valid_sources[0x3a]	20849	1			T26	3		T28	2		T30	4
valid_sources[0x3b]	20261	1			T26	1		T27	1		T28	2
valid_sources[0x3c]	21918	1			T28	1		T1	5		T18	3
valid_sources[0x3d]	21238	1			T27	5		T28	1		T29	4
valid_sources[0x3e]	21341	1			T26	1		T27	2		T28	1
valid_sources[0x3f]	20393	1			T26	1		T27	1		T28	1
valid_sources[0x40]	20771	1			T26	2		T27	1		T28	1
valid_sources[0x41]	20967	1			T27	2		T29	1		T30	3
valid_sources[0x42]	19972	1			T26	1		T27	2		T28	2
valid_sources[0x43]	20584	1			T26	1		T27	1		T28	1
valid_sources[0x44]	19716	1			T27	1		T28	2		T29	2
valid_sources[0x45]	20031	1			T27	2		T28	2		T30	2
valid_sources[0x46]	24677	1			T26	1		T27	1		T28	1
valid_sources[0x47]	150916	1			T26	3		T28	4		T29	3
valid_sources[0x48]	22462	1			T28	4		T29	1		T30	2
valid_sources[0x49]	19962	1			T28	2		T1	5		T12	3
valid_sources[0x4a]	21851	1			T28	3		T32	3		T1	6
valid_sources[0x4b]	20614	1			T27	1		T29	3		T30	1
valid_sources[0x4c]	20088	1			T26	2		T29	1		T30	2
valid_sources[0x4d]	20155	1			T27	2		T32	5		T1	4
valid_sources[0x4e]	19535	1			T27	1		T32	10		T1	1
valid_sources[0x4f]	22448	1			T28	1		T30	3		T31	1
valid_sources[0x50]	19902	1			T26	1		T27	1		T32	6
valid_sources[0x51]	27116	1			T25	47		T27	1		T28	4
valid_sources[0x52]	22265	1			T26	1		T27	1		T32	3
valid_sources[0x53]	22026	1			T26	1		T28	3		T31	6
valid_sources[0x54]	23180	1			T27	2		T33	5		T11	1
valid_sources[0x55]	22060	1			T28	1		T30	2		T32	1
valid_sources[0x56]	19496	1			T26	1		T27	2		T28	1
valid_sources[0x57]	19468	1			T27	1		T31	3		T32	2
valid_sources[0x58]	19561	1			T29	4		T30	1		T31	1
valid_sources[0x59]	23016	1			T27	1		T28	1		T29	3
valid_sources[0x5a]	22204	1			T26	1		T27	1		T28	2
valid_sources[0x5b]	19856	1			T26	2		T30	2		T31	11
valid_sources[0x5c]	20064	1			T27	2		T28	2		T30	1
valid_sources[0x5d]	19778	1			T27	1		T28	1		T29	2
valid_sources[0x5e]	19746	1			T27	2		T28	1		T29	2
valid_sources[0x5f]	19286	1			T30	1		T32	1		T1	2
valid_sources[0x60]	20921	1			T27	2		T28	2		T30	2
valid_sources[0x61]	22234	1			T26	1		T28	2		T29	9
valid_sources[0x62]	154882	1			T27	3		T28	2		T31	3
valid_sources[0x63]	19516	1			T30	3		T1	5		T12	15
valid_sources[0x64]	24417	1			T27	1		T30	2		T32	4
valid_sources[0x65]	20727	1			T28	1		T29	1		T30	2
valid_sources[0x66]	21682	1			T28	1		T29	2		T33	1
valid_sources[0x67]	27700	1			T28	1		T29	7		T30	3
valid_sources[0x68]	20896	1			T28	2		T29	5		T32	5
valid_sources[0x69]	24093	1			T26	2		T27	2		T29	1
valid_sources[0x6a]	22636	1			T27	1		T28	2		T29	1
valid_sources[0x6b]	22750	1			T27	2		T30	1		T31	15
valid_sources[0x6c]	19572	1			T29	6		T33	7		T1	7
valid_sources[0x6d]	20032	1			T26	1		T27	1		T28	1
valid_sources[0x6e]	20838	1			T27	3		T29	5		T1	3
valid_sources[0x6f]	19472	1			T26	3		T27	3		T28	1
valid_sources[0x70]	20108	1			T27	3		T29	4		T1	10
valid_sources[0x71]	21299	1			T28	1		T33	37		T12	8
valid_sources[0x72]	23135	1			T28	2		T30	5		T1	14
valid_sources[0x73]	19574	1			T27	2		T28	1		T31	2
valid_sources[0x74]	19251	1			T27	2		T29	1		T1	1
valid_sources[0x75]	20788	1			T26	1		T1	3		T12	23
valid_sources[0x76]	20413	1			T27	2		T28	3		T30	1
valid_sources[0x77]	20583	1			T26	1		T28	2		T29	10
valid_sources[0x78]	19586	1			T29	1		T33	10		T1	4
valid_sources[0x79]	18952	1			T27	1		T28	7		T32	1
valid_sources[0x7a]	22583	1			T27	2		T28	1		T29	4
valid_sources[0x7b]	19812	1			T27	1		T28	2		T30	1
valid_sources[0x7c]	20636	1			T27	2		T28	1		T29	3
valid_sources[0x7d]	20657	1			T29	4		T31	5		T1	10
valid_sources[0x7e]	19939	1			T27	2		T28	1		T31	18
valid_sources[0x7f]	20590	1			T28	3		T29	3		T31	3
valid_sources[0x80]	21030	1			T28	3		T32	12		T1	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1520785

1

T25

11

T26

9

T27

82

values[0x0]

all_enables

biggest_size

1821984

1

T25

14

T26

40

T27

41

values[0x1]

all_enables

biggest_size

1821068

1

T25

11

T26

58

T27

45