Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2893130	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12449149

1

T41

190

T42

265

T43

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6252211	1			T41	139		T42	88		T43	16
values[0x0]	4475207	1			T41	61		T42	111		T43	20
values[0x1]	4614861	1			T41	59		T42	107		T43	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13105551

1

T41

203

T42

273

T43

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62478	1			T48	2		T69	1		T51	1
valid_sources[0x01]	52302	1			T48	3		T69	2		T51	5
valid_sources[0x02]	60133	1			T48	4		T51	9		T64	6
valid_sources[0x03]	52435	1			T48	3		T69	3		T51	4
valid_sources[0x04]	50910	1			T48	5		T51	4		T52	1
valid_sources[0x05]	58837	1			T48	7		T69	1		T51	7
valid_sources[0x06]	54389	1			T59	1		T69	2		T51	2
valid_sources[0x07]	58543	1			T48	2		T51	2		T52	2
valid_sources[0x08]	61698	1			T51	2		T52	1		T126	13
valid_sources[0x09]	49827	1			T48	3		T51	2		T52	3
valid_sources[0x0a]	64370	1			T48	5		T51	4		T52	2
valid_sources[0x0b]	55561	1			T51	6		T52	2		T79	1
valid_sources[0x0c]	54211	1			T48	7		T69	1		T51	3
valid_sources[0x0d]	56497	1			T48	12		T51	10		T52	3
valid_sources[0x0e]	50699	1			T48	7		T51	14		T52	3
valid_sources[0x0f]	56184	1			T48	2		T69	1		T51	11
valid_sources[0x10]	54777	1			T44	140		T48	3		T52	1
valid_sources[0x11]	50773	1			T48	3		T59	2		T51	2
valid_sources[0x12]	50781	1			T48	4		T51	4		T52	3
valid_sources[0x13]	51503	1			T48	3		T51	6		T52	1
valid_sources[0x14]	58598	1			T48	5		T69	1		T51	3
valid_sources[0x15]	54948	1			T48	4		T59	7		T69	1
valid_sources[0x16]	54956	1			T51	3		T52	3		T64	3
valid_sources[0x17]	61707	1			T48	1		T52	2		T64	3
valid_sources[0x18]	58748	1			T48	2		T51	1		T52	1
valid_sources[0x19]	55991	1			T48	4		T69	4		T51	8
valid_sources[0x1a]	54899	1			T48	2		T51	8		T52	1
valid_sources[0x1b]	61604	1			T48	5		T51	3		T77	61
valid_sources[0x1c]	59934	1			T48	4		T51	1		T52	2
valid_sources[0x1d]	46366	1			T69	2		T51	1		T52	2
valid_sources[0x1e]	54797	1			T48	7		T59	5		T69	2
valid_sources[0x1f]	51365	1			T48	6		T69	1		T51	3
valid_sources[0x20]	61816	1			T48	4		T51	5		T52	4
valid_sources[0x21]	53243	1			T48	3		T62	1		T51	7
valid_sources[0x22]	48862	1			T48	4		T69	1		T51	12
valid_sources[0x23]	51111	1			T51	5		T52	1		T64	2
valid_sources[0x24]	62548	1			T48	4		T69	1		T51	2
valid_sources[0x25]	53677	1			T48	2		T51	1		T128	34
valid_sources[0x26]	51206	1			T48	2		T51	6		T52	3
valid_sources[0x27]	49714	1			T48	2		T51	9		T52	5
valid_sources[0x28]	55621	1			T48	3		T51	1		T52	4
valid_sources[0x29]	188087	1			T48	9		T69	1		T51	1
valid_sources[0x2a]	51193	1			T46	111		T48	3		T69	1
valid_sources[0x2b]	54880	1			T48	1		T51	3		T52	2
valid_sources[0x2c]	54481	1			T48	4		T51	4		T52	2
valid_sources[0x2d]	50234	1			T48	2		T59	2		T69	2
valid_sources[0x2e]	61850	1			T48	4		T69	1		T51	7
valid_sources[0x2f]	53053	1			T48	6		T51	9		T52	4
valid_sources[0x30]	58115	1			T48	9		T59	4		T69	3
valid_sources[0x31]	52738	1			T48	3		T59	3		T69	1
valid_sources[0x32]	59465	1			T48	6		T69	3		T51	1
valid_sources[0x33]	57747	1			T69	2		T51	1		T52	2
valid_sources[0x34]	66043	1			T48	6		T69	1		T51	14
valid_sources[0x35]	53998	1			T48	15		T69	2		T51	1
valid_sources[0x36]	135228	1			T48	6		T49	1		T69	2
valid_sources[0x37]	46992	1			T48	2		T59	14		T69	1
valid_sources[0x38]	56502	1			T69	1		T51	1		T52	2
valid_sources[0x39]	56743	1			T48	3		T51	5		T78	1
valid_sources[0x3a]	50153	1			T48	5		T69	1		T51	1
valid_sources[0x3b]	64361	1			T46	55		T48	5		T51	5
valid_sources[0x3c]	62824	1			T48	4		T69	1		T51	1
valid_sources[0x3d]	65434	1			T48	3		T51	2		T52	2
valid_sources[0x3e]	55809	1			T59	3		T51	2		T52	5
valid_sources[0x3f]	62575	1			T48	3		T51	7		T52	3
valid_sources[0x40]	47694	1			T59	1		T51	7		T52	2
valid_sources[0x41]	50746	1			T48	9		T69	2		T51	12
valid_sources[0x42]	60472	1			T48	4		T69	1		T51	1
valid_sources[0x43]	54891	1			T48	7		T59	1		T69	2
valid_sources[0x44]	61975	1			T48	7		T69	1		T51	13
valid_sources[0x45]	56598	1			T48	6		T49	1		T51	8
valid_sources[0x46]	55667	1			T48	8		T69	1		T51	4
valid_sources[0x47]	57015	1			T48	3		T51	7		T52	3
valid_sources[0x48]	56347	1			T48	12		T69	1		T51	11
valid_sources[0x49]	55480	1			T48	8		T69	1		T51	1
valid_sources[0x4a]	54557	1			T69	2		T51	6		T52	3
valid_sources[0x4b]	49439	1			T48	2		T51	3		T129	2
valid_sources[0x4c]	154946	1			T48	4		T69	2		T51	3
valid_sources[0x4d]	53459	1			T48	10		T69	2		T51	12
valid_sources[0x4e]	50764	1			T47	272		T48	2		T69	1
valid_sources[0x4f]	64404	1			T48	5		T69	2		T52	5
valid_sources[0x50]	53981	1			T48	2		T69	2		T51	2
valid_sources[0x51]	56963	1			T48	4		T69	3		T51	7
valid_sources[0x52]	60334	1			T48	1		T51	2		T64	2
valid_sources[0x53]	51641	1			T48	11		T69	1		T51	3
valid_sources[0x54]	56655	1			T48	2		T51	1		T52	4
valid_sources[0x55]	52717	1			T48	2		T51	3		T52	3
valid_sources[0x56]	151824	1			T48	4		T69	1		T51	2
valid_sources[0x57]	58200	1			T48	3		T69	1		T51	6
valid_sources[0x58]	63961	1			T51	2		T52	2		T129	7
valid_sources[0x59]	54461	1			T48	4		T59	2		T69	1
valid_sources[0x5a]	55624	1			T48	7		T51	12		T52	4
valid_sources[0x5b]	51384	1			T48	2		T59	12		T69	2
valid_sources[0x5c]	50934	1			T51	12		T52	1		T129	1
valid_sources[0x5d]	51419	1			T69	3		T51	4		T52	3
valid_sources[0x5e]	54888	1			T48	1		T69	1		T51	6
valid_sources[0x5f]	61080	1			T48	7		T69	1		T52	1
valid_sources[0x60]	55111	1			T48	5		T69	2		T51	2
valid_sources[0x61]	55326	1			T48	3		T51	3		T52	5
valid_sources[0x62]	49689	1			T48	5		T69	2		T51	1
valid_sources[0x63]	63122	1			T48	7		T69	4		T51	1
valid_sources[0x64]	49646	1			T48	2		T51	2		T52	2
valid_sources[0x65]	57995	1			T48	1		T69	1		T51	3
valid_sources[0x66]	48053	1			T48	9		T49	1		T51	4
valid_sources[0x67]	56667	1			T48	6		T51	7		T52	2
valid_sources[0x68]	56803	1			T51	1		T52	4		T125	19
valid_sources[0x69]	62729	1			T48	3		T64	11		T79	3
valid_sources[0x6a]	62951	1			T48	4		T51	5		T77	1
valid_sources[0x6b]	63368	1			T48	2		T51	7		T52	2
valid_sources[0x6c]	59132	1			T51	3		T52	2		T64	2
valid_sources[0x6d]	56838	1			T48	7		T51	7		T79	10
valid_sources[0x6e]	52445	1			T48	5		T51	3		T52	1
valid_sources[0x6f]	56132	1			T42	306		T48	5		T51	14
valid_sources[0x70]	53279	1			T48	5		T69	2		T51	3
valid_sources[0x71]	50955	1			T48	6		T52	3		T79	4
valid_sources[0x72]	56542	1			T48	9		T59	1		T69	1
valid_sources[0x73]	53510	1			T48	10		T69	2		T51	2
valid_sources[0x74]	57622	1			T48	5		T51	8		T52	4
valid_sources[0x75]	56092	1			T48	7		T51	11		T52	4
valid_sources[0x76]	63160	1			T48	3		T51	3		T52	5
valid_sources[0x77]	59865	1			T48	1		T59	13		T69	2
valid_sources[0x78]	55796	1			T48	2		T59	7		T69	1
valid_sources[0x79]	51291	1			T48	1		T69	2		T51	3
valid_sources[0x7a]	53530	1			T48	2		T59	4		T69	1
valid_sources[0x7b]	59634	1			T48	8		T69	3		T51	4
valid_sources[0x7c]	58639	1			T48	2		T51	6		T52	1
valid_sources[0x7d]	64573	1			T48	5		T49	1		T51	2
valid_sources[0x7e]	50080	1			T59	2		T69	3		T51	2
valid_sources[0x7f]	54464	1			T48	5		T51	2		T52	4
valid_sources[0x80]	59199	1			T48	2		T59	6		T51	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3527230

1

T41

70

T42

47

T43

10

values[0x0]

all_enables

biggest_size

4460906

1

T41

61

T42

111

T43

20

values[0x1]

all_enables

biggest_size

4461013

1

T41

59

T42

107

T43

28