Module Definition
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Module : prim_filter_ctr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_filter[0].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[1].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[2].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[3].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[4].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[5].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[6].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[7].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[8].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[9].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[10].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[11].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[12].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[13].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[14].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[15].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[16].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[17].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[18].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[19].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[20].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[21].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[22].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[23].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[24].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[25].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[26].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[27].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[28].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[29].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[30].u_filter 100.00 100.00 100.00 100.00
tb.dut.gen_filter[31].u_filter 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_filter[0].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[1].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[2].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[3].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[4].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[5].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[6].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[7].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_filter[8].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_filter[9].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[10].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[11].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[12].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[13].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[14].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[15].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[16].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[17].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[18].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[19].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[20].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[21].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[22].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[23].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[24].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[25].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[26].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[27].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[28].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[29].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[30].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_filter[31].u_filter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Module : prim_filter_ctr
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Module : prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[0].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[0].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[0].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[1].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[1].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[1].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[2].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[2].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[2].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[3].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[3].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[3].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[4].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[4].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[4].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[5].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[5].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[5].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[6].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[6].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[6].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[7].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[7].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[7].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[8].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[8].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[8].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[9].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[9].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[9].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[10].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[10].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[10].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[11].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[11].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[11].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[12].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[12].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[12].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[13].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[13].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[13].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[14].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[14].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[14].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[15].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[15].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[15].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[16].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[16].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[16].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[17].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[17].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[17].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[18].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[18].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[18].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[19].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[19].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[19].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[20].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[20].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[20].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[21].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[21].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[21].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[22].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[22].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[22].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[23].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[23].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[23].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[24].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[24].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[24].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[25].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[25].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[25].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[26].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[26].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[26].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[27].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[27].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T27,T28

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T27,T28

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[27].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T27,T28
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[28].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[28].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[28].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[29].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[29].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[29].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[30].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[30].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[30].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

Line Coverage for Instance : tb.dut.gen_filter[31].u_filter
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00

45 end else begin : gen_sync 46 1/1 assign filter_synced = filter_i; Tests: T25 T26 T27  47 end 48 49 always_ff @(posedge clk_i or negedge rst_ni) begin 50 1/1 if (!rst_ni) begin Tests: T25 T26 T27  51 1/1 filter_q <= 1'b0; Tests: T25 T26 T27  52 end else begin 53 1/1 filter_q <= filter_synced; Tests: T25 T26 T27  54 end 55 end 56 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T25 T26 T27  59 1/1 stored_value_q <= 1'b0; Tests: T25 T26 T27  60 1/1 end else if (update_stored_value) begin Tests: T25 T26 T27  61 1/1 stored_value_q <= filter_synced; Tests: T25 T26 T27  62 end MISSING_ELSE 63 end 64 65 always_ff @(posedge clk_i or negedge rst_ni) begin 66 1/1 if (!rst_ni) begin Tests: T25 T26 T27  67 1/1 diff_ctr_q <= '0; Tests: T25 T26 T27  68 end else begin 69 1/1 diff_ctr_q <= diff_ctr_d; Tests: T25 T26 T27  70 end 71 end 72 73 // always look for differences, even if not filter enabled 74 1/1 assign update_stored_value = (diff_ctr_d == thresh_i); Tests: T25 T26 T27  75 1/1 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart Tests: T25 T26 T27  76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate 77 (diff_ctr_q + 1'b1); // count up 78 79 1/1 assign filter_o = enable_i ? stored_value_q : filter_synced; Tests: T25 T26 T27 

Cond Coverage for Instance : tb.dut.gen_filter[31].u_filter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T12

Branch Coverage for Instance : tb.dut.gen_filter[31].u_filter
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 75 3 3 100.00
TERNARY 79 2 2 100.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00


75 assign diff_ctr_d = (filter_synced != filter_q) ? '0 : // restart -1- ==> 76 (diff_ctr_q >= thresh_i) ? thresh_i : // saturate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


79 assign filter_o = enable_i ? stored_value_q : filter_synced; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T30,T32,T12
0 Covered T25,T26,T27


50 if (!rst_ni) begin -1- 51 filter_q <= 1'b0; ==> 52 end else begin 53 filter_q <= filter_synced; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


58 if (!rst_ni) begin -1- 59 stored_value_q <= 1'b0; ==> 60 end else if (update_stored_value) begin -2- 61 stored_value_q <= filter_synced; ==> 62 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T25,T26,T27
0 0 Covered T25,T26,T27


66 if (!rst_ni) begin -1- 67 diff_ctr_q <= '0; ==> 68 end else begin 69 diff_ctr_q <= diff_ctr_d; ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%