Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123412340	0	0	0
ctrl_en_input_filter_rd_A	123412340	78599	0	0
intr_ctrl_en_falling_rd_A	123412340	82049	0	0
intr_ctrl_en_lvlhigh_rd_A	123412340	78765	0	0
intr_ctrl_en_lvllow_rd_A	123412340	80811	0	0
intr_ctrl_en_rising_rd_A	123412340	78762	0	0
intr_enable_rd_A	123412340	79839	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	78599	0	0
T1	36173	233	0	0
T2	3213	1	0	0
T3	37609	279	0	0
T4	0	42	0	0
T5	0	108	0	0
T6	0	6	0	0
T7	0	1651	0	0
T8	0	7	0	0
T9	0	2215	0	0
T10	0	2047	0	0
T11	7613	0	0	0
T12	5881	0	0	0
T13	4753	0	0	0
T14	2985	0	0	0
T15	7165	0	0	0
T16	3717	0	0	0
T17	11274	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	82049	0	0
T1	0	235	0	0
T3	0	280	0	0
T4	0	51	0	0
T5	0	88	0	0
T6	0	8	0	0
T7	0	1933	0	0
T9	0	2265	0	0
T10	0	1889	0	0
T18	7419	1	0	0
T19	0	146	0	0
T20	5591	0	0	0
T21	2367	0	0	0
T22	1573	0	0	0
T23	26054	0	0	0
T24	3872	0	0	0
T25	1660	0	0	0
T26	15976	0	0	0
T27	2545	0	0	0
T28	11886	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	78765	0	0
T1	0	210	0	0
T3	0	215	0	0
T4	0	58	0	0
T5	0	186	0	0
T6	0	11	0	0
T7	0	1747	0	0
T9	0	2003	0	0
T10	0	1992	0	0
T18	7419	7	0	0
T20	5591	0	0	0
T21	2367	0	0	0
T22	1573	0	0	0
T23	26054	0	0	0
T24	3872	0	0	0
T25	1660	0	0	0
T26	15976	0	0	0
T27	2545	0	0	0
T28	11886	0	0	0
T29	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	80811	0	0
T1	0	214	0	0
T3	0	300	0	0
T4	0	46	0	0
T5	0	114	0	0
T6	0	2	0	0
T7	0	1564	0	0
T9	0	2240	0	0
T10	0	1908	0	0
T18	0	3	0	0
T30	4676	1	0	0
T31	2168	0	0	0
T32	2410	0	0	0
T33	2681	0	0	0
T34	5006	0	0	0
T35	1605	0	0	0
T36	9342	0	0	0
T37	6877	0	0	0
T38	5379	0	0	0
T39	2165	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	78762	0	0
T1	0	278	0	0
T3	0	216	0	0
T4	0	29	0	0
T5	0	122	0	0
T6	0	3	0	0
T7	0	1671	0	0
T9	0	2253	0	0
T18	0	3	0	0
T30	4676	8	0	0
T31	2168	0	0	0
T32	2410	0	0	0
T33	2681	0	0	0
T34	5006	0	0	0
T35	1605	0	0	0
T36	9342	0	0	0
T37	6877	0	0	0
T38	5379	0	0	0
T39	2165	0	0	0
T40	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123412340	79839	0	0
T1	0	280	0	0
T3	0	231	0	0
T4	0	53	0	0
T5	0	90	0	0
T6	0	3	0	0
T7	0	1862	0	0
T9	0	2527	0	0
T10	0	1716	0	0
T29	0	4	0	0
T30	4676	4	0	0
T31	2168	0	0	0
T32	2410	0	0	0
T33	2681	0	0	0
T34	5006	0	0	0
T35	1605	0	0	0
T36	9342	0	0	0
T37	6877	0	0	0
T38	5379	0	0	0
T39	2165	0	0	0