Module Definition
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Module : gpio_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.75 100.00 99.01 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.75 100.00 99.01 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.75 100.00 99.01 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.03 97.69 98.53 100.00 98.95 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_ctrl_en_input_filter 100.00 100.00 100.00 100.00
u_data_in 67.59 77.78 50.00 75.00
u_direct_oe 100.00 100.00
u_direct_out 100.00 100.00
u_intr_ctrl_en_falling 100.00 100.00 100.00 100.00
u_intr_ctrl_en_lvlhigh 100.00 100.00 100.00 100.00
u_intr_ctrl_en_lvllow 100.00 100.00 100.00 100.00
u_intr_ctrl_en_rising 100.00 100.00 100.00 100.00
u_intr_enable 100.00 100.00 100.00 100.00
u_intr_state 100.00 100.00 100.00 100.00
u_intr_test 100.00 100.00
u_masked_oe_lower_data 100.00 100.00
u_masked_oe_lower_mask 75.00 75.00
u_masked_oe_upper_data 100.00 100.00
u_masked_oe_upper_mask 75.00 75.00
u_masked_out_lower_data 100.00 100.00
u_masked_out_lower_mask 66.67 66.67
u_masked_out_upper_data 100.00 100.00
u_masked_out_upper_mask 66.67 66.67
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : gpio_reg_top
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67 always_ff @(posedge clk_i or negedge rst_ni) begin 68 1/1 if (!rst_ni) begin Tests: T25 T26 T27  69 1/1 err_q <= '0; Tests: T25 T26 T27  70 1/1 end else if (intg_err || reg_we_err) begin Tests: T25 T26 T27  71 1/1 err_q <= 1'b1; Tests: T13 T43 T44  72 end MISSING_ELSE 73 end 74 75 // integrity error output is permanent and should be used for alert generation 76 // register errors are transactional 77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err; Tests: T25 T26 T27  78 79 // outgoing integrity generation 80 tlul_pkg::tl_d2h_t tl_o_pre; 81 tlul_rsp_intg_gen #( 82 .EnableRspIntgGen(1), 83 .EnableDataIntgGen(1) 84 ) u_rsp_intg_gen ( 85 .tl_i(tl_o_pre), 86 .tl_o(tl_o) 87 ); 88 89 1/1 assign tl_reg_h2d = tl_i; Tests: T25 T26 T27  90 1/1 assign tl_o_pre = tl_reg_d2h; Tests: T25 T26 T27  91 92 tlul_adapter_reg #( 93 .RegAw(AW), 94 .RegDw(DW), 95 .EnableDataIntgGen(0) 96 ) u_reg_if ( 97 .clk_i (clk_i), 98 .rst_ni (rst_ni), 99 100 .tl_i (tl_reg_h2d), 101 .tl_o (tl_reg_d2h), 102 103 .en_ifetch_i(prim_mubi_pkg::MuBi4False), 104 .intg_error_o(), 105 106 .we_o (reg_we), 107 .re_o (reg_re), 108 .addr_o (reg_addr), 109 .wdata_o (reg_wdata), 110 .be_o (reg_be), 111 .busy_i (reg_busy), 112 .rdata_i (reg_rdata), 113 .error_i (reg_error) 114 ); 115 116 // cdc oversampling signals 117 118 1/1 assign reg_rdata = reg_rdata_next ; Tests: T25 T26 T27  119 1/1 assign reg_error = addrmiss | wr_err | intg_err; Tests: T36 T37 T38  120 121 // Define SW related signals 122 // Format: <reg>_<field>_{wd|we|qs} 123 // or <reg>_{wd|we|qs} if field == 1 or 0 124 logic intr_state_we; 125 logic [31:0] intr_state_qs; 126 logic [31:0] intr_state_wd; 127 logic intr_enable_we; 128 logic [31:0] intr_enable_qs; 129 logic [31:0] intr_enable_wd; 130 logic intr_test_we; 131 logic [31:0] intr_test_wd; 132 logic alert_test_we; 133 logic alert_test_wd; 134 logic [31:0] data_in_qs; 135 logic direct_out_re; 136 logic direct_out_we; 137 logic [31:0] direct_out_qs; 138 logic [31:0] direct_out_wd; 139 logic masked_out_lower_re; 140 logic masked_out_lower_we; 141 logic [15:0] masked_out_lower_data_qs; 142 logic [15:0] masked_out_lower_data_wd; 143 logic [15:0] masked_out_lower_mask_wd; 144 logic masked_out_upper_re; 145 logic masked_out_upper_we; 146 logic [15:0] masked_out_upper_data_qs; 147 logic [15:0] masked_out_upper_data_wd; 148 logic [15:0] masked_out_upper_mask_wd; 149 logic direct_oe_re; 150 logic direct_oe_we; 151 logic [31:0] direct_oe_qs; 152 logic [31:0] direct_oe_wd; 153 logic masked_oe_lower_re; 154 logic masked_oe_lower_we; 155 logic [15:0] masked_oe_lower_data_qs; 156 logic [15:0] masked_oe_lower_data_wd; 157 logic [15:0] masked_oe_lower_mask_qs; 158 logic [15:0] masked_oe_lower_mask_wd; 159 logic masked_oe_upper_re; 160 logic masked_oe_upper_we; 161 logic [15:0] masked_oe_upper_data_qs; 162 logic [15:0] masked_oe_upper_data_wd; 163 logic [15:0] masked_oe_upper_mask_qs; 164 logic [15:0] masked_oe_upper_mask_wd; 165 logic intr_ctrl_en_rising_we; 166 logic [31:0] intr_ctrl_en_rising_qs; 167 logic [31:0] intr_ctrl_en_rising_wd; 168 logic intr_ctrl_en_falling_we; 169 logic [31:0] intr_ctrl_en_falling_qs; 170 logic [31:0] intr_ctrl_en_falling_wd; 171 logic intr_ctrl_en_lvlhigh_we; 172 logic [31:0] intr_ctrl_en_lvlhigh_qs; 173 logic [31:0] intr_ctrl_en_lvlhigh_wd; 174 logic intr_ctrl_en_lvllow_we; 175 logic [31:0] intr_ctrl_en_lvllow_qs; 176 logic [31:0] intr_ctrl_en_lvllow_wd; 177 logic ctrl_en_input_filter_we; 178 logic [31:0] ctrl_en_input_filter_qs; 179 logic [31:0] ctrl_en_input_filter_wd; 180 181 // Register instances 182 // R[intr_state]: V(False) 183 prim_subreg #( 184 .DW (32), 185 .SwAccess(prim_subreg_pkg::SwAccessW1C), 186 .RESVAL (32'h0), 187 .Mubi (1'b0) 188 ) u_intr_state ( 189 .clk_i (clk_i), 190 .rst_ni (rst_ni), 191 192 // from register interface 193 .we (intr_state_we), 194 .wd (intr_state_wd), 195 196 // from internal hardware 197 .de (hw2reg.intr_state.de), 198 .d (hw2reg.intr_state.d), 199 200 // to internal hardware 201 .qe (), 202 .q (reg2hw.intr_state.q), 203 .ds (), 204 205 // to register interface (read) 206 .qs (intr_state_qs) 207 ); 208 209 210 // R[intr_enable]: V(False) 211 prim_subreg #( 212 .DW (32), 213 .SwAccess(prim_subreg_pkg::SwAccessRW), 214 .RESVAL (32'h0), 215 .Mubi (1'b0) 216 ) u_intr_enable ( 217 .clk_i (clk_i), 218 .rst_ni (rst_ni), 219 220 // from register interface 221 .we (intr_enable_we), 222 .wd (intr_enable_wd), 223 224 // from internal hardware 225 .de (1'b0), 226 .d ('0), 227 228 // to internal hardware 229 .qe (), 230 .q (reg2hw.intr_enable.q), 231 .ds (), 232 233 // to register interface (read) 234 .qs (intr_enable_qs) 235 ); 236 237 238 // R[intr_test]: V(True) 239 logic intr_test_qe; 240 logic [0:0] intr_test_flds_we; 241 1/1 assign intr_test_qe = &intr_test_flds_we; Tests: T30 T1 T19  242 prim_subreg_ext #( 243 .DW (32) 244 ) u_intr_test ( 245 .re (1'b0), 246 .we (intr_test_we), 247 .wd (intr_test_wd), 248 .d ('0), 249 .qre (), 250 .qe (intr_test_flds_we[0]), 251 .q (reg2hw.intr_test.q), 252 .ds (), 253 .qs () 254 ); 255 1/1 assign reg2hw.intr_test.qe = intr_test_qe; Tests: T30 T1 T19  256 257 258 // R[alert_test]: V(True) 259 logic alert_test_qe; 260 logic [0:0] alert_test_flds_we; 261 1/1 assign alert_test_qe = &alert_test_flds_we; Tests: T11 T17 T45  262 prim_subreg_ext #( 263 .DW (1) 264 ) u_alert_test ( 265 .re (1'b0), 266 .we (alert_test_we), 267 .wd (alert_test_wd), 268 .d ('0), 269 .qre (), 270 .qe (alert_test_flds_we[0]), 271 .q (reg2hw.alert_test.q), 272 .ds (), 273 .qs () 274 ); 275 1/1 assign reg2hw.alert_test.qe = alert_test_qe; Tests: T11 T17 T45  276 277 278 // R[data_in]: V(False) 279 prim_subreg #( 280 .DW (32), 281 .SwAccess(prim_subreg_pkg::SwAccessRO), 282 .RESVAL (32'h0), 283 .Mubi (1'b0) 284 ) u_data_in ( 285 .clk_i (clk_i), 286 .rst_ni (rst_ni), 287 288 // from register interface 289 .we (1'b0), 290 .wd ('0), 291 292 // from internal hardware 293 .de (hw2reg.data_in.de), 294 .d (hw2reg.data_in.d), 295 296 // to internal hardware 297 .qe (), 298 .q (), 299 .ds (), 300 301 // to register interface (read) 302 .qs (data_in_qs) 303 ); 304 305 306 // R[direct_out]: V(True) 307 logic direct_out_qe; 308 logic [0:0] direct_out_flds_we; 309 1/1 assign direct_out_qe = &direct_out_flds_we; Tests: T25 T26 T27  310 prim_subreg_ext #( 311 .DW (32) 312 ) u_direct_out ( 313 .re (direct_out_re), 314 .we (direct_out_we), 315 .wd (direct_out_wd), 316 .d (hw2reg.direct_out.d), 317 .qre (), 318 .qe (direct_out_flds_we[0]), 319 .q (reg2hw.direct_out.q), 320 .ds (), 321 .qs (direct_out_qs) 322 ); 323 1/1 assign reg2hw.direct_out.qe = direct_out_qe; Tests: T25 T26 T27  324 325 326 // R[masked_out_lower]: V(True) 327 logic masked_out_lower_qe; 328 logic [1:0] masked_out_lower_flds_we; 329 1/1 assign masked_out_lower_qe = &masked_out_lower_flds_we; Tests: T25 T26 T29  330 // F[data]: 15:0 331 prim_subreg_ext #( 332 .DW (16) 333 ) u_masked_out_lower_data ( 334 .re (masked_out_lower_re), 335 .we (masked_out_lower_we), 336 .wd (masked_out_lower_data_wd), 337 .d (hw2reg.masked_out_lower.data.d), 338 .qre (), 339 .qe (masked_out_lower_flds_we[0]), 340 .q (reg2hw.masked_out_lower.data.q), 341 .ds (), 342 .qs (masked_out_lower_data_qs) 343 ); 344 1/1 assign reg2hw.masked_out_lower.data.qe = masked_out_lower_qe; Tests: T25 T26 T29  345 346 // F[mask]: 31:16 347 prim_subreg_ext #( 348 .DW (16) 349 ) u_masked_out_lower_mask ( 350 .re (1'b0), 351 .we (masked_out_lower_we), 352 .wd (masked_out_lower_mask_wd), 353 .d (hw2reg.masked_out_lower.mask.d), 354 .qre (), 355 .qe (masked_out_lower_flds_we[1]), 356 .q (reg2hw.masked_out_lower.mask.q), 357 .ds (), 358 .qs () 359 ); 360 1/1 assign reg2hw.masked_out_lower.mask.qe = masked_out_lower_qe; Tests: T25 T26 T29  361 362 363 // R[masked_out_upper]: V(True) 364 logic masked_out_upper_qe; 365 logic [1:0] masked_out_upper_flds_we; 366 1/1 assign masked_out_upper_qe = &masked_out_upper_flds_we; Tests: T25 T26 T29  367 // F[data]: 15:0 368 prim_subreg_ext #( 369 .DW (16) 370 ) u_masked_out_upper_data ( 371 .re (masked_out_upper_re), 372 .we (masked_out_upper_we), 373 .wd (masked_out_upper_data_wd), 374 .d (hw2reg.masked_out_upper.data.d), 375 .qre (), 376 .qe (masked_out_upper_flds_we[0]), 377 .q (reg2hw.masked_out_upper.data.q), 378 .ds (), 379 .qs (masked_out_upper_data_qs) 380 ); 381 1/1 assign reg2hw.masked_out_upper.data.qe = masked_out_upper_qe; Tests: T25 T26 T29  382 383 // F[mask]: 31:16 384 prim_subreg_ext #( 385 .DW (16) 386 ) u_masked_out_upper_mask ( 387 .re (1'b0), 388 .we (masked_out_upper_we), 389 .wd (masked_out_upper_mask_wd), 390 .d (hw2reg.masked_out_upper.mask.d), 391 .qre (), 392 .qe (masked_out_upper_flds_we[1]), 393 .q (reg2hw.masked_out_upper.mask.q), 394 .ds (), 395 .qs () 396 ); 397 1/1 assign reg2hw.masked_out_upper.mask.qe = masked_out_upper_qe; Tests: T25 T26 T29  398 399 400 // R[direct_oe]: V(True) 401 logic direct_oe_qe; 402 logic [0:0] direct_oe_flds_we; 403 1/1 assign direct_oe_qe = &direct_oe_flds_we; Tests: T25 T26 T27  404 prim_subreg_ext #( 405 .DW (32) 406 ) u_direct_oe ( 407 .re (direct_oe_re), 408 .we (direct_oe_we), 409 .wd (direct_oe_wd), 410 .d (hw2reg.direct_oe.d), 411 .qre (), 412 .qe (direct_oe_flds_we[0]), 413 .q (reg2hw.direct_oe.q), 414 .ds (), 415 .qs (direct_oe_qs) 416 ); 417 1/1 assign reg2hw.direct_oe.qe = direct_oe_qe; Tests: T25 T26 T27  418 419 420 // R[masked_oe_lower]: V(True) 421 logic masked_oe_lower_qe; 422 logic [1:0] masked_oe_lower_flds_we; 423 1/1 assign masked_oe_lower_qe = &masked_oe_lower_flds_we; Tests: T25 T26 T29  424 // F[data]: 15:0 425 prim_subreg_ext #( 426 .DW (16) 427 ) u_masked_oe_lower_data ( 428 .re (masked_oe_lower_re), 429 .we (masked_oe_lower_we), 430 .wd (masked_oe_lower_data_wd), 431 .d (hw2reg.masked_oe_lower.data.d), 432 .qre (), 433 .qe (masked_oe_lower_flds_we[0]), 434 .q (reg2hw.masked_oe_lower.data.q), 435 .ds (), 436 .qs (masked_oe_lower_data_qs) 437 ); 438 1/1 assign reg2hw.masked_oe_lower.data.qe = masked_oe_lower_qe; Tests: T25 T26 T29  439 440 // F[mask]: 31:16 441 prim_subreg_ext #( 442 .DW (16) 443 ) u_masked_oe_lower_mask ( 444 .re (masked_oe_lower_re), 445 .we (masked_oe_lower_we), 446 .wd (masked_oe_lower_mask_wd), 447 .d (hw2reg.masked_oe_lower.mask.d), 448 .qre (), 449 .qe (masked_oe_lower_flds_we[1]), 450 .q (reg2hw.masked_oe_lower.mask.q), 451 .ds (), 452 .qs (masked_oe_lower_mask_qs) 453 ); 454 1/1 assign reg2hw.masked_oe_lower.mask.qe = masked_oe_lower_qe; Tests: T25 T26 T29  455 456 457 // R[masked_oe_upper]: V(True) 458 logic masked_oe_upper_qe; 459 logic [1:0] masked_oe_upper_flds_we; 460 1/1 assign masked_oe_upper_qe = &masked_oe_upper_flds_we; Tests: T25 T26 T29  461 // F[data]: 15:0 462 prim_subreg_ext #( 463 .DW (16) 464 ) u_masked_oe_upper_data ( 465 .re (masked_oe_upper_re), 466 .we (masked_oe_upper_we), 467 .wd (masked_oe_upper_data_wd), 468 .d (hw2reg.masked_oe_upper.data.d), 469 .qre (), 470 .qe (masked_oe_upper_flds_we[0]), 471 .q (reg2hw.masked_oe_upper.data.q), 472 .ds (), 473 .qs (masked_oe_upper_data_qs) 474 ); 475 1/1 assign reg2hw.masked_oe_upper.data.qe = masked_oe_upper_qe; Tests: T25 T26 T29  476 477 // F[mask]: 31:16 478 prim_subreg_ext #( 479 .DW (16) 480 ) u_masked_oe_upper_mask ( 481 .re (masked_oe_upper_re), 482 .we (masked_oe_upper_we), 483 .wd (masked_oe_upper_mask_wd), 484 .d (hw2reg.masked_oe_upper.mask.d), 485 .qre (), 486 .qe (masked_oe_upper_flds_we[1]), 487 .q (reg2hw.masked_oe_upper.mask.q), 488 .ds (), 489 .qs (masked_oe_upper_mask_qs) 490 ); 491 1/1 assign reg2hw.masked_oe_upper.mask.qe = masked_oe_upper_qe; Tests: T25 T26 T29  492 493 494 // R[intr_ctrl_en_rising]: V(False) 495 prim_subreg #( 496 .DW (32), 497 .SwAccess(prim_subreg_pkg::SwAccessRW), 498 .RESVAL (32'h0), 499 .Mubi (1'b0) 500 ) u_intr_ctrl_en_rising ( 501 .clk_i (clk_i), 502 .rst_ni (rst_ni), 503 504 // from register interface 505 .we (intr_ctrl_en_rising_we), 506 .wd (intr_ctrl_en_rising_wd), 507 508 // from internal hardware 509 .de (1'b0), 510 .d ('0), 511 512 // to internal hardware 513 .qe (), 514 .q (reg2hw.intr_ctrl_en_rising.q), 515 .ds (), 516 517 // to register interface (read) 518 .qs (intr_ctrl_en_rising_qs) 519 ); 520 521 522 // R[intr_ctrl_en_falling]: V(False) 523 prim_subreg #( 524 .DW (32), 525 .SwAccess(prim_subreg_pkg::SwAccessRW), 526 .RESVAL (32'h0), 527 .Mubi (1'b0) 528 ) u_intr_ctrl_en_falling ( 529 .clk_i (clk_i), 530 .rst_ni (rst_ni), 531 532 // from register interface 533 .we (intr_ctrl_en_falling_we), 534 .wd (intr_ctrl_en_falling_wd), 535 536 // from internal hardware 537 .de (1'b0), 538 .d ('0), 539 540 // to internal hardware 541 .qe (), 542 .q (reg2hw.intr_ctrl_en_falling.q), 543 .ds (), 544 545 // to register interface (read) 546 .qs (intr_ctrl_en_falling_qs) 547 ); 548 549 550 // R[intr_ctrl_en_lvlhigh]: V(False) 551 prim_subreg #( 552 .DW (32), 553 .SwAccess(prim_subreg_pkg::SwAccessRW), 554 .RESVAL (32'h0), 555 .Mubi (1'b0) 556 ) u_intr_ctrl_en_lvlhigh ( 557 .clk_i (clk_i), 558 .rst_ni (rst_ni), 559 560 // from register interface 561 .we (intr_ctrl_en_lvlhigh_we), 562 .wd (intr_ctrl_en_lvlhigh_wd), 563 564 // from internal hardware 565 .de (1'b0), 566 .d ('0), 567 568 // to internal hardware 569 .qe (), 570 .q (reg2hw.intr_ctrl_en_lvlhigh.q), 571 .ds (), 572 573 // to register interface (read) 574 .qs (intr_ctrl_en_lvlhigh_qs) 575 ); 576 577 578 // R[intr_ctrl_en_lvllow]: V(False) 579 prim_subreg #( 580 .DW (32), 581 .SwAccess(prim_subreg_pkg::SwAccessRW), 582 .RESVAL (32'h0), 583 .Mubi (1'b0) 584 ) u_intr_ctrl_en_lvllow ( 585 .clk_i (clk_i), 586 .rst_ni (rst_ni), 587 588 // from register interface 589 .we (intr_ctrl_en_lvllow_we), 590 .wd (intr_ctrl_en_lvllow_wd), 591 592 // from internal hardware 593 .de (1'b0), 594 .d ('0), 595 596 // to internal hardware 597 .qe (), 598 .q (reg2hw.intr_ctrl_en_lvllow.q), 599 .ds (), 600 601 // to register interface (read) 602 .qs (intr_ctrl_en_lvllow_qs) 603 ); 604 605 606 // R[ctrl_en_input_filter]: V(False) 607 prim_subreg #( 608 .DW (32), 609 .SwAccess(prim_subreg_pkg::SwAccessRW), 610 .RESVAL (32'h0), 611 .Mubi (1'b0) 612 ) u_ctrl_en_input_filter ( 613 .clk_i (clk_i), 614 .rst_ni (rst_ni), 615 616 // from register interface 617 .we (ctrl_en_input_filter_we), 618 .wd (ctrl_en_input_filter_wd), 619 620 // from internal hardware 621 .de (1'b0), 622 .d ('0), 623 624 // to internal hardware 625 .qe (), 626 .q (reg2hw.ctrl_en_input_filter.q), 627 .ds (), 628 629 // to register interface (read) 630 .qs (ctrl_en_input_filter_qs) 631 ); 632 633 634 635 logic [15:0] addr_hit; 636 always_comb begin 637 1/1 addr_hit = '0; Tests: T25 T26 T27  638 1/1 addr_hit[ 0] = (reg_addr == GPIO_INTR_STATE_OFFSET); Tests: T25 T26 T27  639 1/1 addr_hit[ 1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET); Tests: T25 T26 T27  640 1/1 addr_hit[ 2] = (reg_addr == GPIO_INTR_TEST_OFFSET); Tests: T25 T26 T27  641 1/1 addr_hit[ 3] = (reg_addr == GPIO_ALERT_TEST_OFFSET); Tests: T25 T26 T27  642 1/1 addr_hit[ 4] = (reg_addr == GPIO_DATA_IN_OFFSET); Tests: T25 T26 T27  643 1/1 addr_hit[ 5] = (reg_addr == GPIO_DIRECT_OUT_OFFSET); Tests: T25 T26 T27  644 1/1 addr_hit[ 6] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET); Tests: T25 T26 T27  645 1/1 addr_hit[ 7] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET); Tests: T25 T26 T27  646 1/1 addr_hit[ 8] = (reg_addr == GPIO_DIRECT_OE_OFFSET); Tests: T25 T26 T27  647 1/1 addr_hit[ 9] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET); Tests: T25 T26 T27  648 1/1 addr_hit[10] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET); Tests: T25 T26 T27  649 1/1 addr_hit[11] = (reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET); Tests: T25 T26 T27  650 1/1 addr_hit[12] = (reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET); Tests: T25 T26 T27  651 1/1 addr_hit[13] = (reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET); Tests: T25 T26 T27  652 1/1 addr_hit[14] = (reg_addr == GPIO_INTR_CTRL_EN_LVLLOW_OFFSET); Tests: T25 T26 T27  653 1/1 addr_hit[15] = (reg_addr == GPIO_CTRL_EN_INPUT_FILTER_OFFSET); Tests: T25 T26 T27  654 end 655 656 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; Tests: T25 T26 T27  657 658 // Check sub-word write is permitted 659 always_comb begin 660 1/1 wr_err = (reg_we & Tests: T25 T26 T27  661 ((addr_hit[ 0] & (|(GPIO_PERMIT[ 0] & ~reg_be))) | 662 (addr_hit[ 1] & (|(GPIO_PERMIT[ 1] & ~reg_be))) | 663 (addr_hit[ 2] & (|(GPIO_PERMIT[ 2] & ~reg_be))) | 664 (addr_hit[ 3] & (|(GPIO_PERMIT[ 3] & ~reg_be))) | 665 (addr_hit[ 4] & (|(GPIO_PERMIT[ 4] & ~reg_be))) | 666 (addr_hit[ 5] & (|(GPIO_PERMIT[ 5] & ~reg_be))) | 667 (addr_hit[ 6] & (|(GPIO_PERMIT[ 6] & ~reg_be))) | 668 (addr_hit[ 7] & (|(GPIO_PERMIT[ 7] & ~reg_be))) | 669 (addr_hit[ 8] & (|(GPIO_PERMIT[ 8] & ~reg_be))) | 670 (addr_hit[ 9] & (|(GPIO_PERMIT[ 9] & ~reg_be))) | 671 (addr_hit[10] & (|(GPIO_PERMIT[10] & ~reg_be))) | 672 (addr_hit[11] & (|(GPIO_PERMIT[11] & ~reg_be))) | 673 (addr_hit[12] & (|(GPIO_PERMIT[12] & ~reg_be))) | 674 (addr_hit[13] & (|(GPIO_PERMIT[13] & ~reg_be))) | 675 (addr_hit[14] & (|(GPIO_PERMIT[14] & ~reg_be))) | 676 (addr_hit[15] & (|(GPIO_PERMIT[15] & ~reg_be))))); 677 end 678 679 // Generate write-enables 680 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error; Tests: T25 T26 T27  681 682 1/1 assign intr_state_wd = reg_wdata[31:0]; Tests: T25 T26 T27  683 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; Tests: T25 T26 T27  684 685 1/1 assign intr_enable_wd = reg_wdata[31:0]; Tests: T25 T26 T27  686 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error; Tests: T25 T26 T27  687 688 1/1 assign intr_test_wd = reg_wdata[31:0]; Tests: T25 T26 T27  689 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error; Tests: T25 T26 T27  690 691 1/1 assign alert_test_wd = reg_wdata[0]; Tests: T25 T26 T27  692 1/1 assign direct_out_re = addr_hit[5] & reg_re & !reg_error; Tests: T25 T26 T27  693 1/1 assign direct_out_we = addr_hit[5] & reg_we & !reg_error; Tests: T25 T26 T27  694 695 1/1 assign direct_out_wd = reg_wdata[31:0]; Tests: T25 T26 T27  696 1/1 assign masked_out_lower_re = addr_hit[6] & reg_re & !reg_error; Tests: T25 T26 T27  697 1/1 assign masked_out_lower_we = addr_hit[6] & reg_we & !reg_error; Tests: T25 T26 T27  698 699 1/1 assign masked_out_lower_data_wd = reg_wdata[15:0]; Tests: T25 T26 T27  700 701 1/1 assign masked_out_lower_mask_wd = reg_wdata[31:16]; Tests: T25 T26 T27  702 1/1 assign masked_out_upper_re = addr_hit[7] & reg_re & !reg_error; Tests: T25 T26 T27  703 1/1 assign masked_out_upper_we = addr_hit[7] & reg_we & !reg_error; Tests: T25 T26 T27  704 705 1/1 assign masked_out_upper_data_wd = reg_wdata[15:0]; Tests: T25 T26 T27  706 707 1/1 assign masked_out_upper_mask_wd = reg_wdata[31:16]; Tests: T25 T26 T27  708 1/1 assign direct_oe_re = addr_hit[8] & reg_re & !reg_error; Tests: T25 T26 T27  709 1/1 assign direct_oe_we = addr_hit[8] & reg_we & !reg_error; Tests: T25 T26 T27  710 711 1/1 assign direct_oe_wd = reg_wdata[31:0]; Tests: T25 T26 T27  712 1/1 assign masked_oe_lower_re = addr_hit[9] & reg_re & !reg_error; Tests: T25 T26 T27  713 1/1 assign masked_oe_lower_we = addr_hit[9] & reg_we & !reg_error; Tests: T25 T26 T27  714 715 1/1 assign masked_oe_lower_data_wd = reg_wdata[15:0]; Tests: T25 T26 T27  716 717 1/1 assign masked_oe_lower_mask_wd = reg_wdata[31:16]; Tests: T25 T26 T27  718 1/1 assign masked_oe_upper_re = addr_hit[10] & reg_re & !reg_error; Tests: T25 T26 T27  719 1/1 assign masked_oe_upper_we = addr_hit[10] & reg_we & !reg_error; Tests: T25 T26 T27  720 721 1/1 assign masked_oe_upper_data_wd = reg_wdata[15:0]; Tests: T25 T26 T27  722 723 1/1 assign masked_oe_upper_mask_wd = reg_wdata[31:16]; Tests: T25 T26 T27  724 1/1 assign intr_ctrl_en_rising_we = addr_hit[11] & reg_we & !reg_error; Tests: T25 T26 T27  725 726 1/1 assign intr_ctrl_en_rising_wd = reg_wdata[31:0]; Tests: T25 T26 T27  727 1/1 assign intr_ctrl_en_falling_we = addr_hit[12] & reg_we & !reg_error; Tests: T25 T26 T27  728 729 1/1 assign intr_ctrl_en_falling_wd = reg_wdata[31:0]; Tests: T25 T26 T27  730 1/1 assign intr_ctrl_en_lvlhigh_we = addr_hit[13] & reg_we & !reg_error; Tests: T25 T26 T27  731 732 1/1 assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0]; Tests: T25 T26 T27  733 1/1 assign intr_ctrl_en_lvllow_we = addr_hit[14] & reg_we & !reg_error; Tests: T25 T26 T27  734 735 1/1 assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0]; Tests: T25 T26 T27  736 1/1 assign ctrl_en_input_filter_we = addr_hit[15] & reg_we & !reg_error; Tests: T25 T26 T27  737 738 1/1 assign ctrl_en_input_filter_wd = reg_wdata[31:0]; Tests: T25 T26 T27  739 740 // Assign write-enables to checker logic vector. 741 always_comb begin 742 1/1 reg_we_check = '0; Tests: T25 T26 T27  743 1/1 reg_we_check[0] = intr_state_we; Tests: T25 T26 T27  744 1/1 reg_we_check[1] = intr_enable_we; Tests: T25 T26 T27  745 1/1 reg_we_check[2] = intr_test_we; Tests: T25 T26 T27  746 1/1 reg_we_check[3] = alert_test_we; Tests: T25 T26 T27  747 1/1 reg_we_check[4] = 1'b0; Tests: T25 T26 T27  748 1/1 reg_we_check[5] = direct_out_we; Tests: T25 T26 T27  749 1/1 reg_we_check[6] = masked_out_lower_we; Tests: T25 T26 T27  750 1/1 reg_we_check[7] = masked_out_upper_we; Tests: T25 T26 T27  751 1/1 reg_we_check[8] = direct_oe_we; Tests: T25 T26 T27  752 1/1 reg_we_check[9] = masked_oe_lower_we; Tests: T25 T26 T27  753 1/1 reg_we_check[10] = masked_oe_upper_we; Tests: T25 T26 T27  754 1/1 reg_we_check[11] = intr_ctrl_en_rising_we; Tests: T25 T26 T27  755 1/1 reg_we_check[12] = intr_ctrl_en_falling_we; Tests: T25 T26 T27  756 1/1 reg_we_check[13] = intr_ctrl_en_lvlhigh_we; Tests: T25 T26 T27  757 1/1 reg_we_check[14] = intr_ctrl_en_lvllow_we; Tests: T25 T26 T27  758 1/1 reg_we_check[15] = ctrl_en_input_filter_we; Tests: T25 T26 T27  759 end 760 761 // Read data return 762 always_comb begin 763 1/1 reg_rdata_next = '0; Tests: T25 T26 T27  764 1/1 unique case (1'b1) Tests: T25 T26 T27  765 addr_hit[0]: begin 766 1/1 reg_rdata_next[31:0] = intr_state_qs; Tests: T25 T26 T27  767 end 768 769 addr_hit[1]: begin 770 1/1 reg_rdata_next[31:0] = intr_enable_qs; Tests: T25 T26 T27  771 end 772 773 addr_hit[2]: begin 774 1/1 reg_rdata_next[31:0] = '0; Tests: T25 T26 T27  775 end 776 777 addr_hit[3]: begin 778 1/1 reg_rdata_next[0] = '0; Tests: T25 T26 T27  779 end 780 781 addr_hit[4]: begin 782 1/1 reg_rdata_next[31:0] = data_in_qs; Tests: T25 T26 T27  783 end 784 785 addr_hit[5]: begin 786 1/1 reg_rdata_next[31:0] = direct_out_qs; Tests: T25 T26 T27  787 end 788 789 addr_hit[6]: begin 790 1/1 reg_rdata_next[15:0] = masked_out_lower_data_qs; Tests: T25 T26 T27  791 1/1 reg_rdata_next[31:16] = '0; Tests: T25 T26 T27  792 end 793 794 addr_hit[7]: begin 795 1/1 reg_rdata_next[15:0] = masked_out_upper_data_qs; Tests: T25 T26 T27  796 1/1 reg_rdata_next[31:16] = '0; Tests: T25 T26 T27  797 end 798 799 addr_hit[8]: begin 800 1/1 reg_rdata_next[31:0] = direct_oe_qs; Tests: T25 T26 T27  801 end 802 803 addr_hit[9]: begin 804 1/1 reg_rdata_next[15:0] = masked_oe_lower_data_qs; Tests: T25 T26 T27  805 1/1 reg_rdata_next[31:16] = masked_oe_lower_mask_qs; Tests: T25 T26 T27  806 end 807 808 addr_hit[10]: begin 809 1/1 reg_rdata_next[15:0] = masked_oe_upper_data_qs; Tests: T25 T26 T27  810 1/1 reg_rdata_next[31:16] = masked_oe_upper_mask_qs; Tests: T25 T26 T27  811 end 812 813 addr_hit[11]: begin 814 1/1 reg_rdata_next[31:0] = intr_ctrl_en_rising_qs; Tests: T25 T26 T27  815 end 816 817 addr_hit[12]: begin 818 1/1 reg_rdata_next[31:0] = intr_ctrl_en_falling_qs; Tests: T25 T26 T27  819 end 820 821 addr_hit[13]: begin 822 1/1 reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs; Tests: T25 T26 T27  823 end 824 825 addr_hit[14]: begin 826 1/1 reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs; Tests: T25 T26 T27  827 end 828 829 addr_hit[15]: begin 830 1/1 reg_rdata_next[31:0] = ctrl_en_input_filter_qs; Tests: T25 T26 T27  831 end 832 833 default: begin 834 reg_rdata_next = '1; 835 end 836 endcase 837 end 838 839 // shadow busy 840 logic shadow_busy; 841 assign shadow_busy = 1'b0; 842 843 // register busy 844 unreachable assign reg_busy = shadow_busy; 845 846 // Unused signal tieoff 847 848 // wdata / byte enable are not always fully used 849 // add a blanket unused statement to handle lint waivers 850 logic unused_wdata; 851 logic unused_be; 852 1/1 assign unused_wdata = ^reg_wdata; Tests: T25 T26 T27  853 1/1 assign unused_be = ^reg_be; Tests: T25 T26 T27 

Cond Coverage for Module : gpio_reg_top
TotalCoveredPercent
Conditions20320199.01
Logical20320199.01
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT25,T26,T27
10Not Covered
11CoveredT25,T26,T27

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT25,T26,T27
01CoveredT13,T43,T44
10CoveredT39,T42,T40

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT25,T26,T27
001CoveredT13,T43,T44
010CoveredT39,T42,T40
100CoveredT13,T43,T44

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT25,T26,T27
001CoveredT39,T42,T40
010CoveredT36,T37,T38
100Not Covered

 LINE       638
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_STATE_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       639
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT28,T30,T32

 LINE       640
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_TEST_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T33,T1

 LINE       641
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_ALERT_TEST_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T33,T11

 LINE       642
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DATA_IN_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       643
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OUT_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       644
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_LOWER_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T29

 LINE       645
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_UPPER_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T29

 LINE       646
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OE_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       647
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_LOWER_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T29

 LINE       648
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_UPPER_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T29

 LINE       649
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_RISING_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT28,T30,T32

 LINE       650
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_FALLING_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT28,T30,T32

 LINE       651
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT28,T30,T32

 LINE       652
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLLOW_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT28,T30,T32

 LINE       653
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_CTRL_EN_INPUT_FILTER_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT30,T32,T33

 LINE       656
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT25,T26,T27
1CoveredT25,T26,T27

 LINE       656
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT25,T26,T27
01CoveredT25,T26,T27
10CoveredT25,T26,T27

 LINE       660
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT36,T37,T38

 LINE       660
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
0000000000000000CoveredT25,T26,T27
0000000000000001CoveredT30,T33,T1
0000000000000010CoveredT30,T33,T1
0000000000000100CoveredT30,T33,T1
0000000000001000CoveredT30,T33,T1
0000000000010000CoveredT30,T33,T1
0000000000100000CoveredT25,T30,T33
0000000001000000CoveredT25,T30,T33
0000000010000000CoveredT30,T33,T1
0000000100000000CoveredT25,T30,T33
0000001000000000CoveredT25,T30,T33
0000010000000000CoveredT25,T30,T33
0000100000000000CoveredT25,T26,T27
0001000000000000CoveredT30,T33,T13
0010000000000000CoveredT30,T33,T1
0100000000000000CoveredT30,T33,T1
1000000000000000CoveredT28,T29,T30

 LINE       660
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT28,T29,T30

 LINE       660
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT28,T30,T32
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT30,T1,T13
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT30,T33,T11
11CoveredT30,T33,T13

 LINE       660
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T28,T29
10CoveredT25,T26,T27
11CoveredT25,T26,T27

 LINE       660
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT25,T30,T33

 LINE       660
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T29
11CoveredT25,T30,T33

 LINE       660
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T29
11CoveredT25,T30,T33

 LINE       660
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T29
11CoveredT25,T30,T33

 LINE       660
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T29
11CoveredT25,T30,T33

 LINE       660
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT28,T30,T32
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT28,T30,T32
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT28,T30,T32
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT28,T30,T32
11CoveredT30,T33,T1

 LINE       660
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT30,T32,T1
11CoveredT30,T33,T1

 LINE       680
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T27
110CoveredT36,T37,T38
111CoveredT28,T30,T33

 LINE       683
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT28,T30,T32
110CoveredT36,T37,T38
111CoveredT28,T30,T32

 LINE       686
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT30,T33,T1
110CoveredT36,T37,T38
111CoveredT30,T1,T19

 LINE       689
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT30,T33,T11
110CoveredT36,T37,T38
111CoveredT11,T17,T45

 LINE       692
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T27
110CoveredT46,T47,T48
111CoveredT25,T30,T1

 LINE       693
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T27
110CoveredT36,T37,T38
111CoveredT25,T26,T27

 LINE       696
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT39,T41,T49
111CoveredT25,T1,T14

 LINE       697
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT36,T37,T38
111CoveredT25,T26,T29

 LINE       702
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT41,T50,T46
111CoveredT25,T1,T14

 LINE       703
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT36,T37,T38
111CoveredT25,T26,T29

 LINE       708
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T27
110CoveredT51,T52,T53
111CoveredT25,T30,T1

 LINE       709
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T27
110CoveredT36,T37,T38
111CoveredT25,T26,T27

 LINE       712
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT41,T51,T54
111CoveredT25,T30,T1

 LINE       713
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT36,T37,T38
111CoveredT25,T26,T29

 LINE       718
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT41,T51,T53
111CoveredT25,T1,T14

 LINE       719
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT25,T26,T29
110CoveredT36,T37,T38
111CoveredT25,T26,T29

 LINE       724
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT28,T30,T32
110CoveredT36,T37,T38
111CoveredT28,T30,T32

 LINE       727
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT28,T30,T32
110CoveredT36,T37,T38
111CoveredT28,T30,T32

 LINE       730
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT28,T30,T32
110CoveredT36,T37,T38
111CoveredT28,T30,T32

 LINE       733
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT28,T30,T32
110CoveredT36,T37,T38
111CoveredT28,T30,T32

 LINE       736
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT25,T26,T27
101CoveredT30,T32,T33
110CoveredT36,T37,T38
111CoveredT30,T32,T12

Branch Coverage for Module : gpio_reg_top
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 656 2 2 100.00
IF 68 3 3 100.00
CASE 764 17 17 100.00


656 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T25,T26,T27
0 Covered T25,T26,T27


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T25,T26,T27
0 1 Covered T13,T43,T44
0 0 Covered T25,T26,T27


764 unique case (1'b1) -1- 765 addr_hit[0]: begin 766 reg_rdata_next[31:0] = intr_state_qs; ==> 767 end 768 769 addr_hit[1]: begin 770 reg_rdata_next[31:0] = intr_enable_qs; ==> 771 end 772 773 addr_hit[2]: begin 774 reg_rdata_next[31:0] = '0; ==> 775 end 776 777 addr_hit[3]: begin 778 reg_rdata_next[0] = '0; ==> 779 end 780 781 addr_hit[4]: begin 782 reg_rdata_next[31:0] = data_in_qs; ==> 783 end 784 785 addr_hit[5]: begin 786 reg_rdata_next[31:0] = direct_out_qs; ==> 787 end 788 789 addr_hit[6]: begin 790 reg_rdata_next[15:0] = masked_out_lower_data_qs; ==> 791 reg_rdata_next[31:16] = '0; 792 end 793 794 addr_hit[7]: begin 795 reg_rdata_next[15:0] = masked_out_upper_data_qs; ==> 796 reg_rdata_next[31:16] = '0; 797 end 798 799 addr_hit[8]: begin 800 reg_rdata_next[31:0] = direct_oe_qs; ==> 801 end 802 803 addr_hit[9]: begin 804 reg_rdata_next[15:0] = masked_oe_lower_data_qs; ==> 805 reg_rdata_next[31:16] = masked_oe_lower_mask_qs; 806 end 807 808 addr_hit[10]: begin 809 reg_rdata_next[15:0] = masked_oe_upper_data_qs; ==> 810 reg_rdata_next[31:16] = masked_oe_upper_mask_qs; 811 end 812 813 addr_hit[11]: begin 814 reg_rdata_next[31:0] = intr_ctrl_en_rising_qs; ==> 815 end 816 817 addr_hit[12]: begin 818 reg_rdata_next[31:0] = intr_ctrl_en_falling_qs; ==> 819 end 820 821 addr_hit[13]: begin 822 reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs; ==> 823 end 824 825 addr_hit[14]: begin 826 reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs; ==> 827 end 828 829 addr_hit[15]: begin 830 reg_rdata_next[31:0] = ctrl_en_input_filter_qs; ==> 831 end 832 833 default: begin 834 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T25,T26,T27
addr_hit[1] Covered T25,T26,T27
addr_hit[2] Covered T25,T26,T27
addr_hit[3] Covered T25,T26,T27
addr_hit[4] Covered T25,T26,T27
addr_hit[5] Covered T25,T26,T27
addr_hit[6] Covered T25,T26,T27
addr_hit[7] Covered T25,T26,T27
addr_hit[8] Covered T25,T26,T27
addr_hit[9] Covered T25,T26,T27
addr_hit[10] Covered T25,T26,T27
addr_hit[11] Covered T25,T26,T27
addr_hit[12] Covered T25,T26,T27
addr_hit[13] Covered T25,T26,T27
addr_hit[14] Covered T25,T26,T27
addr_hit[15] Covered T25,T26,T27
default Covered T25,T26,T27


Assert Coverage for Module : gpio_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 55868486 6348553 0 0
reAfterRv 55868486 6348553 0 0
rePulse 55868486 2899613 0 0
wePulse 55868486 3448940 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 55868486 6348553 0 0
T1 13183 1096 0 0
T25 1248 47 0 0
T26 2219 117 0 0
T27 3281 259 0 0
T28 2584 309 0 0
T29 2956 414 0 0
T30 4709 196 0 0
T31 4678 499 0 0
T32 2274 441 0 0
T33 6512 457 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 55868486 6348553 0 0
T1 13183 1096 0 0
T25 1248 47 0 0
T26 2219 117 0 0
T27 3281 259 0 0
T28 2584 309 0 0
T29 2956 414 0 0
T30 4709 196 0 0
T31 4678 499 0 0
T32 2274 441 0 0
T33 6512 457 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 55868486 2899613 0 0
T1 13183 697 0 0
T25 1248 22 0 0
T26 2219 19 0 0
T27 3281 173 0 0
T28 2584 136 0 0
T29 2956 73 0 0
T30 4709 14 0 0
T31 4678 171 0 0
T32 2274 324 0 0
T33 6512 179 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 55868486 3448940 0 0
T1 13183 399 0 0
T25 1248 25 0 0
T26 2219 98 0 0
T27 3281 86 0 0
T28 2584 173 0 0
T29 2956 341 0 0
T30 4709 182 0 0
T31 4678 328 0 0
T32 2274 117 0 0
T33 6512 278 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%