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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 939
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T756 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_csr_rw.1092475099 Feb 09 06:34:36 AM UTC 25 Feb 09 06:34:38 AM UTC 25 14123818 ps
T757 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1934494899 Feb 09 06:34:36 AM UTC 25 Feb 09 06:34:38 AM UTC 25 62043486 ps
T758 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_tl_intg_err.870059970 Feb 09 06:34:36 AM UTC 25 Feb 09 06:34:39 AM UTC 25 58241548 ps
T759 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2190064790 Feb 09 06:34:36 AM UTC 25 Feb 09 06:34:39 AM UTC 25 68503392 ps
T760 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_csr_rw.1783759785 Feb 09 06:34:37 AM UTC 25 Feb 09 06:34:40 AM UTC 25 15549316 ps
T761 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_tl_errors.1945729633 Feb 09 06:34:35 AM UTC 25 Feb 09 06:34:40 AM UTC 25 689074503 ps
T762 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_intr_test.1432730499 Feb 09 06:34:37 AM UTC 25 Feb 09 06:34:40 AM UTC 25 12294968 ps
T763 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3247939318 Feb 09 06:34:37 AM UTC 25 Feb 09 06:34:40 AM UTC 25 63354009 ps
T764 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_tl_errors.3499652122 Feb 09 06:34:37 AM UTC 25 Feb 09 06:34:42 AM UTC 25 92216469 ps
T765 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_intr_test.3648086905 Feb 09 06:34:40 AM UTC 25 Feb 09 06:34:42 AM UTC 25 39337288 ps
T766 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_csr_rw.4061729519 Feb 09 06:34:40 AM UTC 25 Feb 09 06:34:42 AM UTC 25 17428819 ps
T767 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1220337732 Feb 09 06:34:40 AM UTC 25 Feb 09 06:34:42 AM UTC 25 76359997 ps
T768 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.65944931 Feb 09 06:34:40 AM UTC 25 Feb 09 06:34:42 AM UTC 25 21125470 ps
T769 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_tl_intg_err.520623525 Feb 09 06:34:40 AM UTC 25 Feb 09 06:34:43 AM UTC 25 148685272 ps
T770 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_tl_errors.2351177255 Feb 09 06:34:39 AM UTC 25 Feb 09 06:34:43 AM UTC 25 41962951 ps
T771 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_intr_test.893217379 Feb 09 06:34:41 AM UTC 25 Feb 09 06:34:43 AM UTC 25 39565591 ps
T772 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_csr_rw.3549043804 Feb 09 06:34:41 AM UTC 25 Feb 09 06:34:43 AM UTC 25 51455849 ps
T773 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1429264704 Feb 09 06:34:41 AM UTC 25 Feb 09 06:34:44 AM UTC 25 42884579 ps
T774 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1729232541 Feb 09 06:34:41 AM UTC 25 Feb 09 06:34:44 AM UTC 25 47454820 ps
T775 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_tl_errors.3967646630 Feb 09 06:34:42 AM UTC 25 Feb 09 06:34:45 AM UTC 25 172617779 ps
T73 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_tl_intg_err.478049804 Feb 09 06:34:42 AM UTC 25 Feb 09 06:34:45 AM UTC 25 206517328 ps
T110 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_csr_rw.4083554706 Feb 09 06:34:43 AM UTC 25 Feb 09 06:34:45 AM UTC 25 67217129 ps
T776 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_intr_test.3990913863 Feb 09 06:34:43 AM UTC 25 Feb 09 06:34:45 AM UTC 25 13127497 ps
T777 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_tl_errors.1742132846 Feb 09 06:34:41 AM UTC 25 Feb 09 06:34:45 AM UTC 25 41710518 ps
T778 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1584842984 Feb 09 06:34:43 AM UTC 25 Feb 09 06:34:46 AM UTC 25 23485975 ps
T779 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2835420036 Feb 09 06:34:43 AM UTC 25 Feb 09 06:34:46 AM UTC 25 30751772 ps
T780 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_tl_intg_err.2521093423 Feb 09 06:34:43 AM UTC 25 Feb 09 06:34:46 AM UTC 25 72047722 ps
T781 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_intr_test.944592559 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:47 AM UTC 25 22191794 ps
T111 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_csr_rw.3386994756 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:48 AM UTC 25 53592602 ps
T782 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2830237611 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:48 AM UTC 25 54301787 ps
T783 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3949478033 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:48 AM UTC 25 34881090 ps
T784 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_tl_intg_err.503725566 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:48 AM UTC 25 366556163 ps
T785 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_csr_rw.2872686099 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:49 AM UTC 25 13575102 ps
T786 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_tl_errors.2358515965 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:49 AM UTC 25 90722509 ps
T787 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_intr_test.3816243604 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:49 AM UTC 25 35323381 ps
T788 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1499798752 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:49 AM UTC 25 41034015 ps
T112 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_csr_rw.1494383858 Feb 09 06:34:47 AM UTC 25 Feb 09 06:34:49 AM UTC 25 48051215 ps
T789 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_intr_test.2064268466 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:49 AM UTC 25 14490045 ps
T790 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_tl_errors.571488350 Feb 09 06:34:45 AM UTC 25 Feb 09 06:34:49 AM UTC 25 107243149 ps
T791 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3647277526 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:49 AM UTC 25 58986508 ps
T792 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_tl_intg_err.3655333715 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:50 AM UTC 25 53756745 ps
T793 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_same_csr_outstanding.438743871 Feb 09 06:34:48 AM UTC 25 Feb 09 06:34:51 AM UTC 25 24259939 ps
T794 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_tl_errors.642347157 Feb 09 06:34:46 AM UTC 25 Feb 09 06:34:51 AM UTC 25 542672849 ps
T795 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_intr_test.446257935 Feb 09 06:34:49 AM UTC 25 Feb 09 06:34:51 AM UTC 25 29370295 ps
T796 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2260658541 Feb 09 06:34:49 AM UTC 25 Feb 09 06:34:51 AM UTC 25 14445176 ps
T797 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_csr_rw.1420143361 Feb 09 06:34:49 AM UTC 25 Feb 09 06:34:51 AM UTC 25 61422103 ps
T798 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_tl_intg_err.3227111686 Feb 09 06:34:49 AM UTC 25 Feb 09 06:34:52 AM UTC 25 157509904 ps
T799 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_tl_errors.2422663451 Feb 09 06:34:49 AM UTC 25 Feb 09 06:34:52 AM UTC 25 92986996 ps
T800 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_same_csr_outstanding.6016848 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:52 AM UTC 25 74866635 ps
T801 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_intr_test.1343779684 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:52 AM UTC 25 103017622 ps
T802 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1723134559 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:52 AM UTC 25 20981141 ps
T113 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_csr_rw.3058200811 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:53 AM UTC 25 20985452 ps
T803 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.813065089 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:53 AM UTC 25 29797663 ps
T804 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1110678452 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:53 AM UTC 25 33028660 ps
T805 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_tl_intg_err.1729675775 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:53 AM UTC 25 79937291 ps
T806 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_tl_errors.3593290193 Feb 09 06:34:50 AM UTC 25 Feb 09 06:34:54 AM UTC 25 186030302 ps
T807 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_tl_intg_err.3234948610 Feb 09 06:34:51 AM UTC 25 Feb 09 06:34:54 AM UTC 25 116970232 ps
T808 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/21.gpio_intr_test.2132821009 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:54 AM UTC 25 22924864 ps
T809 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/20.gpio_intr_test.1702826808 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:55 AM UTC 25 22802565 ps
T810 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/23.gpio_intr_test.3599138258 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:55 AM UTC 25 178453444 ps
T811 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/25.gpio_intr_test.3051251933 Feb 09 06:34:53 AM UTC 25 Feb 09 06:34:55 AM UTC 25 72800402 ps
T812 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/22.gpio_intr_test.3175685340 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:55 AM UTC 25 12788390 ps
T813 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/24.gpio_intr_test.81852244 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:55 AM UTC 25 15388691 ps
T814 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_intr_test.1075653404 Feb 09 06:34:52 AM UTC 25 Feb 09 06:34:55 AM UTC 25 16714928 ps
T815 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_tl_errors.969313083 Feb 09 06:34:51 AM UTC 25 Feb 09 06:34:55 AM UTC 25 120467135 ps
T816 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/26.gpio_intr_test.112895292 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 43998972 ps
T817 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/28.gpio_intr_test.1885066958 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 33135532 ps
T818 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/27.gpio_intr_test.3553139028 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 20672549 ps
T819 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/29.gpio_intr_test.995024217 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 64575995 ps
T820 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/30.gpio_intr_test.1602224509 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 52357476 ps
T821 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/32.gpio_intr_test.521866289 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 58270561 ps
T822 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/31.gpio_intr_test.761019190 Feb 09 06:34:54 AM UTC 25 Feb 09 06:34:56 AM UTC 25 24773998 ps
T823 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/35.gpio_intr_test.1712239767 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 14727809 ps
T824 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/38.gpio_intr_test.1271924803 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 42523905 ps
T825 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/34.gpio_intr_test.1887608898 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 33039046 ps
T826 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/33.gpio_intr_test.2933647127 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 29701155 ps
T827 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/39.gpio_intr_test.691867264 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 50660617 ps
T828 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/37.gpio_intr_test.2350682596 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 11876570 ps
T829 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/36.gpio_intr_test.349064584 Feb 09 06:34:55 AM UTC 25 Feb 09 06:34:57 AM UTC 25 17782912 ps
T830 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/41.gpio_intr_test.622615896 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 53847818 ps
T831 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/43.gpio_intr_test.4082065219 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 40758658 ps
T832 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/40.gpio_intr_test.567752475 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 16304517 ps
T833 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/42.gpio_intr_test.671616144 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 15629536 ps
T834 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/44.gpio_intr_test.1003637591 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 62076233 ps
T835 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/45.gpio_intr_test.4064866100 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 14170989 ps
T836 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/46.gpio_intr_test.2238486984 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:58 AM UTC 25 18562351 ps
T837 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/47.gpio_intr_test.724807939 Feb 09 06:34:56 AM UTC 25 Feb 09 06:34:59 AM UTC 25 45268619 ps
T838 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/49.gpio_intr_test.2870759004 Feb 09 06:34:58 AM UTC 25 Feb 09 06:34:59 AM UTC 25 14468857 ps
T839 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/48.gpio_intr_test.706742940 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 22881073 ps
T840 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1356944071 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 201283502 ps
T841 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837371075 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 27463610 ps
T842 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.828020124 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 49418443 ps
T843 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3049843755 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 120953807 ps
T844 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532510010 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:00 AM UTC 25 33864361 ps
T845 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.951797400 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:01 AM UTC 25 53312028 ps
T846 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876697382 Feb 09 06:34:58 AM UTC 25 Feb 09 06:35:01 AM UTC 25 177116060 ps
T847 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730125161 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:01 AM UTC 25 148980808 ps
T848 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1153046971 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:01 AM UTC 25 104993870 ps
T849 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258640683 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 57635388 ps
T850 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515060864 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 274073651 ps
T851 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.272923122 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 77179185 ps
T852 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1951256573 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 212494482 ps
T853 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.138846714 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 288357581 ps
T854 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3834072711 Feb 09 06:34:59 AM UTC 25 Feb 09 06:35:02 AM UTC 25 625406994 ps
T855 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3727940976 Feb 09 06:35:00 AM UTC 25 Feb 09 06:35:02 AM UTC 25 41165704 ps
T856 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.5369939 Feb 09 06:35:00 AM UTC 25 Feb 09 06:35:02 AM UTC 25 30576724 ps
T857 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3660593038 Feb 09 06:35:00 AM UTC 25 Feb 09 06:35:03 AM UTC 25 115080285 ps
T858 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937088859 Feb 09 06:35:00 AM UTC 25 Feb 09 06:35:03 AM UTC 25 57450401 ps
T859 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045362688 Feb 09 06:35:01 AM UTC 25 Feb 09 06:35:04 AM UTC 25 189801448 ps
T860 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.533495441 Feb 09 06:35:01 AM UTC 25 Feb 09 06:35:04 AM UTC 25 150676024 ps
T861 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1002624591 Feb 09 06:35:01 AM UTC 25 Feb 09 06:35:04 AM UTC 25 82497567 ps
T862 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1709435035 Feb 09 06:35:01 AM UTC 25 Feb 09 06:35:04 AM UTC 25 74951827 ps
T863 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768713881 Feb 09 06:35:02 AM UTC 25 Feb 09 06:35:04 AM UTC 25 36571122 ps
T864 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539963272 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:05 AM UTC 25 31173903 ps
T865 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.665116249 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:05 AM UTC 25 60819705 ps
T866 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2011923483 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:05 AM UTC 25 42226792 ps
T867 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3893241766 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:05 AM UTC 25 287005479 ps
T868 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2362002611 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 130208060 ps
T869 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558388466 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 525295050 ps
T870 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4269916705 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 411796598 ps
T871 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2444436276 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 169817103 ps
T872 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3437162999 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 62360471 ps
T873 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509150314 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 160920239 ps
T874 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594797506 Feb 09 06:35:03 AM UTC 25 Feb 09 06:35:06 AM UTC 25 73269337 ps
T875 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1269058692 Feb 09 06:35:04 AM UTC 25 Feb 09 06:35:06 AM UTC 25 113880904 ps
T876 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3646846923 Feb 09 06:35:04 AM UTC 25 Feb 09 06:35:06 AM UTC 25 110692123 ps
T877 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908943533 Feb 09 06:35:04 AM UTC 25 Feb 09 06:35:06 AM UTC 25 59223188 ps
T878 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2003711797 Feb 09 06:35:04 AM UTC 25 Feb 09 06:35:07 AM UTC 25 36281466 ps
T879 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471878642 Feb 09 06:35:05 AM UTC 25 Feb 09 06:35:08 AM UTC 25 99483073 ps
T880 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2661116069 Feb 09 06:35:05 AM UTC 25 Feb 09 06:35:08 AM UTC 25 29915356 ps
T881 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4090057472 Feb 09 06:35:05 AM UTC 25 Feb 09 06:35:08 AM UTC 25 37945378 ps
T882 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2012257799 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:09 AM UTC 25 40085939 ps
T883 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913043093 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:09 AM UTC 25 134581920 ps
T884 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3645495194 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:09 AM UTC 25 58218542 ps
T885 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3238600109 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:09 AM UTC 25 52749009 ps
T886 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3903002719 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:09 AM UTC 25 89387152 ps
T887 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114880556 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 235021430 ps
T888 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.597441654 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 59839122 ps
T889 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2434086710 Feb 09 06:35:08 AM UTC 25 Feb 09 06:35:11 AM UTC 25 305297628 ps
T890 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3133337938 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 62901729 ps
T891 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.207753579 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 173784134 ps
T892 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2649889188 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 655572959 ps
T893 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.202873867 Feb 09 06:35:07 AM UTC 25 Feb 09 06:35:10 AM UTC 25 56509568 ps
T894 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3117850513 Feb 09 06:35:08 AM UTC 25 Feb 09 06:35:10 AM UTC 25 32427829 ps
T895 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1599537920 Feb 09 06:35:08 AM UTC 25 Feb 09 06:35:10 AM UTC 25 36299279 ps
T896 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486305941 Feb 09 06:35:08 AM UTC 25 Feb 09 06:35:11 AM UTC 25 271889439 ps
T897 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.399556348 Feb 09 06:35:09 AM UTC 25 Feb 09 06:35:12 AM UTC 25 35298697 ps
T898 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587288962 Feb 09 06:35:09 AM UTC 25 Feb 09 06:35:12 AM UTC 25 110346057 ps
T899 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3586575650 Feb 09 06:35:09 AM UTC 25 Feb 09 06:35:12 AM UTC 25 90988880 ps
T900 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2672197110 Feb 09 06:35:10 AM UTC 25 Feb 09 06:35:13 AM UTC 25 29131884 ps
T901 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2701323833 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:13 AM UTC 25 228361407 ps
T902 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1377233580 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:13 AM UTC 25 135147868 ps
T903 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3241050508 Feb 09 06:35:10 AM UTC 25 Feb 09 06:35:13 AM UTC 25 59110487 ps
T904 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2654478932 Feb 09 06:35:10 AM UTC 25 Feb 09 06:35:13 AM UTC 25 62361408 ps
T905 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408093791 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:13 AM UTC 25 35320160 ps
T906 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2287307455 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:13 AM UTC 25 70758388 ps
T907 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1259812838 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:13 AM UTC 25 138469882 ps
T908 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2694915102 Feb 09 06:35:10 AM UTC 25 Feb 09 06:35:14 AM UTC 25 204963462 ps
T909 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2353166130 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:14 AM UTC 25 284137122 ps
T910 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2893727713 Feb 09 06:35:11 AM UTC 25 Feb 09 06:35:14 AM UTC 25 688163615 ps
T911 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.815697742 Feb 09 06:35:12 AM UTC 25 Feb 09 06:35:14 AM UTC 25 83790085 ps
T912 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3316528588 Feb 09 06:35:12 AM UTC 25 Feb 09 06:35:14 AM UTC 25 206022666 ps
T913 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1153997598 Feb 09 06:35:12 AM UTC 25 Feb 09 06:35:15 AM UTC 25 37177900 ps
T914 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159167034 Feb 09 06:35:12 AM UTC 25 Feb 09 06:35:15 AM UTC 25 47673204 ps
T915 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2051198264 Feb 09 06:35:12 AM UTC 25 Feb 09 06:35:15 AM UTC 25 382199634 ps
T916 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1388216306 Feb 09 06:35:13 AM UTC 25 Feb 09 06:35:16 AM UTC 25 67281966 ps
T917 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916114619 Feb 09 06:35:13 AM UTC 25 Feb 09 06:35:16 AM UTC 25 137054073 ps
T918 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1075733489 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 20469833 ps
T919 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4092281507 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 63091435 ps
T920 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4091646085 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 36989531 ps
T921 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3237075895 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 24700311 ps
T922 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912609424 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 164261571 ps
T923 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3921422955 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 137137399 ps
T924 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3174810673 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 100465601 ps
T925 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4035975852 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 48515917 ps
T926 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1655007264 Feb 09 06:35:14 AM UTC 25 Feb 09 06:35:17 AM UTC 25 41419580 ps
T927 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4270802278 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:18 AM UTC 25 46496798 ps
T928 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3704757506 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:18 AM UTC 25 102793615 ps
T929 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2565308348 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:18 AM UTC 25 79596287 ps
T930 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1502149115 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:18 AM UTC 25 22475507 ps
T931 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777577393 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:18 AM UTC 25 107672372 ps
T932 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279270783 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:19 AM UTC 25 307021783 ps
T933 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.544716642 Feb 09 06:35:16 AM UTC 25 Feb 09 06:35:19 AM UTC 25 78603098 ps
T934 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.970374396 Feb 09 06:35:17 AM UTC 25 Feb 09 06:35:20 AM UTC 25 295217538 ps
T935 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.300299955 Feb 09 06:35:17 AM UTC 25 Feb 09 06:35:20 AM UTC 25 346669892 ps
T936 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3996646752 Feb 09 06:35:17 AM UTC 25 Feb 09 06:35:20 AM UTC 25 49145745 ps
T937 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.903043040 Feb 09 06:35:18 AM UTC 25 Feb 09 06:35:20 AM UTC 25 161269744 ps
T938 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470642025 Feb 09 06:35:18 AM UTC 25 Feb 09 06:35:21 AM UTC 25 57492047 ps
T939 /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2457149654 Feb 09 06:35:18 AM UTC 25 Feb 09 06:35:21 AM UTC 25 103118775 ps

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_full_random.3965033277
Short name T46
Test name
Test status
Simulation time 166327509 ps
CPU time 0.94 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:26 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965033277 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3965033277
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_intr_rand_pgm.1610431107
Short name T79
Test name
Test status
Simulation time 89746350 ps
CPU time 1.29 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610431107 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1610431107
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2558455934
Short name T36
Test name
Test status
Simulation time 93452693 ps
CPU time 3.33 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 200724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558455934 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2558455934
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_stress_all_with_rand_reset.2163753519
Short name T55
Test name
Test status
Simulation time 206524403065 ps
CPU time 569.61 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:38:04 AM UTC 25
Peak memory 206692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2163753519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress
_all_with_rand_reset.2163753519
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_sec_cm.3248820030
Short name T62
Test name
Test status
Simulation time 80241626 ps
CPU time 1 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 235388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248820030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3248820030
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_csr_rw.2450408997
Short name T100
Test name
Test status
Simulation time 11543258 ps
CPU time 0.88 seconds
Started Feb 09 06:34:13 AM UTC 25
Finished Feb 09 06:34:15 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450408997 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_rw.2450408997
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_random_long_reg_writes_reg_reads.214172142
Short name T1
Test name
Test status
Simulation time 1339771083 ps
CPU time 4.34 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214172142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_long_reg_writes_reg_reads.214172142
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_tl_intg_err.2723741378
Short name T61
Test name
Test status
Simulation time 190686370 ps
CPU time 2.03 seconds
Started Feb 09 06:34:23 AM UTC 25
Finished Feb 09 06:34:26 AM UTC 25
Peak memory 206608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723741378 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_intg_err.2723741378
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_dout_din_regs_random_rw.4133361360
Short name T44
Test name
Test status
Simulation time 82215022 ps
CPU time 0.85 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:26 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133361360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4133361360
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_alert_test.1470756204
Short name T49
Test name
Test status
Simulation time 152940185 ps
CPU time 0.63 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470756204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1470756204
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_csr_rw.2904734337
Short name T96
Test name
Test status
Simulation time 33711693 ps
CPU time 0.89 seconds
Started Feb 09 06:34:03 AM UTC 25
Finished Feb 09 06:34:05 AM UTC 25
Peak memory 202452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904734337 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_rw.2904734337
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1265636809
Short name T114
Test name
Test status
Simulation time 26852814 ps
CPU time 1.16 seconds
Started Feb 09 06:34:03 AM UTC 25
Finished Feb 09 06:34:05 AM UTC 25
Peak memory 202092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265636809 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_same_csr_outstanding.1265636809
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_tl_intg_err.1023813023
Short name T72
Test name
Test status
Simulation time 119632133 ps
CPU time 1.75 seconds
Started Feb 09 06:34:39 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 206524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023813023 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_intg_err.1023813023
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_dout_din_regs_random_rw.3227912434
Short name T69
Test name
Test status
Simulation time 53417924 ps
CPU time 0.82 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227912434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3227912434
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_intr_rand_pgm.1275888684
Short name T47
Test name
Test status
Simulation time 77616557 ps
CPU time 1.06 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:26 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275888684 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1275888684
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_csr_aliasing.32019710
Short name T97
Test name
Test status
Simulation time 35935657 ps
CPU time 1.01 seconds
Started Feb 09 06:34:04 AM UTC 25
Finished Feb 09 06:34:06 AM UTC 25
Peak memory 202028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32019710 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.32019710
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_csr_bit_bash.2660870605
Short name T718
Test name
Test status
Simulation time 355605409 ps
CPU time 1.68 seconds
Started Feb 09 06:34:07 AM UTC 25
Finished Feb 09 06:34:10 AM UTC 25
Peak memory 202016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660870605 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2660870605
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_csr_hw_reset.1277683707
Short name T123
Test name
Test status
Simulation time 21335100 ps
CPU time 0.9 seconds
Started Feb 09 06:34:07 AM UTC 25
Finished Feb 09 06:34:09 AM UTC 25
Peak memory 204064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277683707 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1277683707
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4215576998
Short name T715
Test name
Test status
Simulation time 63453525 ps
CPU time 1.07 seconds
Started Feb 09 06:34:04 AM UTC 25
Finished Feb 09 06:34:06 AM UTC 25
Peak memory 201300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4215576998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_r
and_reset.4215576998
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_intr_test.4234403726
Short name T716
Test name
Test status
Simulation time 17111497 ps
CPU time 0.89 seconds
Started Feb 09 06:34:06 AM UTC 25
Finished Feb 09 06:34:08 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234403726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4234403726
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_tl_errors.565034649
Short name T717
Test name
Test status
Simulation time 100388424 ps
CPU time 1.82 seconds
Started Feb 09 06:34:06 AM UTC 25
Finished Feb 09 06:34:09 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565034649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.565034649
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/0.gpio_tl_intg_err.1965694772
Short name T56
Test name
Test status
Simulation time 302188796 ps
CPU time 1.27 seconds
Started Feb 09 06:34:06 AM UTC 25
Finished Feb 09 06:34:08 AM UTC 25
Peak memory 205572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965694772 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_intg_err.1965694772
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_csr_aliasing.874660834
Short name T99
Test name
Test status
Simulation time 31862996 ps
CPU time 0.98 seconds
Started Feb 09 06:34:09 AM UTC 25
Finished Feb 09 06:34:12 AM UTC 25
Peak memory 203340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874660834 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.874660834
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_csr_bit_bash.72050647
Short name T101
Test name
Test status
Simulation time 58498158 ps
CPU time 2.99 seconds
Started Feb 09 06:34:11 AM UTC 25
Finished Feb 09 06:34:15 AM UTC 25
Peak memory 205640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72050647 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.72050647
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_csr_hw_reset.3130178987
Short name T124
Test name
Test status
Simulation time 116880570 ps
CPU time 0.95 seconds
Started Feb 09 06:34:11 AM UTC 25
Finished Feb 09 06:34:13 AM UTC 25
Peak memory 202016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130178987 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3130178987
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2346967385
Short name T719
Test name
Test status
Simulation time 21663470 ps
CPU time 1.06 seconds
Started Feb 09 06:34:10 AM UTC 25
Finished Feb 09 06:34:12 AM UTC 25
Peak memory 204968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2346967385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_r
and_reset.2346967385
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_csr_rw.906834190
Short name T98
Test name
Test status
Simulation time 23333362 ps
CPU time 0.88 seconds
Started Feb 09 06:34:08 AM UTC 25
Finished Feb 09 06:34:10 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906834190 -assert nopostproc +UVM_T
ESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_rw.906834190
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_intr_test.4014048704
Short name T720
Test name
Test status
Simulation time 14646684 ps
CPU time 0.9 seconds
Started Feb 09 06:34:11 AM UTC 25
Finished Feb 09 06:34:13 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014048704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4014048704
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1336400468
Short name T115
Test name
Test status
Simulation time 390824223 ps
CPU time 1.09 seconds
Started Feb 09 06:34:09 AM UTC 25
Finished Feb 09 06:34:12 AM UTC 25
Peak memory 204140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336400468 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_same_csr_outstanding.1336400468
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_tl_errors.2092735613
Short name T721
Test name
Test status
Simulation time 1433071910 ps
CPU time 3.92 seconds
Started Feb 09 06:34:10 AM UTC 25
Finished Feb 09 06:34:15 AM UTC 25
Peak memory 203180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092735613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2092735613
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/1.gpio_tl_intg_err.3872637116
Short name T57
Test name
Test status
Simulation time 380589120 ps
CPU time 2 seconds
Started Feb 09 06:34:10 AM UTC 25
Finished Feb 09 06:34:13 AM UTC 25
Peak memory 206524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872637116 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_intg_err.3872637116
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2190064790
Short name T759
Test name
Test status
Simulation time 68503392 ps
CPU time 1.39 seconds
Started Feb 09 06:34:36 AM UTC 25
Finished Feb 09 06:34:39 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2190064790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_
rand_reset.2190064790
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_csr_rw.1092475099
Short name T756
Test name
Test status
Simulation time 14123818 ps
CPU time 0.79 seconds
Started Feb 09 06:34:36 AM UTC 25
Finished Feb 09 06:34:38 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092475099 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_rw.1092475099
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_intr_test.1432730499
Short name T762
Test name
Test status
Simulation time 12294968 ps
CPU time 0.92 seconds
Started Feb 09 06:34:37 AM UTC 25
Finished Feb 09 06:34:40 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432730499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1432730499
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1934494899
Short name T757
Test name
Test status
Simulation time 62043486 ps
CPU time 0.95 seconds
Started Feb 09 06:34:36 AM UTC 25
Finished Feb 09 06:34:38 AM UTC 25
Peak memory 202088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934494899 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_same_csr_outstanding.1934494899
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_tl_errors.3499652122
Short name T764
Test name
Test status
Simulation time 92216469 ps
CPU time 2.84 seconds
Started Feb 09 06:34:37 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 203304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499652122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3499652122
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/10.gpio_tl_intg_err.870059970
Short name T758
Test name
Test status
Simulation time 58241548 ps
CPU time 1.3 seconds
Started Feb 09 06:34:36 AM UTC 25
Finished Feb 09 06:34:39 AM UTC 25
Peak memory 204984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870059970 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_intg_err.870059970
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1874659573
Short name T754
Test name
Test status
Simulation time 31034156 ps
CPU time 1.23 seconds
Started Feb 09 06:34:38 AM UTC 25
Finished Feb 09 06:34:40 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1874659573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_
rand_reset.1874659573
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_csr_rw.1783759785
Short name T760
Test name
Test status
Simulation time 15549316 ps
CPU time 0.87 seconds
Started Feb 09 06:34:37 AM UTC 25
Finished Feb 09 06:34:40 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783759785 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_rw.1783759785
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_intr_test.3648086905
Short name T765
Test name
Test status
Simulation time 39337288 ps
CPU time 0.84 seconds
Started Feb 09 06:34:40 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648086905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3648086905
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3247939318
Short name T763
Test name
Test status
Simulation time 63354009 ps
CPU time 1.03 seconds
Started Feb 09 06:34:37 AM UTC 25
Finished Feb 09 06:34:40 AM UTC 25
Peak memory 203356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247939318 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_same_csr_outstanding.3247939318
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/11.gpio_tl_errors.2351177255
Short name T770
Test name
Test status
Simulation time 41962951 ps
CPU time 3.09 seconds
Started Feb 09 06:34:39 AM UTC 25
Finished Feb 09 06:34:43 AM UTC 25
Peak memory 206828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351177255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2351177255
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.65944931
Short name T768
Test name
Test status
Simulation time 21125470 ps
CPU time 1.06 seconds
Started Feb 09 06:34:40 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 204008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=65944931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_ra
nd_reset.65944931
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_csr_rw.4061729519
Short name T766
Test name
Test status
Simulation time 17428819 ps
CPU time 0.92 seconds
Started Feb 09 06:34:40 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061729519 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_rw.4061729519
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_intr_test.893217379
Short name T771
Test name
Test status
Simulation time 39565591 ps
CPU time 0.85 seconds
Started Feb 09 06:34:41 AM UTC 25
Finished Feb 09 06:34:43 AM UTC 25
Peak memory 201460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893217379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.893217379
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1220337732
Short name T767
Test name
Test status
Simulation time 76359997 ps
CPU time 0.99 seconds
Started Feb 09 06:34:40 AM UTC 25
Finished Feb 09 06:34:42 AM UTC 25
Peak memory 199980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220337732 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_same_csr_outstanding.1220337732
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_tl_errors.1742132846
Short name T777
Test name
Test status
Simulation time 41710518 ps
CPU time 2.85 seconds
Started Feb 09 06:34:41 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 202840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742132846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1742132846
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/12.gpio_tl_intg_err.520623525
Short name T769
Test name
Test status
Simulation time 148685272 ps
CPU time 1.51 seconds
Started Feb 09 06:34:40 AM UTC 25
Finished Feb 09 06:34:43 AM UTC 25
Peak memory 206528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520623525 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_intg_err.520623525
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1429264704
Short name T773
Test name
Test status
Simulation time 42884579 ps
CPU time 0.93 seconds
Started Feb 09 06:34:41 AM UTC 25
Finished Feb 09 06:34:44 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1429264704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_
rand_reset.1429264704
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_csr_rw.3549043804
Short name T772
Test name
Test status
Simulation time 51455849 ps
CPU time 0.86 seconds
Started Feb 09 06:34:41 AM UTC 25
Finished Feb 09 06:34:43 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549043804 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_rw.3549043804
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_intr_test.3990913863
Short name T776
Test name
Test status
Simulation time 13127497 ps
CPU time 0.84 seconds
Started Feb 09 06:34:43 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990913863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3990913863
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1729232541
Short name T774
Test name
Test status
Simulation time 47454820 ps
CPU time 1.06 seconds
Started Feb 09 06:34:41 AM UTC 25
Finished Feb 09 06:34:44 AM UTC 25
Peak memory 201788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729232541 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_same_csr_outstanding.1729232541
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_tl_errors.3967646630
Short name T775
Test name
Test status
Simulation time 172617779 ps
CPU time 1.34 seconds
Started Feb 09 06:34:42 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 202048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967646630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3967646630
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/13.gpio_tl_intg_err.478049804
Short name T73
Test name
Test status
Simulation time 206517328 ps
CPU time 1.32 seconds
Started Feb 09 06:34:42 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 205808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478049804 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_intg_err.478049804
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2835420036
Short name T779
Test name
Test status
Simulation time 30751772 ps
CPU time 1.18 seconds
Started Feb 09 06:34:43 AM UTC 25
Finished Feb 09 06:34:46 AM UTC 25
Peak memory 201968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2835420036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_
rand_reset.2835420036
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_csr_rw.4083554706
Short name T110
Test name
Test status
Simulation time 67217129 ps
CPU time 0.73 seconds
Started Feb 09 06:34:43 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083554706 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_rw.4083554706
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_intr_test.944592559
Short name T781
Test name
Test status
Simulation time 22191794 ps
CPU time 0.84 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:47 AM UTC 25
Peak memory 202652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944592559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.944592559
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1584842984
Short name T778
Test name
Test status
Simulation time 23485975 ps
CPU time 0.9 seconds
Started Feb 09 06:34:43 AM UTC 25
Finished Feb 09 06:34:46 AM UTC 25
Peak memory 200040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584842984 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_same_csr_outstanding.1584842984
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_tl_errors.571488350
Short name T790
Test name
Test status
Simulation time 107243149 ps
CPU time 2.72 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 203224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571488350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.571488350
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/14.gpio_tl_intg_err.2521093423
Short name T780
Test name
Test status
Simulation time 72047722 ps
CPU time 1.22 seconds
Started Feb 09 06:34:43 AM UTC 25
Finished Feb 09 06:34:46 AM UTC 25
Peak memory 204720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521093423 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_intg_err.2521093423
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3949478033
Short name T783
Test name
Test status
Simulation time 34881090 ps
CPU time 1.07 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:48 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3949478033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_
rand_reset.3949478033
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_csr_rw.3386994756
Short name T111
Test name
Test status
Simulation time 53592602 ps
CPU time 0.88 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:48 AM UTC 25
Peak memory 204572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386994756 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_rw.3386994756
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_intr_test.3816243604
Short name T787
Test name
Test status
Simulation time 35323381 ps
CPU time 0.84 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 201268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816243604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3816243604
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2830237611
Short name T782
Test name
Test status
Simulation time 54301787 ps
CPU time 1.05 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:48 AM UTC 25
Peak memory 204136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830237611 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_same_csr_outstanding.2830237611
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_tl_errors.2358515965
Short name T786
Test name
Test status
Simulation time 90722509 ps
CPU time 2.03 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 203348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358515965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2358515965
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/15.gpio_tl_intg_err.503725566
Short name T784
Test name
Test status
Simulation time 366556163 ps
CPU time 1.51 seconds
Started Feb 09 06:34:45 AM UTC 25
Finished Feb 09 06:34:48 AM UTC 25
Peak memory 206464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503725566 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_intg_err.503725566
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1499798752
Short name T788
Test name
Test status
Simulation time 41034015 ps
CPU time 1.17 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 201968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1499798752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_
rand_reset.1499798752
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_csr_rw.2872686099
Short name T785
Test name
Test status
Simulation time 13575102 ps
CPU time 0.82 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 204024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872686099 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_rw.2872686099
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_intr_test.2064268466
Short name T789
Test name
Test status
Simulation time 14490045 ps
CPU time 0.86 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064268466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2064268466
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3647277526
Short name T791
Test name
Test status
Simulation time 58986508 ps
CPU time 1.17 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 203356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647277526 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_same_csr_outstanding.3647277526
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_tl_errors.642347157
Short name T794
Test name
Test status
Simulation time 542672849 ps
CPU time 2.71 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:51 AM UTC 25
Peak memory 205256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642347157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.642347157
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/16.gpio_tl_intg_err.3655333715
Short name T792
Test name
Test status
Simulation time 53756745 ps
CPU time 1.31 seconds
Started Feb 09 06:34:46 AM UTC 25
Finished Feb 09 06:34:50 AM UTC 25
Peak memory 205236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655333715 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_intg_err.3655333715
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2260658541
Short name T796
Test name
Test status
Simulation time 14445176 ps
CPU time 0.9 seconds
Started Feb 09 06:34:49 AM UTC 25
Finished Feb 09 06:34:51 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2260658541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_
rand_reset.2260658541
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_csr_rw.1494383858
Short name T112
Test name
Test status
Simulation time 48051215 ps
CPU time 0.93 seconds
Started Feb 09 06:34:47 AM UTC 25
Finished Feb 09 06:34:49 AM UTC 25
Peak memory 201992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494383858 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_rw.1494383858
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_intr_test.446257935
Short name T795
Test name
Test status
Simulation time 29370295 ps
CPU time 0.75 seconds
Started Feb 09 06:34:49 AM UTC 25
Finished Feb 09 06:34:51 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446257935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.446257935
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_same_csr_outstanding.438743871
Short name T793
Test name
Test status
Simulation time 24259939 ps
CPU time 1.01 seconds
Started Feb 09 06:34:48 AM UTC 25
Finished Feb 09 06:34:51 AM UTC 25
Peak memory 203360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438743871 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_same_csr_outstanding.438743871
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_tl_errors.2422663451
Short name T799
Test name
Test status
Simulation time 92986996 ps
CPU time 1.53 seconds
Started Feb 09 06:34:49 AM UTC 25
Finished Feb 09 06:34:52 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422663451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2422663451
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/17.gpio_tl_intg_err.3227111686
Short name T798
Test name
Test status
Simulation time 157509904 ps
CPU time 1.28 seconds
Started Feb 09 06:34:49 AM UTC 25
Finished Feb 09 06:34:52 AM UTC 25
Peak memory 205716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227111686 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_intg_err.3227111686
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1723134559
Short name T802
Test name
Test status
Simulation time 20981141 ps
CPU time 0.84 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:52 AM UTC 25
Peak memory 201968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1723134559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_
rand_reset.1723134559
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_csr_rw.1420143361
Short name T797
Test name
Test status
Simulation time 61422103 ps
CPU time 0.81 seconds
Started Feb 09 06:34:49 AM UTC 25
Finished Feb 09 06:34:51 AM UTC 25
Peak memory 203356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420143361 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_rw.1420143361
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_intr_test.1343779684
Short name T801
Test name
Test status
Simulation time 103017622 ps
CPU time 0.74 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:52 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343779684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1343779684
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_same_csr_outstanding.6016848
Short name T800
Test name
Test status
Simulation time 74866635 ps
CPU time 0.72 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:52 AM UTC 25
Peak memory 198000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6016848 -assert n
opostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_same_csr_outstanding.6016848
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_tl_errors.3593290193
Short name T806
Test name
Test status
Simulation time 186030302 ps
CPU time 2.4 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:54 AM UTC 25
Peak memory 203304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593290193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3593290193
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/18.gpio_tl_intg_err.1729675775
Short name T805
Test name
Test status
Simulation time 79937291 ps
CPU time 1.46 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:53 AM UTC 25
Peak memory 206524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729675775 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_intg_err.1729675775
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.813065089
Short name T803
Test name
Test status
Simulation time 29797663 ps
CPU time 0.84 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:53 AM UTC 25
Peak memory 201300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=813065089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_r
and_reset.813065089
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_csr_rw.3058200811
Short name T113
Test name
Test status
Simulation time 20985452 ps
CPU time 0.8 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:53 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058200811 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_rw.3058200811
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_intr_test.1075653404
Short name T814
Test name
Test status
Simulation time 16714928 ps
CPU time 0.9 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075653404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1075653404
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1110678452
Short name T804
Test name
Test status
Simulation time 33028660 ps
CPU time 0.94 seconds
Started Feb 09 06:34:50 AM UTC 25
Finished Feb 09 06:34:53 AM UTC 25
Peak memory 200040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110678452 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_same_csr_outstanding.1110678452
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_tl_errors.969313083
Short name T815
Test name
Test status
Simulation time 120467135 ps
CPU time 2.6 seconds
Started Feb 09 06:34:51 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 203220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969313083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.969313083
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/19.gpio_tl_intg_err.3234948610
Short name T807
Test name
Test status
Simulation time 116970232 ps
CPU time 1.59 seconds
Started Feb 09 06:34:51 AM UTC 25
Finished Feb 09 06:34:54 AM UTC 25
Peak memory 206564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234948610 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_intg_err.3234948610
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_csr_aliasing.3924547206
Short name T722
Test name
Test status
Simulation time 24692622 ps
CPU time 1.16 seconds
Started Feb 09 06:34:13 AM UTC 25
Finished Feb 09 06:34:15 AM UTC 25
Peak memory 202028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924547206 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.3924547206
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_csr_bit_bash.4041602563
Short name T105
Test name
Test status
Simulation time 61102224 ps
CPU time 3.08 seconds
Started Feb 09 06:34:16 AM UTC 25
Finished Feb 09 06:34:20 AM UTC 25
Peak memory 203100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041602563 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4041602563
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_csr_hw_reset.3828352906
Short name T102
Test name
Test status
Simulation time 85148941 ps
CPU time 0.9 seconds
Started Feb 09 06:34:16 AM UTC 25
Finished Feb 09 06:34:18 AM UTC 25
Peak memory 203348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828352906 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3828352906
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2749616715
Short name T723
Test name
Test status
Simulation time 46064165 ps
CPU time 1.21 seconds
Started Feb 09 06:34:14 AM UTC 25
Finished Feb 09 06:34:16 AM UTC 25
Peak memory 206448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2749616715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_r
and_reset.2749616715
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_intr_test.1268148990
Short name T724
Test name
Test status
Simulation time 16434485 ps
CPU time 0.87 seconds
Started Feb 09 06:34:15 AM UTC 25
Finished Feb 09 06:34:17 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268148990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1268148990
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2882751860
Short name T116
Test name
Test status
Simulation time 23460784 ps
CPU time 0.86 seconds
Started Feb 09 06:34:13 AM UTC 25
Finished Feb 09 06:34:15 AM UTC 25
Peak memory 200052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882751860 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_same_csr_outstanding.2882751860
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_tl_errors.1425153499
Short name T725
Test name
Test status
Simulation time 278974099 ps
CPU time 3.74 seconds
Started Feb 09 06:34:14 AM UTC 25
Finished Feb 09 06:34:19 AM UTC 25
Peak memory 203236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425153499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1425153499
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/2.gpio_tl_intg_err.2901424655
Short name T58
Test name
Test status
Simulation time 47807539 ps
CPU time 1.31 seconds
Started Feb 09 06:34:14 AM UTC 25
Finished Feb 09 06:34:16 AM UTC 25
Peak memory 205808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901424655 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_intg_err.2901424655
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/20.gpio_intr_test.1702826808
Short name T809
Test name
Test status
Simulation time 22802565 ps
CPU time 0.83 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702826808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1702826808
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/21.gpio_intr_test.2132821009
Short name T808
Test name
Test status
Simulation time 22924864 ps
CPU time 0.86 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:54 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132821009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2132821009
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/22.gpio_intr_test.3175685340
Short name T812
Test name
Test status
Simulation time 12788390 ps
CPU time 0.78 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175685340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3175685340
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/23.gpio_intr_test.3599138258
Short name T810
Test name
Test status
Simulation time 178453444 ps
CPU time 0.77 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599138258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3599138258
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/24.gpio_intr_test.81852244
Short name T813
Test name
Test status
Simulation time 15388691 ps
CPU time 0.75 seconds
Started Feb 09 06:34:52 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81852244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.81852244
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/25.gpio_intr_test.3051251933
Short name T811
Test name
Test status
Simulation time 72800402 ps
CPU time 0.6 seconds
Started Feb 09 06:34:53 AM UTC 25
Finished Feb 09 06:34:55 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051251933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3051251933
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/26.gpio_intr_test.112895292
Short name T816
Test name
Test status
Simulation time 43998972 ps
CPU time 0.77 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112895292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.112895292
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/27.gpio_intr_test.3553139028
Short name T818
Test name
Test status
Simulation time 20672549 ps
CPU time 0.87 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553139028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3553139028
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/28.gpio_intr_test.1885066958
Short name T817
Test name
Test status
Simulation time 33135532 ps
CPU time 0.78 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885066958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1885066958
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/29.gpio_intr_test.995024217
Short name T819
Test name
Test status
Simulation time 64575995 ps
CPU time 0.81 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995024217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.995024217
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_csr_aliasing.1065834046
Short name T726
Test name
Test status
Simulation time 27811038 ps
CPU time 1.18 seconds
Started Feb 09 06:34:17 AM UTC 25
Finished Feb 09 06:34:20 AM UTC 25
Peak memory 202028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065834046 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_aliasing.1065834046
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_csr_bit_bash.3969157554
Short name T734
Test name
Test status
Simulation time 337873819 ps
CPU time 5.2 seconds
Started Feb 09 06:34:21 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 202868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969157554 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3969157554
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_csr_hw_reset.3678003899
Short name T729
Test name
Test status
Simulation time 23495613 ps
CPU time 0.9 seconds
Started Feb 09 06:34:20 AM UTC 25
Finished Feb 09 06:34:22 AM UTC 25
Peak memory 202016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678003899 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3678003899
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2715980674
Short name T727
Test name
Test status
Simulation time 22053926 ps
CPU time 1.73 seconds
Started Feb 09 06:34:17 AM UTC 25
Finished Feb 09 06:34:20 AM UTC 25
Peak memory 201300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2715980674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_r
and_reset.2715980674
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_csr_rw.4046723224
Short name T103
Test name
Test status
Simulation time 15700489 ps
CPU time 0.89 seconds
Started Feb 09 06:34:16 AM UTC 25
Finished Feb 09 06:34:18 AM UTC 25
Peak memory 203356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046723224 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_rw.4046723224
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_intr_test.3564323759
Short name T728
Test name
Test status
Simulation time 123370696 ps
CPU time 0.91 seconds
Started Feb 09 06:34:20 AM UTC 25
Finished Feb 09 06:34:22 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564323759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3564323759
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3797462425
Short name T104
Test name
Test status
Simulation time 34975653 ps
CPU time 0.95 seconds
Started Feb 09 06:34:16 AM UTC 25
Finished Feb 09 06:34:18 AM UTC 25
Peak memory 202092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797462425 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_same_csr_outstanding.3797462425
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_tl_errors.2340498045
Short name T731
Test name
Test status
Simulation time 423730655 ps
CPU time 3.67 seconds
Started Feb 09 06:34:19 AM UTC 25
Finished Feb 09 06:34:25 AM UTC 25
Peak memory 206632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340498045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2340498045
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/3.gpio_tl_intg_err.3610071518
Short name T60
Test name
Test status
Simulation time 89281951 ps
CPU time 1.45 seconds
Started Feb 09 06:34:18 AM UTC 25
Finished Feb 09 06:34:21 AM UTC 25
Peak memory 206584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610071518 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_intg_err.3610071518
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/30.gpio_intr_test.1602224509
Short name T820
Test name
Test status
Simulation time 52357476 ps
CPU time 0.82 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602224509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1602224509
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/31.gpio_intr_test.761019190
Short name T822
Test name
Test status
Simulation time 24773998 ps
CPU time 0.92 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761019190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.761019190
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/32.gpio_intr_test.521866289
Short name T821
Test name
Test status
Simulation time 58270561 ps
CPU time 0.71 seconds
Started Feb 09 06:34:54 AM UTC 25
Finished Feb 09 06:34:56 AM UTC 25
Peak memory 201904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521866289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.521866289
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/33.gpio_intr_test.2933647127
Short name T826
Test name
Test status
Simulation time 29701155 ps
CPU time 0.88 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933647127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2933647127
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/34.gpio_intr_test.1887608898
Short name T825
Test name
Test status
Simulation time 33039046 ps
CPU time 0.85 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887608898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1887608898
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/35.gpio_intr_test.1712239767
Short name T823
Test name
Test status
Simulation time 14727809 ps
CPU time 0.81 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712239767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1712239767
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/36.gpio_intr_test.349064584
Short name T829
Test name
Test status
Simulation time 17782912 ps
CPU time 0.91 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349064584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.349064584
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/37.gpio_intr_test.2350682596
Short name T828
Test name
Test status
Simulation time 11876570 ps
CPU time 0.83 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350682596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2350682596
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/38.gpio_intr_test.1271924803
Short name T824
Test name
Test status
Simulation time 42523905 ps
CPU time 0.73 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271924803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1271924803
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/39.gpio_intr_test.691867264
Short name T827
Test name
Test status
Simulation time 50660617 ps
CPU time 0.88 seconds
Started Feb 09 06:34:55 AM UTC 25
Finished Feb 09 06:34:57 AM UTC 25
Peak memory 200940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691867264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.691867264
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_csr_aliasing.72603811
Short name T106
Test name
Test status
Simulation time 117288434 ps
CPU time 1.25 seconds
Started Feb 09 06:34:22 AM UTC 25
Finished Feb 09 06:34:24 AM UTC 25
Peak memory 202036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72603811 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_aliasing.72603811
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_csr_bit_bash.682677120
Short name T738
Test name
Test status
Simulation time 391671154 ps
CPU time 3.5 seconds
Started Feb 09 06:34:25 AM UTC 25
Finished Feb 09 06:34:30 AM UTC 25
Peak memory 206520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682677120 -assert nopostproc +UVM_TESTNAME=gpio_base_tes
t +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.682677120
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_csr_hw_reset.3827891411
Short name T107
Test name
Test status
Simulation time 24771518 ps
CPU time 1 seconds
Started Feb 09 06:34:24 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 204064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827891411 -assert nopostproc +UVM_TESTNAME=gpio_base_te
st +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3827891411
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.246898064
Short name T732
Test name
Test status
Simulation time 17249581 ps
CPU time 1.03 seconds
Started Feb 09 06:34:23 AM UTC 25
Finished Feb 09 06:34:25 AM UTC 25
Peak memory 204748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=246898064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_ra
nd_reset.246898064
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_csr_rw.3455677278
Short name T730
Test name
Test status
Simulation time 55016816 ps
CPU time 0.88 seconds
Started Feb 09 06:34:21 AM UTC 25
Finished Feb 09 06:34:23 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455677278 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_rw.3455677278
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_intr_test.3486470290
Short name T733
Test name
Test status
Simulation time 13058769 ps
CPU time 0.88 seconds
Started Feb 09 06:34:24 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486470290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3486470290
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2705363084
Short name T117
Test name
Test status
Simulation time 20330912 ps
CPU time 0.91 seconds
Started Feb 09 06:34:21 AM UTC 25
Finished Feb 09 06:34:23 AM UTC 25
Peak memory 204148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705363084 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_same_csr_outstanding.2705363084
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/4.gpio_tl_errors.3544513842
Short name T736
Test name
Test status
Simulation time 48412733 ps
CPU time 3.61 seconds
Started Feb 09 06:34:23 AM UTC 25
Finished Feb 09 06:34:28 AM UTC 25
Peak memory 205268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544513842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3544513842
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/40.gpio_intr_test.567752475
Short name T832
Test name
Test status
Simulation time 16304517 ps
CPU time 0.83 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567752475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.567752475
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/41.gpio_intr_test.622615896
Short name T830
Test name
Test status
Simulation time 53847818 ps
CPU time 0.79 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622615896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.622615896
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/42.gpio_intr_test.671616144
Short name T833
Test name
Test status
Simulation time 15629536 ps
CPU time 0.79 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671616144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.671616144
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/43.gpio_intr_test.4082065219
Short name T831
Test name
Test status
Simulation time 40758658 ps
CPU time 0.74 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082065219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4082065219
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/44.gpio_intr_test.1003637591
Short name T834
Test name
Test status
Simulation time 62076233 ps
CPU time 0.84 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003637591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1003637591
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/45.gpio_intr_test.4064866100
Short name T835
Test name
Test status
Simulation time 14170989 ps
CPU time 0.86 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064866100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.4064866100
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/46.gpio_intr_test.2238486984
Short name T836
Test name
Test status
Simulation time 18562351 ps
CPU time 0.85 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:58 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238486984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2238486984
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/47.gpio_intr_test.724807939
Short name T837
Test name
Test status
Simulation time 45268619 ps
CPU time 0.84 seconds
Started Feb 09 06:34:56 AM UTC 25
Finished Feb 09 06:34:59 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724807939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.724807939
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/48.gpio_intr_test.706742940
Short name T839
Test name
Test status
Simulation time 22881073 ps
CPU time 0.84 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706742940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.706742940
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/49.gpio_intr_test.2870759004
Short name T838
Test name
Test status
Simulation time 14468857 ps
CPU time 0.75 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:34:59 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870759004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2870759004
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3133045550
Short name T740
Test name
Test status
Simulation time 386014503 ps
CPU time 1.98 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:31 AM UTC 25
Peak memory 204008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3133045550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_r
and_reset.3133045550
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_csr_rw.1963520680
Short name T735
Test name
Test status
Simulation time 38786234 ps
CPU time 0.83 seconds
Started Feb 09 06:34:25 AM UTC 25
Finished Feb 09 06:34:28 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963520680 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_rw.1963520680
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_intr_test.27432887
Short name T737
Test name
Test status
Simulation time 20782888 ps
CPU time 0.8 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:30 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27432887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.27432887
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4139240285
Short name T118
Test name
Test status
Simulation time 51845860 ps
CPU time 1.06 seconds
Started Feb 09 06:34:26 AM UTC 25
Finished Feb 09 06:34:29 AM UTC 25
Peak memory 203360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139240285 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_same_csr_outstanding.4139240285
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_tl_errors.529961973
Short name T744
Test name
Test status
Simulation time 131486652 ps
CPU time 3.68 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:33 AM UTC 25
Peak memory 203212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529961973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.529961973
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/5.gpio_tl_intg_err.1117648344
Short name T74
Test name
Test status
Simulation time 186660265 ps
CPU time 1.29 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:30 AM UTC 25
Peak memory 204692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117648344 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_intg_err.1117648344
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1611030350
Short name T739
Test name
Test status
Simulation time 61808772 ps
CPU time 1.14 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:31 AM UTC 25
Peak memory 206448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1611030350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_r
and_reset.1611030350
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_csr_rw.2527660364
Short name T108
Test name
Test status
Simulation time 23200155 ps
CPU time 0.9 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:30 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527660364 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_rw.2527660364
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_intr_test.2889131759
Short name T741
Test name
Test status
Simulation time 51441013 ps
CPU time 0.88 seconds
Started Feb 09 06:34:29 AM UTC 25
Finished Feb 09 06:34:31 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889131759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2889131759
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1183131728
Short name T119
Test name
Test status
Simulation time 19750331 ps
CPU time 1.07 seconds
Started Feb 09 06:34:28 AM UTC 25
Finished Feb 09 06:34:31 AM UTC 25
Peak memory 199984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183131728 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_same_csr_outstanding.1183131728
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_tl_errors.1321307441
Short name T743
Test name
Test status
Simulation time 26181701 ps
CPU time 1.85 seconds
Started Feb 09 06:34:29 AM UTC 25
Finished Feb 09 06:34:32 AM UTC 25
Peak memory 202088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321307441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1321307441
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/6.gpio_tl_intg_err.933883126
Short name T75
Test name
Test status
Simulation time 1010375185 ps
CPU time 1.71 seconds
Started Feb 09 06:34:29 AM UTC 25
Finished Feb 09 06:34:32 AM UTC 25
Peak memory 206648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933883126 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_intg_err.933883126
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3824707246
Short name T746
Test name
Test status
Simulation time 66786664 ps
CPU time 1.14 seconds
Started Feb 09 06:34:31 AM UTC 25
Finished Feb 09 06:34:34 AM UTC 25
Peak memory 206288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3824707246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_r
and_reset.3824707246
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_csr_rw.2008367612
Short name T742
Test name
Test status
Simulation time 43267882 ps
CPU time 0.92 seconds
Started Feb 09 06:34:29 AM UTC 25
Finished Feb 09 06:34:32 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008367612 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_rw.2008367612
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_intr_test.513727242
Short name T745
Test name
Test status
Simulation time 30540157 ps
CPU time 0.92 seconds
Started Feb 09 06:34:31 AM UTC 25
Finished Feb 09 06:34:34 AM UTC 25
Peak memory 201304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513727242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.513727242
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3610029520
Short name T120
Test name
Test status
Simulation time 35346816 ps
CPU time 1.19 seconds
Started Feb 09 06:34:30 AM UTC 25
Finished Feb 09 06:34:33 AM UTC 25
Peak memory 203360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610029520 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_same_csr_outstanding.3610029520
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_tl_errors.3009415127
Short name T747
Test name
Test status
Simulation time 56259366 ps
CPU time 1.99 seconds
Started Feb 09 06:34:31 AM UTC 25
Finished Feb 09 06:34:35 AM UTC 25
Peak memory 201980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009415127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3009415127
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/7.gpio_tl_intg_err.2303745536
Short name T71
Test name
Test status
Simulation time 140915360 ps
CPU time 2.18 seconds
Started Feb 09 06:34:31 AM UTC 25
Finished Feb 09 06:34:35 AM UTC 25
Peak memory 206608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303745536 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_intg_err.2303745536
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1353121876
Short name T750
Test name
Test status
Simulation time 35646726 ps
CPU time 2.35 seconds
Started Feb 09 06:34:33 AM UTC 25
Finished Feb 09 06:34:36 AM UTC 25
Peak memory 206532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1353121876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_r
and_reset.1353121876
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_csr_rw.2814391844
Short name T109
Test name
Test status
Simulation time 29017093 ps
CPU time 0.91 seconds
Started Feb 09 06:34:31 AM UTC 25
Finished Feb 09 06:34:34 AM UTC 25
Peak memory 204072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814391844 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_rw.2814391844
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_intr_test.1399430406
Short name T749
Test name
Test status
Simulation time 17281259 ps
CPU time 0.87 seconds
Started Feb 09 06:34:34 AM UTC 25
Finished Feb 09 06:34:36 AM UTC 25
Peak memory 201308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399430406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1399430406
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_same_csr_outstanding.206317585
Short name T121
Test name
Test status
Simulation time 44041048 ps
CPU time 0.92 seconds
Started Feb 09 06:34:32 AM UTC 25
Finished Feb 09 06:34:34 AM UTC 25
Peak memory 202092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206317585 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_same_csr_outstanding.206317585
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_tl_errors.1813210447
Short name T751
Test name
Test status
Simulation time 98165046 ps
CPU time 2.65 seconds
Started Feb 09 06:34:33 AM UTC 25
Finished Feb 09 06:34:37 AM UTC 25
Peak memory 205340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813210447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1813210447
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/8.gpio_tl_intg_err.1182636263
Short name T70
Test name
Test status
Simulation time 41853706 ps
CPU time 1.13 seconds
Started Feb 09 06:34:33 AM UTC 25
Finished Feb 09 06:34:35 AM UTC 25
Peak memory 205164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182636263 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_intg_err.1182636263
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1861634705
Short name T752
Test name
Test status
Simulation time 50549924 ps
CPU time 0.92 seconds
Started Feb 09 06:34:35 AM UTC 25
Finished Feb 09 06:34:37 AM UTC 25
Peak memory 201960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100
00000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1861634705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_r
and_reset.1861634705
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_csr_rw.4200299089
Short name T748
Test name
Test status
Simulation time 84452848 ps
CPU time 0.84 seconds
Started Feb 09 06:34:34 AM UTC 25
Finished Feb 09 06:34:36 AM UTC 25
Peak memory 202024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200299089 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_rw.4200299089
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_intr_test.2580610789
Short name T753
Test name
Test status
Simulation time 13583214 ps
CPU time 0.87 seconds
Started Feb 09 06:34:35 AM UTC 25
Finished Feb 09 06:34:37 AM UTC 25
Peak memory 201964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580610789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2580610789
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2344575943
Short name T122
Test name
Test status
Simulation time 125698929 ps
CPU time 1.25 seconds
Started Feb 09 06:34:34 AM UTC 25
Finished Feb 09 06:34:36 AM UTC 25
Peak memory 200044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344575943 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_same_csr_outstanding.2344575943
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_tl_errors.1945729633
Short name T761
Test name
Test status
Simulation time 689074503 ps
CPU time 3.3 seconds
Started Feb 09 06:34:35 AM UTC 25
Finished Feb 09 06:34:40 AM UTC 25
Peak memory 206652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945729633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1945729633
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/cover_reg_top/9.gpio_tl_intg_err.521180862
Short name T755
Test name
Test status
Simulation time 218027443 ps
CPU time 2.11 seconds
Started Feb 09 06:34:35 AM UTC 25
Finished Feb 09 06:34:38 AM UTC 25
Peak memory 206612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521180862 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_intg_err.521180862
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_filter_stress.1007502119
Short name T52
Test name
Test status
Simulation time 70696634 ps
CPU time 3.1 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:29 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007502119 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress.1007502119
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3482626582
Short name T48
Test name
Test status
Simulation time 82336605 ps
CPU time 1.87 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:27 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482626582 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3482626582
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_rand_intr_trigger.1021543262
Short name T51
Test name
Test status
Simulation time 393932899 ps
CPU time 2.66 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021543262 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.1021543262
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_random_dout_din.2521011355
Short name T45
Test name
Test status
Simulation time 18715620 ps
CPU time 0.97 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:26 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521011355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.gpio_random_dout_din.2521011355
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1021495428
Short name T43
Test name
Test status
Simulation time 52536618 ps
CPU time 0.77 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:26 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021495428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_pulldown.1021495428
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2265214509
Short name T125
Test name
Test status
Simulation time 473840565 ps
CPU time 5.06 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:28:31 AM UTC 25
Peak memory 198808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265214509 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_long_reg_writes_reg_reads.2265214509
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_smoke.1562935035
Short name T42
Test name
Test status
Simulation time 313542935 ps
CPU time 1.09 seconds
Started Feb 09 06:28:23 AM UTC 25
Finished Feb 09 06:28:25 AM UTC 25
Peak memory 198368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562935035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.gpio_smoke.1562935035
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_smoke_no_pullup_pulldown.2557018229
Short name T41
Test name
Test status
Simulation time 93481983 ps
CPU time 1.05 seconds
Started Feb 09 06:28:23 AM UTC 25
Finished Feb 09 06:28:25 AM UTC 25
Peak memory 198200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557018229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2557018229
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/0.gpio_stress_all.1410831987
Short name T292
Test name
Test status
Simulation time 1542542082 ps
CPU time 41.95 seconds
Started Feb 09 06:28:24 AM UTC 25
Finished Feb 09 06:29:08 AM UTC 25
Peak memory 200776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410831987 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all.1410831987
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_alert_test.846393354
Short name T66
Test name
Test status
Simulation time 29614836 ps
CPU time 0.54 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:29 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846393354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.846393354
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_filter_stress.3259510132
Short name T132
Test name
Test status
Simulation time 421247919 ps
CPU time 3.61 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259510132 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.3259510132
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_full_random.1079084217
Short name T64
Test name
Test status
Simulation time 135123485 ps
CPU time 1.06 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079084217 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1079084217
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_rand_intr_trigger.591841039
Short name T126
Test name
Test status
Simulation time 112140398 ps
CPU time 1.39 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591841039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.591841039
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_random_dout_din.2761528692
Short name T77
Test name
Test status
Simulation time 93663627 ps
CPU time 1.04 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761528692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.gpio_random_dout_din.2761528692
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.297819446
Short name T50
Test name
Test status
Simulation time 49007797 ps
CPU time 0.68 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297819446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_pulldown.297819446
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1908204224
Short name T65
Test name
Test status
Simulation time 124464356 ps
CPU time 1.58 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908204224 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_long_reg_writes_reg_reads.1908204224
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_sec_cm.3163308582
Short name T63
Test name
Test status
Simulation time 146898078 ps
CPU time 0.83 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 235388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163308582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3163308582
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_smoke.2683263864
Short name T59
Test name
Test status
Simulation time 89254476 ps
CPU time 0.9 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683263864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.gpio_smoke.2683263864
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_smoke_no_pullup_pulldown.915955486
Short name T68
Test name
Test status
Simulation time 163001150 ps
CPU time 0.93 seconds
Started Feb 09 06:28:26 AM UTC 25
Finished Feb 09 06:28:28 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915955486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.915955486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/1.gpio_stress_all.778983298
Short name T517
Test name
Test status
Simulation time 14556016159 ps
CPU time 174.27 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:31:25 AM UTC 25
Peak memory 201084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778983298 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all.778983298
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_alert_test.4210736234
Short name T195
Test name
Test status
Simulation time 12011522 ps
CPU time 0.68 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:44 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210736234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4210736234
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_dout_din_regs_random_rw.897692352
Short name T189
Test name
Test status
Simulation time 16121006 ps
CPU time 0.66 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897692352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.897692352
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_filter_stress.2313963501
Short name T263
Test name
Test status
Simulation time 533186362 ps
CPU time 15.7 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:59 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313963501 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stress.2313963501
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_full_random.502610637
Short name T197
Test name
Test status
Simulation time 143090450 ps
CPU time 0.99 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:45 AM UTC 25
Peak memory 198200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502610637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.502610637
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_intr_rand_pgm.2378677699
Short name T198
Test name
Test status
Simulation time 118290849 ps
CPU time 1.33 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:45 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378677699 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2378677699
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4070489190
Short name T202
Test name
Test status
Simulation time 198532850 ps
CPU time 1.86 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:45 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070489190 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4070489190
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_rand_intr_trigger.1323207058
Short name T199
Test name
Test status
Simulation time 276994511 ps
CPU time 1.16 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:45 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323207058 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.1323207058
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_random_dout_din.1422759966
Short name T191
Test name
Test status
Simulation time 66741652 ps
CPU time 0.88 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422759966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.gpio_random_dout_din.1422759966
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3924239147
Short name T188
Test name
Test status
Simulation time 23799822 ps
CPU time 0.73 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924239147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup_pulldown.3924239147
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_random_long_reg_writes_reg_reads.450205384
Short name T210
Test name
Test status
Simulation time 752297278 ps
CPU time 3.24 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450205384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_long_reg_writes_reg_reads.450205384
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_smoke.2618710639
Short name T190
Test name
Test status
Simulation time 49081063 ps
CPU time 1.17 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618710639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.gpio_smoke.2618710639
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_smoke_no_pullup_pulldown.2236431483
Short name T192
Test name
Test status
Simulation time 104867231 ps
CPU time 1.09 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236431483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2236431483
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/10.gpio_stress_all.639441545
Short name T10
Test name
Test status
Simulation time 28710451387 ps
CPU time 107.2 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:30:32 AM UTC 25
Peak memory 201012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639441545 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all.639441545
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_alert_test.2125769698
Short name T211
Test name
Test status
Simulation time 11714088 ps
CPU time 0.59 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125769698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2125769698
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_dout_din_regs_random_rw.429827783
Short name T205
Test name
Test status
Simulation time 55816837 ps
CPU time 0.96 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429827783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.429827783
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_filter_stress.1957692782
Short name T276
Test name
Test status
Simulation time 593852941 ps
CPU time 17.89 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957692782 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress.1957692782
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_full_random.7657449
Short name T40
Test name
Test status
Simulation time 68996768 ps
CPU time 0.63 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7657449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.7657449
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_intr_rand_pgm.818662067
Short name T209
Test name
Test status
Simulation time 100085026 ps
CPU time 1.29 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818662067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.818662067
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_intr_with_filter_rand_intr_event.482481285
Short name T218
Test name
Test status
Simulation time 239286559 ps
CPU time 2.54 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:48 AM UTC 25
Peak memory 198680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482481285 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.482481285
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_rand_intr_trigger.2544232863
Short name T219
Test name
Test status
Simulation time 180201533 ps
CPU time 3 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:48 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544232863 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.2544232863
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_random_dout_din.3267500581
Short name T204
Test name
Test status
Simulation time 30102340 ps
CPU time 0.98 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267500581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.gpio_random_dout_din.3267500581
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1642812637
Short name T208
Test name
Test status
Simulation time 227967183 ps
CPU time 1.13 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642812637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup_pulldown.1642812637
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2436245627
Short name T222
Test name
Test status
Simulation time 472132358 ps
CPU time 4.18 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436245627 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_long_reg_writes_reg_reads.2436245627
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_smoke.4041023274
Short name T200
Test name
Test status
Simulation time 33589826 ps
CPU time 1.11 seconds
Started Feb 09 06:28:42 AM UTC 25
Finished Feb 09 06:28:45 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041023274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.gpio_smoke.4041023274
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_smoke_no_pullup_pulldown.675743049
Short name T206
Test name
Test status
Simulation time 38401607 ps
CPU time 1.1 seconds
Started Feb 09 06:28:43 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675743049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.675743049
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_stress_all.837927519
Short name T453
Test name
Test status
Simulation time 37074315446 ps
CPU time 125.32 seconds
Started Feb 09 06:28:44 AM UTC 25
Finished Feb 09 06:30:52 AM UTC 25
Peak memory 200892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837927519 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all.837927519
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/11.gpio_stress_all_with_rand_reset.248219404
Short name T708
Test name
Test status
Simulation time 156033499371 ps
CPU time 1111.57 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:47:30 AM UTC 25
Peak memory 206576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=248219404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress
_all_with_rand_reset.248219404
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_alert_test.1719039670
Short name T194
Test name
Test status
Simulation time 213381963 ps
CPU time 0.81 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719039670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1719039670
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_dout_din_regs_random_rw.937506656
Short name T214
Test name
Test status
Simulation time 99250552 ps
CPU time 0.92 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937506656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.937506656
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_filter_stress.1880731035
Short name T304
Test name
Test status
Simulation time 3886679131 ps
CPU time 26.08 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:29:14 AM UTC 25
Peak memory 198784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880731035 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stress.1880731035
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_full_random.2144212653
Short name T220
Test name
Test status
Simulation time 221884837 ps
CPU time 0.85 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:28:48 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144212653 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2144212653
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_intr_rand_pgm.3610323289
Short name T216
Test name
Test status
Simulation time 93450895 ps
CPU time 1.07 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610323289 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3610323289
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2262867439
Short name T221
Test name
Test status
Simulation time 32995868 ps
CPU time 1.49 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262867439 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2262867439
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_rand_intr_trigger.360388999
Short name T230
Test name
Test status
Simulation time 297254191 ps
CPU time 3.31 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:28:51 AM UTC 25
Peak memory 198692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360388999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.360388999
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_random_dout_din.510691605
Short name T213
Test name
Test status
Simulation time 89938582 ps
CPU time 0.96 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510691605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.gpio_random_dout_din.510691605
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.904972831
Short name T212
Test name
Test status
Simulation time 118294514 ps
CPU time 0.99 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904972831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup_pulldown.904972831
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3793856552
Short name T227
Test name
Test status
Simulation time 139109453 ps
CPU time 2.37 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:28:50 AM UTC 25
Peak memory 198604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793856552 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_long_reg_writes_reg_reads.3793856552
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_smoke.3234333545
Short name T215
Test name
Test status
Simulation time 62671390 ps
CPU time 1.2 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:47 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234333545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.gpio_smoke.3234333545
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_smoke_no_pullup_pulldown.3141241991
Short name T217
Test name
Test status
Simulation time 243115857 ps
CPU time 1.3 seconds
Started Feb 09 06:28:45 AM UTC 25
Finished Feb 09 06:28:48 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141241991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3141241991
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_stress_all.1292934599
Short name T574
Test name
Test status
Simulation time 8558490123 ps
CPU time 196.89 seconds
Started Feb 09 06:28:46 AM UTC 25
Finished Feb 09 06:32:06 AM UTC 25
Peak memory 200956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292934599 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all.1292934599
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/12.gpio_stress_all_with_rand_reset.2829552268
Short name T713
Test name
Test status
Simulation time 75938688987 ps
CPU time 1725.95 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:57:55 AM UTC 25
Peak memory 209752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2829552268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stres
s_all_with_rand_reset.2829552268
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_alert_test.591466211
Short name T231
Test name
Test status
Simulation time 18835655 ps
CPU time 0.71 seconds
Started Feb 09 06:28:49 AM UTC 25
Finished Feb 09 06:28:51 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591466211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.591466211
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_dout_din_regs_random_rw.213479653
Short name T223
Test name
Test status
Simulation time 18946528 ps
CPU time 0.91 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213479653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.213479653
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_filter_stress.1893468153
Short name T281
Test name
Test status
Simulation time 1737693490 ps
CPU time 15.33 seconds
Started Feb 09 06:28:48 AM UTC 25
Finished Feb 09 06:29:05 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893468153 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stress.1893468153
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_full_random.1389484035
Short name T232
Test name
Test status
Simulation time 84793379 ps
CPU time 0.91 seconds
Started Feb 09 06:28:48 AM UTC 25
Finished Feb 09 06:28:51 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389484035 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1389484035
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_intr_rand_pgm.3457976886
Short name T229
Test name
Test status
Simulation time 106241181 ps
CPU time 1.45 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:50 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457976886 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3457976886
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1512290040
Short name T240
Test name
Test status
Simulation time 217290021 ps
CPU time 3.28 seconds
Started Feb 09 06:28:48 AM UTC 25
Finished Feb 09 06:28:53 AM UTC 25
Peak memory 201008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512290040 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1512290040
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_rand_intr_trigger.33859473
Short name T234
Test name
Test status
Simulation time 355243724 ps
CPU time 2.44 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:51 AM UTC 25
Peak memory 198660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33859473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.33859473
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_random_dout_din.3712699511
Short name T201
Test name
Test status
Simulation time 39711680 ps
CPU time 0.93 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712699511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.gpio_random_dout_din.3712699511
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2515884896
Short name T228
Test name
Test status
Simulation time 71762370 ps
CPU time 1.33 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:50 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515884896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup_pulldown.2515884896
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_random_long_reg_writes_reg_reads.880862292
Short name T247
Test name
Test status
Simulation time 328936511 ps
CPU time 5.09 seconds
Started Feb 09 06:28:48 AM UTC 25
Finished Feb 09 06:28:55 AM UTC 25
Peak memory 200784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880862292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_long_reg_writes_reg_reads.880862292
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_smoke.2630982263
Short name T225
Test name
Test status
Simulation time 45649907 ps
CPU time 0.97 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630982263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.gpio_smoke.2630982263
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_smoke_no_pullup_pulldown.2046255597
Short name T226
Test name
Test status
Simulation time 22317157 ps
CPU time 1.14 seconds
Started Feb 09 06:28:47 AM UTC 25
Finished Feb 09 06:28:50 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046255597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2046255597
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_stress_all.1658803359
Short name T418
Test name
Test status
Simulation time 27786291070 ps
CPU time 94.6 seconds
Started Feb 09 06:28:48 AM UTC 25
Finished Feb 09 06:30:25 AM UTC 25
Peak memory 200848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658803359 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all.1658803359
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/13.gpio_stress_all_with_rand_reset.237766681
Short name T710
Test name
Test status
Simulation time 364570315366 ps
CPU time 1477.82 seconds
Started Feb 09 06:28:49 AM UTC 25
Finished Feb 09 06:53:42 AM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=237766681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress
_all_with_rand_reset.237766681
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_alert_test.4120971011
Short name T242
Test name
Test status
Simulation time 12484821 ps
CPU time 0.73 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:28:54 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120971011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4120971011
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_dout_din_regs_random_rw.4114970107
Short name T236
Test name
Test status
Simulation time 27368289 ps
CPU time 0.94 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:52 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114970107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4114970107
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_filter_stress.1529060784
Short name T285
Test name
Test status
Simulation time 960897562 ps
CPU time 12.49 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:29:06 AM UTC 25
Peak memory 198332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529060784 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stress.1529060784
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_full_random.3076317612
Short name T244
Test name
Test status
Simulation time 32589852 ps
CPU time 0.95 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:28:54 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076317612 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3076317612
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_intr_rand_pgm.2097657607
Short name T239
Test name
Test status
Simulation time 110226316 ps
CPU time 1.43 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:52 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097657607 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2097657607
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1112492117
Short name T243
Test name
Test status
Simulation time 123966184 ps
CPU time 2.04 seconds
Started Feb 09 06:28:51 AM UTC 25
Finished Feb 09 06:28:54 AM UTC 25
Peak memory 198896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112492117 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1112492117
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_rand_intr_trigger.1288771393
Short name T245
Test name
Test status
Simulation time 635574651 ps
CPU time 3.64 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:55 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288771393 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.1288771393
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_random_dout_din.3674773584
Short name T237
Test name
Test status
Simulation time 102977438 ps
CPU time 1.19 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:52 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674773584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.gpio_random_dout_din.3674773584
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.240807671
Short name T238
Test name
Test status
Simulation time 323195231 ps
CPU time 1.28 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:52 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240807671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_pulldown.240807671
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_random_long_reg_writes_reg_reads.495171618
Short name T4
Test name
Test status
Simulation time 562381675 ps
CPU time 1.99 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:28:55 AM UTC 25
Peak memory 198096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495171618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_long_reg_writes_reg_reads.495171618
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_smoke.3038122104
Short name T233
Test name
Test status
Simulation time 56174206 ps
CPU time 1.08 seconds
Started Feb 09 06:28:49 AM UTC 25
Finished Feb 09 06:28:51 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038122104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.gpio_smoke.3038122104
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_smoke_no_pullup_pulldown.1247737659
Short name T235
Test name
Test status
Simulation time 21172088 ps
CPU time 0.71 seconds
Started Feb 09 06:28:50 AM UTC 25
Finished Feb 09 06:28:52 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247737659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1247737659
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/14.gpio_stress_all.2211766074
Short name T9
Test name
Test status
Simulation time 125822406602 ps
CPU time 91.56 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:30:26 AM UTC 25
Peak memory 200776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211766074 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all.2211766074
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_alert_test.3616124629
Short name T256
Test name
Test status
Simulation time 14728420 ps
CPU time 0.83 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 197828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616124629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3616124629
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_dout_din_regs_random_rw.2300509043
Short name T249
Test name
Test status
Simulation time 72492619 ps
CPU time 0.86 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:28:56 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300509043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2300509043
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_filter_stress.2438371448
Short name T321
Test name
Test status
Simulation time 930617479 ps
CPU time 26.33 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:29:22 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438371448 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stress.2438371448
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_full_random.1050632248
Short name T257
Test name
Test status
Simulation time 128449913 ps
CPU time 1.01 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 197624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050632248 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1050632248
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_intr_rand_pgm.2310547907
Short name T250
Test name
Test status
Simulation time 73515974 ps
CPU time 0.93 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:28:56 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310547907 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2310547907
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_intr_with_filter_rand_intr_event.993262008
Short name T254
Test name
Test status
Simulation time 256164036 ps
CPU time 2.76 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 201076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993262008 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.993262008
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_rand_intr_trigger.1452758094
Short name T253
Test name
Test status
Simulation time 74406851 ps
CPU time 1.81 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:28:57 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452758094 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.1452758094
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_random_dout_din.910388500
Short name T251
Test name
Test status
Simulation time 109277081 ps
CPU time 1.23 seconds
Started Feb 09 06:28:53 AM UTC 25
Finished Feb 09 06:28:56 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910388500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.gpio_random_dout_din.910388500
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2728525368
Short name T252
Test name
Test status
Simulation time 127966358 ps
CPU time 1.21 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:28:56 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728525368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup_pulldown.2728525368
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4088416684
Short name T267
Test name
Test status
Simulation time 241829775 ps
CPU time 6.17 seconds
Started Feb 09 06:28:54 AM UTC 25
Finished Feb 09 06:29:01 AM UTC 25
Peak memory 198716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088416684 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_long_reg_writes_reg_reads.4088416684
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_smoke.3926405355
Short name T248
Test name
Test status
Simulation time 179098734 ps
CPU time 1.55 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:28:55 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926405355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.gpio_smoke.3926405355
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_smoke_no_pullup_pulldown.2098562076
Short name T246
Test name
Test status
Simulation time 33883245 ps
CPU time 1.13 seconds
Started Feb 09 06:28:52 AM UTC 25
Finished Feb 09 06:28:55 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098562076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2098562076
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/15.gpio_stress_all.3173172729
Short name T593
Test name
Test status
Simulation time 32628261598 ps
CPU time 203.69 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:32:23 AM UTC 25
Peak memory 200668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173172729 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all.3173172729
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_alert_test.1686294663
Short name T272
Test name
Test status
Simulation time 12952907 ps
CPU time 0.83 seconds
Started Feb 09 06:29:01 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686294663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1686294663
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_dout_din_regs_random_rw.4010703311
Short name T264
Test name
Test status
Simulation time 340730315 ps
CPU time 1 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:00 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010703311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4010703311
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_filter_stress.2967187167
Short name T279
Test name
Test status
Simulation time 734340309 ps
CPU time 5.44 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:05 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967187167 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stress.2967187167
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_full_random.2976200620
Short name T275
Test name
Test status
Simulation time 278707970 ps
CPU time 1.41 seconds
Started Feb 09 06:29:00 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976200620 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2976200620
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_intr_rand_pgm.3070792728
Short name T266
Test name
Test status
Simulation time 48804896 ps
CPU time 1.61 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:01 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070792728 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3070792728
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1052521248
Short name T271
Test name
Test status
Simulation time 281654437 ps
CPU time 2.84 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:02 AM UTC 25
Peak memory 198632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052521248 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1052521248
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_rand_intr_trigger.2222285097
Short name T269
Test name
Test status
Simulation time 458953788 ps
CPU time 2.22 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:02 AM UTC 25
Peak memory 198652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222285097 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.2222285097
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_random_dout_din.3707540593
Short name T259
Test name
Test status
Simulation time 64770615 ps
CPU time 1.23 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707540593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.gpio_random_dout_din.3707540593
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2481545449
Short name T261
Test name
Test status
Simulation time 68455151 ps
CPU time 1.44 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:59 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481545449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup_pulldown.2481545449
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1903809868
Short name T270
Test name
Test status
Simulation time 153060450 ps
CPU time 2.26 seconds
Started Feb 09 06:28:58 AM UTC 25
Finished Feb 09 06:29:02 AM UTC 25
Peak memory 198556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903809868 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_long_reg_writes_reg_reads.1903809868
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_smoke.1269263337
Short name T262
Test name
Test status
Simulation time 75566183 ps
CPU time 1.69 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:59 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269263337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.gpio_smoke.1269263337
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_smoke_no_pullup_pulldown.3121055137
Short name T260
Test name
Test status
Simulation time 63816907 ps
CPU time 1.29 seconds
Started Feb 09 06:28:56 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 198364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121055137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3121055137
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/16.gpio_stress_all.3756739487
Short name T392
Test name
Test status
Simulation time 2377983530 ps
CPU time 65.61 seconds
Started Feb 09 06:29:00 AM UTC 25
Finished Feb 09 06:30:08 AM UTC 25
Peak memory 200956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756739487 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all.3756739487
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_alert_test.1635273486
Short name T287
Test name
Test status
Simulation time 18530721 ps
CPU time 0.78 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:07 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635273486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1635273486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_dout_din_regs_random_rw.3222350902
Short name T280
Test name
Test status
Simulation time 71773815 ps
CPU time 1.08 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:05 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222350902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3222350902
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_filter_stress.955300789
Short name T338
Test name
Test status
Simulation time 506782861 ps
CPU time 27.04 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:31 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955300789 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress.955300789
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_full_random.1777820905
Short name T282
Test name
Test status
Simulation time 349695241 ps
CPU time 1.25 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:06 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777820905 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1777820905
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_intr_rand_pgm.3673691397
Short name T283
Test name
Test status
Simulation time 215589776 ps
CPU time 1.71 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:06 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673691397 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3673691397
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1335828505
Short name T284
Test name
Test status
Simulation time 42132153 ps
CPU time 1.97 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:06 AM UTC 25
Peak memory 200400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335828505 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1335828505
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_rand_intr_trigger.3697233319
Short name T286
Test name
Test status
Simulation time 68698723 ps
CPU time 2.43 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:06 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697233319 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.3697233319
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_random_dout_din.3767559600
Short name T274
Test name
Test status
Simulation time 34123532 ps
CPU time 1.07 seconds
Started Feb 09 06:29:01 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767559600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.gpio_random_dout_din.3767559600
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.177205657
Short name T273
Test name
Test status
Simulation time 24190524 ps
CPU time 0.8 seconds
Started Feb 09 06:29:01 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177205657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup_pulldown.177205657
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_random_long_reg_writes_reg_reads.849533700
Short name T5
Test name
Test status
Simulation time 249412974 ps
CPU time 4.72 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:29:09 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849533700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_long_reg_writes_reg_reads.849533700
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_smoke.3164834680
Short name T277
Test name
Test status
Simulation time 32229069 ps
CPU time 1.32 seconds
Started Feb 09 06:29:01 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164834680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.gpio_smoke.3164834680
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_smoke_no_pullup_pulldown.1030727388
Short name T278
Test name
Test status
Simulation time 53418964 ps
CPU time 1.37 seconds
Started Feb 09 06:29:01 AM UTC 25
Finished Feb 09 06:29:03 AM UTC 25
Peak memory 198072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030727388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1030727388
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_stress_all.426955469
Short name T519
Test name
Test status
Simulation time 11899093306 ps
CPU time 146.41 seconds
Started Feb 09 06:29:03 AM UTC 25
Finished Feb 09 06:31:32 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426955469 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all.426955469
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/17.gpio_stress_all_with_rand_reset.2374792337
Short name T86
Test name
Test status
Simulation time 34133858435 ps
CPU time 858.32 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:43:33 AM UTC 25
Peak memory 206656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2374792337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stres
s_all_with_rand_reset.2374792337
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_alert_test.2692468807
Short name T255
Test name
Test status
Simulation time 11528534 ps
CPU time 0.76 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:12 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692468807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2692468807
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_dout_din_regs_random_rw.4071023097
Short name T289
Test name
Test status
Simulation time 42271460 ps
CPU time 1.17 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:08 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071023097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4071023097
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_filter_stress.861634599
Short name T316
Test name
Test status
Simulation time 1849049226 ps
CPU time 11.9 seconds
Started Feb 09 06:29:07 AM UTC 25
Finished Feb 09 06:29:21 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861634599 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stress.861634599
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_full_random.2704320027
Short name T294
Test name
Test status
Simulation time 228797114 ps
CPU time 1.36 seconds
Started Feb 09 06:29:08 AM UTC 25
Finished Feb 09 06:29:10 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704320027 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2704320027
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_intr_rand_pgm.1717597741
Short name T296
Test name
Test status
Simulation time 752477938 ps
CPU time 2.05 seconds
Started Feb 09 06:29:07 AM UTC 25
Finished Feb 09 06:29:11 AM UTC 25
Peak memory 198736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717597741 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1717597741
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1651437925
Short name T295
Test name
Test status
Simulation time 29570693 ps
CPU time 1.94 seconds
Started Feb 09 06:29:07 AM UTC 25
Finished Feb 09 06:29:11 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651437925 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1651437925
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_rand_intr_trigger.3529513608
Short name T241
Test name
Test status
Simulation time 371962808 ps
CPU time 2.64 seconds
Started Feb 09 06:29:07 AM UTC 25
Finished Feb 09 06:29:11 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529513608 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.3529513608
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_random_dout_din.3236842055
Short name T288
Test name
Test status
Simulation time 204379378 ps
CPU time 0.87 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:07 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236842055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.gpio_random_dout_din.3236842055
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.691166181
Short name T290
Test name
Test status
Simulation time 28271257 ps
CPU time 1.25 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:08 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691166181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup_pulldown.691166181
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2469069042
Short name T303
Test name
Test status
Simulation time 278096835 ps
CPU time 4.54 seconds
Started Feb 09 06:29:07 AM UTC 25
Finished Feb 09 06:29:13 AM UTC 25
Peak memory 198812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469069042 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_long_reg_writes_reg_reads.2469069042
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_smoke.831662623
Short name T293
Test name
Test status
Simulation time 609443707 ps
CPU time 1.77 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:08 AM UTC 25
Peak memory 198328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831662623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.gpio_smoke.831662623
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_smoke_no_pullup_pulldown.452714578
Short name T291
Test name
Test status
Simulation time 52789113 ps
CPU time 1.4 seconds
Started Feb 09 06:29:05 AM UTC 25
Finished Feb 09 06:29:08 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452714578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.452714578
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/18.gpio_stress_all.2582262913
Short name T506
Test name
Test status
Simulation time 24853189919 ps
CPU time 129.15 seconds
Started Feb 09 06:29:08 AM UTC 25
Finished Feb 09 06:31:19 AM UTC 25
Peak memory 200832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582262913 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all.2582262913
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_alert_test.2535787680
Short name T307
Test name
Test status
Simulation time 72785288 ps
CPU time 0.83 seconds
Started Feb 09 06:29:14 AM UTC 25
Finished Feb 09 06:29:16 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535787680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2535787680
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_dout_din_regs_random_rw.1157413364
Short name T265
Test name
Test status
Simulation time 40971500 ps
CPU time 1 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:12 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157413364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1157413364
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_filter_stress.1693473859
Short name T352
Test name
Test status
Simulation time 1005220531 ps
CPU time 25.95 seconds
Started Feb 09 06:29:12 AM UTC 25
Finished Feb 09 06:29:39 AM UTC 25
Peak memory 198768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693473859 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress.1693473859
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_full_random.17723327
Short name T305
Test name
Test status
Simulation time 120832587 ps
CPU time 1.48 seconds
Started Feb 09 06:29:12 AM UTC 25
Finished Feb 09 06:29:15 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17723327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.17723327
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_intr_rand_pgm.1084865953
Short name T298
Test name
Test status
Simulation time 41729511 ps
CPU time 1.39 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:12 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084865953 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1084865953
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_intr_with_filter_rand_intr_event.432301071
Short name T306
Test name
Test status
Simulation time 100178499 ps
CPU time 2.36 seconds
Started Feb 09 06:29:12 AM UTC 25
Finished Feb 09 06:29:16 AM UTC 25
Peak memory 198828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432301071 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.432301071
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_rand_intr_trigger.1666955909
Short name T300
Test name
Test status
Simulation time 62504355 ps
CPU time 1.63 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:13 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666955909 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.1666955909
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_random_dout_din.730746817
Short name T301
Test name
Test status
Simulation time 501964753 ps
CPU time 1.83 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:13 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730746817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.gpio_random_dout_din.730746817
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2035673669
Short name T299
Test name
Test status
Simulation time 28023902 ps
CPU time 1.57 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:13 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035673669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup_pulldown.2035673669
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1236523542
Short name T319
Test name
Test status
Simulation time 4392015770 ps
CPU time 7.89 seconds
Started Feb 09 06:29:12 AM UTC 25
Finished Feb 09 06:29:21 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236523542 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_long_reg_writes_reg_reads.1236523542
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_smoke.3527694412
Short name T302
Test name
Test status
Simulation time 345230073 ps
CPU time 1.99 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:13 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527694412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.gpio_smoke.3527694412
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_smoke_no_pullup_pulldown.2196561293
Short name T297
Test name
Test status
Simulation time 41426467 ps
CPU time 1.52 seconds
Started Feb 09 06:29:10 AM UTC 25
Finished Feb 09 06:29:12 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196561293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2196561293
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_stress_all.2874557100
Short name T591
Test name
Test status
Simulation time 25110801825 ps
CPU time 186.21 seconds
Started Feb 09 06:29:12 AM UTC 25
Finished Feb 09 06:32:22 AM UTC 25
Peak memory 200852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874557100 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all.2874557100
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/19.gpio_stress_all_with_rand_reset.3886071063
Short name T714
Test name
Test status
Simulation time 410867150656 ps
CPU time 2437.13 seconds
Started Feb 09 06:29:14 AM UTC 25
Finished Feb 09 07:10:17 AM UTC 25
Peak memory 209884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3886071063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stres
s_all_with_rand_reset.3886071063
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_alert_test.1709994193
Short name T67
Test name
Test status
Simulation time 30007795 ps
CPU time 0.55 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:31 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709994193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1709994193
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_dout_din_regs_random_rw.3773150926
Short name T33
Test name
Test status
Simulation time 27103867 ps
CPU time 0.85 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:31 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773150926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3773150926
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_filter_stress.1985991486
Short name T149
Test name
Test status
Simulation time 133441440 ps
CPU time 3.84 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985991486 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress.1985991486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_full_random.2319873989
Short name T30
Test name
Test status
Simulation time 779630187 ps
CPU time 0.75 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:31 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319873989 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2319873989
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_intr_rand_pgm.1949209084
Short name T32
Test name
Test status
Simulation time 104860791 ps
CPU time 0.76 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:31 AM UTC 25
Peak memory 198452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949209084 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1949209084
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4036631807
Short name T135
Test name
Test status
Simulation time 97302444 ps
CPU time 1.91 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036631807 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4036631807
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_rand_intr_trigger.793589591
Short name T34
Test name
Test status
Simulation time 208684330 ps
CPU time 1.18 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793589591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.793589591
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_random_dout_din.1971081495
Short name T130
Test name
Test status
Simulation time 250530101 ps
CPU time 1.25 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971081495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.gpio_random_dout_din.1971081495
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.624369817
Short name T128
Test name
Test status
Simulation time 63910726 ps
CPU time 1.05 seconds
Started Feb 09 06:28:28 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624369817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_pulldown.624369817
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_random_long_reg_writes_reg_reads.360691581
Short name T23
Test name
Test status
Simulation time 265875218 ps
CPU time 4.06 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360691581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_long_reg_writes_reg_reads.360691581
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_sec_cm.346422312
Short name T37
Test name
Test status
Simulation time 382169298 ps
CPU time 0.91 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 235404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346422312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.346422312
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_smoke.98766203
Short name T78
Test name
Test status
Simulation time 237237730 ps
CPU time 0.87 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98766203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.gpio_smoke.98766203
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_smoke_no_pullup_pulldown.530721147
Short name T129
Test name
Test status
Simulation time 41405387 ps
CPU time 0.94 seconds
Started Feb 09 06:28:27 AM UTC 25
Finished Feb 09 06:28:30 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530721147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.530721147
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/2.gpio_stress_all.684307799
Short name T386
Test name
Test status
Simulation time 4071768059 ps
CPU time 92.25 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:30:04 AM UTC 25
Peak memory 200916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684307799 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all.684307799
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_alert_test.170257486
Short name T317
Test name
Test status
Simulation time 11743512 ps
CPU time 0.84 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:21 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170257486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.170257486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_dout_din_regs_random_rw.175446472
Short name T308
Test name
Test status
Simulation time 27069292 ps
CPU time 0.91 seconds
Started Feb 09 06:29:15 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175446472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.175446472
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_filter_stress.1445892704
Short name T357
Test name
Test status
Simulation time 4029642930 ps
CPU time 24.53 seconds
Started Feb 09 06:29:17 AM UTC 25
Finished Feb 09 06:29:43 AM UTC 25
Peak memory 198856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445892704 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stress.1445892704
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_full_random.630166347
Short name T6
Test name
Test status
Simulation time 908411684 ps
CPU time 1.34 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:21 AM UTC 25
Peak memory 198344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630166347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.630166347
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_intr_rand_pgm.1542521122
Short name T311
Test name
Test status
Simulation time 223863246 ps
CPU time 1.43 seconds
Started Feb 09 06:29:15 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542521122 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1542521122
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1368184251
Short name T325
Test name
Test status
Simulation time 331461938 ps
CPU time 5.11 seconds
Started Feb 09 06:29:17 AM UTC 25
Finished Feb 09 06:29:23 AM UTC 25
Peak memory 198836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368184251 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1368184251
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_rand_intr_trigger.308015348
Short name T314
Test name
Test status
Simulation time 57218489 ps
CPU time 2.46 seconds
Started Feb 09 06:29:15 AM UTC 25
Finished Feb 09 06:29:18 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308015348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.308015348
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_random_dout_din.1289440229
Short name T313
Test name
Test status
Simulation time 55251585 ps
CPU time 1.5 seconds
Started Feb 09 06:29:14 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289440229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.gpio_random_dout_din.1289440229
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2671311047
Short name T312
Test name
Test status
Simulation time 419711074 ps
CPU time 1.48 seconds
Started Feb 09 06:29:15 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671311047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup_pulldown.2671311047
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3346592747
Short name T324
Test name
Test status
Simulation time 154804703 ps
CPU time 2.42 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:22 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346592747 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_long_reg_writes_reg_reads.3346592747
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_smoke.1007113992
Short name T310
Test name
Test status
Simulation time 229745391 ps
CPU time 1.58 seconds
Started Feb 09 06:29:14 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007113992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.gpio_smoke.1007113992
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_smoke_no_pullup_pulldown.3615441572
Short name T309
Test name
Test status
Simulation time 47557052 ps
CPU time 1.37 seconds
Started Feb 09 06:29:14 AM UTC 25
Finished Feb 09 06:29:17 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615441572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3615441572
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/20.gpio_stress_all.3729154200
Short name T7
Test name
Test status
Simulation time 20161555488 ps
CPU time 51.19 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:30:12 AM UTC 25
Peak memory 200916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729154200 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all.3729154200
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_alert_test.3701113916
Short name T333
Test name
Test status
Simulation time 41505793 ps
CPU time 0.85 seconds
Started Feb 09 06:29:26 AM UTC 25
Finished Feb 09 06:29:28 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701113916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3701113916
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_dout_din_regs_random_rw.1624729467
Short name T327
Test name
Test status
Simulation time 25850431 ps
CPU time 1.08 seconds
Started Feb 09 06:29:23 AM UTC 25
Finished Feb 09 06:29:26 AM UTC 25
Peak memory 197848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624729467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1624729467
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_filter_stress.4141082720
Short name T315
Test name
Test status
Simulation time 724165436 ps
CPU time 28.03 seconds
Started Feb 09 06:29:23 AM UTC 25
Finished Feb 09 06:29:53 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141082720 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stress.4141082720
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_full_random.2498394165
Short name T328
Test name
Test status
Simulation time 57083635 ps
CPU time 1.12 seconds
Started Feb 09 06:29:24 AM UTC 25
Finished Feb 09 06:29:26 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498394165 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2498394165
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_intr_rand_pgm.3314920559
Short name T329
Test name
Test status
Simulation time 105506174 ps
CPU time 1.61 seconds
Started Feb 09 06:29:23 AM UTC 25
Finished Feb 09 06:29:27 AM UTC 25
Peak memory 197860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314920559 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3314920559
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3724398582
Short name T330
Test name
Test status
Simulation time 60073813 ps
CPU time 1.8 seconds
Started Feb 09 06:29:23 AM UTC 25
Finished Feb 09 06:29:27 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724398582 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3724398582
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_rand_intr_trigger.4291310240
Short name T331
Test name
Test status
Simulation time 139824689 ps
CPU time 2.06 seconds
Started Feb 09 06:29:23 AM UTC 25
Finished Feb 09 06:29:27 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291310240 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.4291310240
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_random_dout_din.113287474
Short name T318
Test name
Test status
Simulation time 87127326 ps
CPU time 0.93 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:21 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113287474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.gpio_random_dout_din.113287474
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.364737802
Short name T326
Test name
Test status
Simulation time 144620696 ps
CPU time 1.31 seconds
Started Feb 09 06:29:21 AM UTC 25
Finished Feb 09 06:29:24 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364737802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup_pulldown.364737802
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1823409383
Short name T334
Test name
Test status
Simulation time 753731632 ps
CPU time 3.55 seconds
Started Feb 09 06:29:24 AM UTC 25
Finished Feb 09 06:29:29 AM UTC 25
Peak memory 198660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823409383 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_long_reg_writes_reg_reads.1823409383
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_smoke.3566150563
Short name T323
Test name
Test status
Simulation time 49795381 ps
CPU time 1.96 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:22 AM UTC 25
Peak memory 198380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566150563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.gpio_smoke.3566150563
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_smoke_no_pullup_pulldown.2404232871
Short name T322
Test name
Test status
Simulation time 50264692 ps
CPU time 1.28 seconds
Started Feb 09 06:29:19 AM UTC 25
Finished Feb 09 06:29:22 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404232871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2404232871
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/21.gpio_stress_all.3632816018
Short name T610
Test name
Test status
Simulation time 24253016893 ps
CPU time 185.85 seconds
Started Feb 09 06:29:24 AM UTC 25
Finished Feb 09 06:32:33 AM UTC 25
Peak memory 200504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632816018 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all.3632816018
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_alert_test.1116844839
Short name T345
Test name
Test status
Simulation time 22245676 ps
CPU time 0.85 seconds
Started Feb 09 06:29:33 AM UTC 25
Finished Feb 09 06:29:36 AM UTC 25
Peak memory 198372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116844839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1116844839
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_dout_din_regs_random_rw.2394853057
Short name T339
Test name
Test status
Simulation time 17924434 ps
CPU time 0.95 seconds
Started Feb 09 06:29:29 AM UTC 25
Finished Feb 09 06:29:32 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394853057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2394853057
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_filter_stress.2629440351
Short name T366
Test name
Test status
Simulation time 439222343 ps
CPU time 16.42 seconds
Started Feb 09 06:29:31 AM UTC 25
Finished Feb 09 06:29:49 AM UTC 25
Peak memory 198800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629440351 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stress.2629440351
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_full_random.1534232450
Short name T344
Test name
Test status
Simulation time 39529556 ps
CPU time 1.15 seconds
Started Feb 09 06:29:31 AM UTC 25
Finished Feb 09 06:29:34 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534232450 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1534232450
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_intr_rand_pgm.3236428516
Short name T343
Test name
Test status
Simulation time 313898929 ps
CPU time 1.91 seconds
Started Feb 09 06:29:29 AM UTC 25
Finished Feb 09 06:29:33 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236428516 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3236428516
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1186261682
Short name T341
Test name
Test status
Simulation time 74715120 ps
CPU time 1.53 seconds
Started Feb 09 06:29:29 AM UTC 25
Finished Feb 09 06:29:32 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186261682 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1186261682
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_rand_intr_trigger.169050224
Short name T342
Test name
Test status
Simulation time 118888117 ps
CPU time 1.71 seconds
Started Feb 09 06:29:29 AM UTC 25
Finished Feb 09 06:29:32 AM UTC 25
Peak memory 197880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169050224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.169050224
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_random_dout_din.3959424407
Short name T337
Test name
Test status
Simulation time 52147542 ps
CPU time 1.48 seconds
Started Feb 09 06:29:27 AM UTC 25
Finished Feb 09 06:29:30 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959424407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.gpio_random_dout_din.3959424407
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3759437709
Short name T340
Test name
Test status
Simulation time 27188309 ps
CPU time 1.48 seconds
Started Feb 09 06:29:29 AM UTC 25
Finished Feb 09 06:29:32 AM UTC 25
Peak memory 197880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759437709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup_pulldown.3759437709
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_random_long_reg_writes_reg_reads.425671732
Short name T350
Test name
Test status
Simulation time 159102006 ps
CPU time 4.87 seconds
Started Feb 09 06:29:31 AM UTC 25
Finished Feb 09 06:29:37 AM UTC 25
Peak memory 198736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425671732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_long_reg_writes_reg_reads.425671732
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_smoke.1292635627
Short name T335
Test name
Test status
Simulation time 173623712 ps
CPU time 1.77 seconds
Started Feb 09 06:29:26 AM UTC 25
Finished Feb 09 06:29:29 AM UTC 25
Peak memory 198376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292635627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.gpio_smoke.1292635627
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_smoke_no_pullup_pulldown.999538278
Short name T336
Test name
Test status
Simulation time 143726988 ps
CPU time 1.47 seconds
Started Feb 09 06:29:27 AM UTC 25
Finished Feb 09 06:29:30 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999538278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.999538278
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_stress_all.674967424
Short name T621
Test name
Test status
Simulation time 13660875285 ps
CPU time 182.54 seconds
Started Feb 09 06:29:31 AM UTC 25
Finished Feb 09 06:32:37 AM UTC 25
Peak memory 200920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674967424 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all.674967424
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/22.gpio_stress_all_with_rand_reset.2137570686
Short name T82
Test name
Test status
Simulation time 133098165652 ps
CPU time 638.94 seconds
Started Feb 09 06:29:33 AM UTC 25
Finished Feb 09 06:40:20 AM UTC 25
Peak memory 206540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2137570686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stres
s_all_with_rand_reset.2137570686
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_alert_test.353293045
Short name T359
Test name
Test status
Simulation time 13649547 ps
CPU time 0.86 seconds
Started Feb 09 06:29:42 AM UTC 25
Finished Feb 09 06:29:45 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353293045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.353293045
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_dout_din_regs_random_rw.3288698646
Short name T351
Test name
Test status
Simulation time 53114935 ps
CPU time 1.06 seconds
Started Feb 09 06:29:36 AM UTC 25
Finished Feb 09 06:29:38 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288698646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3288698646
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_filter_stress.1641532074
Short name T363
Test name
Test status
Simulation time 697547443 ps
CPU time 13.61 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:53 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641532074 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress.1641532074
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_full_random.3585402049
Short name T354
Test name
Test status
Simulation time 46100083 ps
CPU time 1.12 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:40 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585402049 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3585402049
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_intr_rand_pgm.2740730909
Short name T353
Test name
Test status
Simulation time 128019178 ps
CPU time 1.17 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:40 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740730909 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2740730909
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1831091110
Short name T356
Test name
Test status
Simulation time 139630593 ps
CPU time 2.38 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:41 AM UTC 25
Peak memory 198824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831091110 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1831091110
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_rand_intr_trigger.1984557860
Short name T355
Test name
Test status
Simulation time 49335217 ps
CPU time 1.67 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:41 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984557860 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.1984557860
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_random_dout_din.3333498739
Short name T346
Test name
Test status
Simulation time 85634993 ps
CPU time 1.25 seconds
Started Feb 09 06:29:34 AM UTC 25
Finished Feb 09 06:29:36 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333498739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.gpio_random_dout_din.3333498739
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.53225363
Short name T348
Test name
Test status
Simulation time 51512573 ps
CPU time 1.46 seconds
Started Feb 09 06:29:34 AM UTC 25
Finished Feb 09 06:29:36 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53225363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup_pulldown.53225363
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_random_long_reg_writes_reg_reads.829722891
Short name T358
Test name
Test status
Simulation time 78253714 ps
CPU time 4.61 seconds
Started Feb 09 06:29:38 AM UTC 25
Finished Feb 09 06:29:44 AM UTC 25
Peak memory 198752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829722891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_long_reg_writes_reg_reads.829722891
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_smoke.3877317661
Short name T347
Test name
Test status
Simulation time 56828294 ps
CPU time 1.61 seconds
Started Feb 09 06:29:33 AM UTC 25
Finished Feb 09 06:29:36 AM UTC 25
Peak memory 198340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877317661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.gpio_smoke.3877317661
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_smoke_no_pullup_pulldown.2908688674
Short name T349
Test name
Test status
Simulation time 183948174 ps
CPU time 2.05 seconds
Started Feb 09 06:29:33 AM UTC 25
Finished Feb 09 06:29:37 AM UTC 25
Peak memory 198696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908688674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2908688674
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_stress_all.2521513986
Short name T447
Test name
Test status
Simulation time 4395397641 ps
CPU time 65.7 seconds
Started Feb 09 06:29:40 AM UTC 25
Finished Feb 09 06:30:48 AM UTC 25
Peak memory 200916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521513986 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all.2521513986
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/23.gpio_stress_all_with_rand_reset.2167393386
Short name T54
Test name
Test status
Simulation time 29643705338 ps
CPU time 282.42 seconds
Started Feb 09 06:29:40 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2167393386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stres
s_all_with_rand_reset.2167393386
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_alert_test.685108459
Short name T372
Test name
Test status
Simulation time 22152416 ps
CPU time 0.85 seconds
Started Feb 09 06:29:51 AM UTC 25
Finished Feb 09 06:29:53 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685108459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.685108459
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_dout_din_regs_random_rw.2744028026
Short name T364
Test name
Test status
Simulation time 86312399 ps
CPU time 1.03 seconds
Started Feb 09 06:29:44 AM UTC 25
Finished Feb 09 06:29:47 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744028026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2744028026
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_filter_stress.984113445
Short name T396
Test name
Test status
Simulation time 1204180345 ps
CPU time 22.76 seconds
Started Feb 09 06:29:46 AM UTC 25
Finished Feb 09 06:30:11 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984113445 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stress.984113445
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_full_random.1178442319
Short name T369
Test name
Test status
Simulation time 105270205 ps
CPU time 1.03 seconds
Started Feb 09 06:29:49 AM UTC 25
Finished Feb 09 06:29:51 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178442319 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1178442319
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_intr_rand_pgm.682554138
Short name T367
Test name
Test status
Simulation time 371758001 ps
CPU time 1.94 seconds
Started Feb 09 06:29:46 AM UTC 25
Finished Feb 09 06:29:50 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682554138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.682554138
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3196190735
Short name T368
Test name
Test status
Simulation time 607717286 ps
CPU time 2.5 seconds
Started Feb 09 06:29:46 AM UTC 25
Finished Feb 09 06:29:50 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196190735 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3196190735
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_rand_intr_trigger.2038418949
Short name T370
Test name
Test status
Simulation time 498216003 ps
CPU time 3.72 seconds
Started Feb 09 06:29:46 AM UTC 25
Finished Feb 09 06:29:52 AM UTC 25
Peak memory 198732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038418949 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.2038418949
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_random_dout_din.435638290
Short name T361
Test name
Test status
Simulation time 61857665 ps
CPU time 1.5 seconds
Started Feb 09 06:29:42 AM UTC 25
Finished Feb 09 06:29:45 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435638290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.gpio_random_dout_din.435638290
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.222193775
Short name T365
Test name
Test status
Simulation time 18487977 ps
CPU time 1.12 seconds
Started Feb 09 06:29:44 AM UTC 25
Finished Feb 09 06:29:47 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222193775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_pulldown.222193775
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1448539652
Short name T373
Test name
Test status
Simulation time 145614006 ps
CPU time 4.6 seconds
Started Feb 09 06:29:49 AM UTC 25
Finished Feb 09 06:29:54 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448539652 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_long_reg_writes_reg_reads.1448539652
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_smoke.2794866386
Short name T362
Test name
Test status
Simulation time 178601295 ps
CPU time 1.56 seconds
Started Feb 09 06:29:42 AM UTC 25
Finished Feb 09 06:29:45 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794866386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.gpio_smoke.2794866386
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_smoke_no_pullup_pulldown.519281475
Short name T360
Test name
Test status
Simulation time 424979800 ps
CPU time 1.21 seconds
Started Feb 09 06:29:42 AM UTC 25
Finished Feb 09 06:29:45 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519281475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.519281475
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/24.gpio_stress_all.3575058453
Short name T463
Test name
Test status
Simulation time 8520823136 ps
CPU time 67.54 seconds
Started Feb 09 06:29:49 AM UTC 25
Finished Feb 09 06:30:58 AM UTC 25
Peak memory 200816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575058453 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all.3575058453
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_alert_test.3978694400
Short name T383
Test name
Test status
Simulation time 33712353 ps
CPU time 0.83 seconds
Started Feb 09 06:29:59 AM UTC 25
Finished Feb 09 06:30:01 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978694400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3978694400
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_dout_din_regs_random_rw.2005571396
Short name T378
Test name
Test status
Simulation time 40297045 ps
CPU time 0.99 seconds
Started Feb 09 06:29:55 AM UTC 25
Finished Feb 09 06:29:57 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005571396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2005571396
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_filter_stress.11934503
Short name T395
Test name
Test status
Simulation time 240478821 ps
CPU time 11.9 seconds
Started Feb 09 06:29:57 AM UTC 25
Finished Feb 09 06:30:10 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11934503 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stress.11934503
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_full_random.2167732334
Short name T29
Test name
Test status
Simulation time 41693907 ps
CPU time 1.06 seconds
Started Feb 09 06:29:57 AM UTC 25
Finished Feb 09 06:29:59 AM UTC 25
Peak memory 198500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167732334 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2167732334
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_intr_rand_pgm.1613829188
Short name T379
Test name
Test status
Simulation time 38468683 ps
CPU time 1.29 seconds
Started Feb 09 06:29:55 AM UTC 25
Finished Feb 09 06:29:58 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613829188 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1613829188
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1582713486
Short name T382
Test name
Test status
Simulation time 161886442 ps
CPU time 4.45 seconds
Started Feb 09 06:29:55 AM UTC 25
Finished Feb 09 06:30:01 AM UTC 25
Peak memory 198896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582713486 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1582713486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_rand_intr_trigger.4053749411
Short name T380
Test name
Test status
Simulation time 33017610 ps
CPU time 1.59 seconds
Started Feb 09 06:29:55 AM UTC 25
Finished Feb 09 06:29:58 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053749411 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.4053749411
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_random_dout_din.3766350027
Short name T375
Test name
Test status
Simulation time 54651929 ps
CPU time 1.19 seconds
Started Feb 09 06:29:53 AM UTC 25
Finished Feb 09 06:29:55 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766350027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.gpio_random_dout_din.3766350027
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3224355993
Short name T376
Test name
Test status
Simulation time 40217850 ps
CPU time 1.32 seconds
Started Feb 09 06:29:53 AM UTC 25
Finished Feb 09 06:29:55 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224355993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_pulldown.3224355993
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1885380594
Short name T385
Test name
Test status
Simulation time 335233536 ps
CPU time 4.37 seconds
Started Feb 09 06:29:57 AM UTC 25
Finished Feb 09 06:30:03 AM UTC 25
Peak memory 198848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885380594 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_long_reg_writes_reg_reads.1885380594
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_smoke.328047093
Short name T377
Test name
Test status
Simulation time 195168043 ps
CPU time 1.82 seconds
Started Feb 09 06:29:53 AM UTC 25
Finished Feb 09 06:29:56 AM UTC 25
Peak memory 198348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328047093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 25.gpio_smoke.328047093
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_smoke_no_pullup_pulldown.1757839862
Short name T374
Test name
Test status
Simulation time 95477696 ps
CPU time 1.26 seconds
Started Feb 09 06:29:53 AM UTC 25
Finished Feb 09 06:29:55 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757839862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1757839862
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/25.gpio_stress_all.1126451235
Short name T515
Test name
Test status
Simulation time 18718400820 ps
CPU time 85.16 seconds
Started Feb 09 06:29:57 AM UTC 25
Finished Feb 09 06:31:25 AM UTC 25
Peak memory 200960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126451235 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all.1126451235
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_alert_test.2615652179
Short name T398
Test name
Test status
Simulation time 21474144 ps
CPU time 0.85 seconds
Started Feb 09 06:30:10 AM UTC 25
Finished Feb 09 06:30:12 AM UTC 25
Peak memory 198212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615652179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2615652179
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_dout_din_regs_random_rw.586644123
Short name T390
Test name
Test status
Simulation time 20574580 ps
CPU time 1.09 seconds
Started Feb 09 06:30:04 AM UTC 25
Finished Feb 09 06:30:06 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586644123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.586644123
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_filter_stress.3445512434
Short name T438
Test name
Test status
Simulation time 374371436 ps
CPU time 31.52 seconds
Started Feb 09 06:30:06 AM UTC 25
Finished Feb 09 06:30:39 AM UTC 25
Peak memory 198800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445512434 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stress.3445512434
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_full_random.2015557896
Short name T393
Test name
Test status
Simulation time 54798359 ps
CPU time 1.29 seconds
Started Feb 09 06:30:06 AM UTC 25
Finished Feb 09 06:30:09 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015557896 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2015557896
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_intr_rand_pgm.2107424398
Short name T391
Test name
Test status
Simulation time 129114769 ps
CPU time 1.61 seconds
Started Feb 09 06:30:04 AM UTC 25
Finished Feb 09 06:30:07 AM UTC 25
Peak memory 198376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107424398 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2107424398
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2356333258
Short name T397
Test name
Test status
Simulation time 263544800 ps
CPU time 4.15 seconds
Started Feb 09 06:30:06 AM UTC 25
Finished Feb 09 06:30:11 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356333258 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2356333258
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_rand_intr_trigger.277652077
Short name T394
Test name
Test status
Simulation time 326823646 ps
CPU time 4.54 seconds
Started Feb 09 06:30:04 AM UTC 25
Finished Feb 09 06:30:10 AM UTC 25
Peak memory 198656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277652077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.277652077
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_random_dout_din.1625513340
Short name T388
Test name
Test status
Simulation time 26887096 ps
CPU time 1.52 seconds
Started Feb 09 06:30:02 AM UTC 25
Finished Feb 09 06:30:04 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625513340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.gpio_random_dout_din.1625513340
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1024871308
Short name T389
Test name
Test status
Simulation time 291254645 ps
CPU time 1.94 seconds
Started Feb 09 06:30:02 AM UTC 25
Finished Feb 09 06:30:05 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024871308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup_pulldown.1024871308
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2253156583
Short name T399
Test name
Test status
Simulation time 213169272 ps
CPU time 5.15 seconds
Started Feb 09 06:30:06 AM UTC 25
Finished Feb 09 06:30:12 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253156583 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_long_reg_writes_reg_reads.2253156583
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_smoke.3673305059
Short name T384
Test name
Test status
Simulation time 48254583 ps
CPU time 1.55 seconds
Started Feb 09 06:29:59 AM UTC 25
Finished Feb 09 06:30:02 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673305059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.gpio_smoke.3673305059
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_smoke_no_pullup_pulldown.4043729624
Short name T387
Test name
Test status
Simulation time 47881923 ps
CPU time 1.42 seconds
Started Feb 09 06:30:02 AM UTC 25
Finished Feb 09 06:30:04 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043729624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4043729624
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_stress_all.1038084203
Short name T652
Test name
Test status
Simulation time 11493973269 ps
CPU time 166.08 seconds
Started Feb 09 06:30:08 AM UTC 25
Finished Feb 09 06:32:57 AM UTC 25
Peak memory 200912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038084203 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all.1038084203
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/26.gpio_stress_all_with_rand_reset.2229351529
Short name T707
Test name
Test status
Simulation time 175138144685 ps
CPU time 1024.99 seconds
Started Feb 09 06:30:08 AM UTC 25
Finished Feb 09 06:47:25 AM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2229351529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stres
s_all_with_rand_reset.2229351529
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_alert_test.1685320238
Short name T406
Test name
Test status
Simulation time 35746540 ps
CPU time 0.81 seconds
Started Feb 09 06:30:16 AM UTC 25
Finished Feb 09 06:30:18 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685320238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1685320238
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_dout_din_regs_random_rw.1779419106
Short name T402
Test name
Test status
Simulation time 63985043 ps
CPU time 1.07 seconds
Started Feb 09 06:30:13 AM UTC 25
Finished Feb 09 06:30:15 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779419106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1779419106
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_filter_stress.1179469706
Short name T422
Test name
Test status
Simulation time 358700182 ps
CPU time 12.05 seconds
Started Feb 09 06:30:15 AM UTC 25
Finished Feb 09 06:30:28 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179469706 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress.1179469706
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_full_random.831324750
Short name T408
Test name
Test status
Simulation time 50929386 ps
CPU time 1.32 seconds
Started Feb 09 06:30:16 AM UTC 25
Finished Feb 09 06:30:18 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831324750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.831324750
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_intr_rand_pgm.1729563134
Short name T404
Test name
Test status
Simulation time 70898806 ps
CPU time 0.99 seconds
Started Feb 09 06:30:13 AM UTC 25
Finished Feb 09 06:30:15 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729563134 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1729563134
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_intr_with_filter_rand_intr_event.165928179
Short name T407
Test name
Test status
Simulation time 533090539 ps
CPU time 2.33 seconds
Started Feb 09 06:30:15 AM UTC 25
Finished Feb 09 06:30:18 AM UTC 25
Peak memory 198580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165928179 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.165928179
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_rand_intr_trigger.3591965513
Short name T409
Test name
Test status
Simulation time 453282225 ps
CPU time 2.46 seconds
Started Feb 09 06:30:15 AM UTC 25
Finished Feb 09 06:30:18 AM UTC 25
Peak memory 198544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591965513 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.3591965513
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_random_dout_din.801367259
Short name T403
Test name
Test status
Simulation time 78878873 ps
CPU time 1.05 seconds
Started Feb 09 06:30:13 AM UTC 25
Finished Feb 09 06:30:15 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801367259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.gpio_random_dout_din.801367259
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4153123410
Short name T405
Test name
Test status
Simulation time 126890690 ps
CPU time 1.82 seconds
Started Feb 09 06:30:13 AM UTC 25
Finished Feb 09 06:30:16 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153123410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup_pulldown.4153123410
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2321377396
Short name T412
Test name
Test status
Simulation time 252924157 ps
CPU time 5.01 seconds
Started Feb 09 06:30:15 AM UTC 25
Finished Feb 09 06:30:21 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321377396 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_long_reg_writes_reg_reads.2321377396
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_smoke.3008935714
Short name T401
Test name
Test status
Simulation time 262924293 ps
CPU time 1.8 seconds
Started Feb 09 06:30:10 AM UTC 25
Finished Feb 09 06:30:13 AM UTC 25
Peak memory 198200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008935714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.gpio_smoke.3008935714
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_smoke_no_pullup_pulldown.320485115
Short name T400
Test name
Test status
Simulation time 187827041 ps
CPU time 1.52 seconds
Started Feb 09 06:30:10 AM UTC 25
Finished Feb 09 06:30:13 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320485115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.320485115
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_stress_all.2602600829
Short name T613
Test name
Test status
Simulation time 44104685336 ps
CPU time 134.97 seconds
Started Feb 09 06:30:16 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 200948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602600829 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all.2602600829
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/27.gpio_stress_all_with_rand_reset.194135023
Short name T711
Test name
Test status
Simulation time 82814384094 ps
CPU time 1465.57 seconds
Started Feb 09 06:30:16 AM UTC 25
Finished Feb 09 06:54:57 AM UTC 25
Peak memory 207968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=194135023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress
_all_with_rand_reset.194135023
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_alert_test.2965063850
Short name T421
Test name
Test status
Simulation time 10863056 ps
CPU time 0.75 seconds
Started Feb 09 06:30:26 AM UTC 25
Finished Feb 09 06:30:28 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965063850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2965063850
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_dout_din_regs_random_rw.4201213498
Short name T415
Test name
Test status
Simulation time 78942904 ps
CPU time 1.28 seconds
Started Feb 09 06:30:19 AM UTC 25
Finished Feb 09 06:30:22 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201213498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4201213498
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_filter_stress.2756895324
Short name T434
Test name
Test status
Simulation time 964195109 ps
CPU time 13.78 seconds
Started Feb 09 06:30:22 AM UTC 25
Finished Feb 09 06:30:38 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756895324 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress.2756895324
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_full_random.840848792
Short name T8
Test name
Test status
Simulation time 91955513 ps
CPU time 1.15 seconds
Started Feb 09 06:30:23 AM UTC 25
Finished Feb 09 06:30:25 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840848792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.840848792
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_intr_rand_pgm.284201880
Short name T417
Test name
Test status
Simulation time 379900609 ps
CPU time 1.99 seconds
Started Feb 09 06:30:19 AM UTC 25
Finished Feb 09 06:30:22 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284201880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.284201880
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2896298261
Short name T419
Test name
Test status
Simulation time 156927813 ps
CPU time 2.22 seconds
Started Feb 09 06:30:22 AM UTC 25
Finished Feb 09 06:30:26 AM UTC 25
Peak memory 198680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896298261 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2896298261
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_rand_intr_trigger.3937654952
Short name T420
Test name
Test status
Simulation time 511514028 ps
CPU time 4.03 seconds
Started Feb 09 06:30:21 AM UTC 25
Finished Feb 09 06:30:27 AM UTC 25
Peak memory 198732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937654952 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.3937654952
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_random_dout_din.3226506317
Short name T416
Test name
Test status
Simulation time 40035985 ps
CPU time 1.46 seconds
Started Feb 09 06:30:19 AM UTC 25
Finished Feb 09 06:30:22 AM UTC 25
Peak memory 198080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226506317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.gpio_random_dout_din.3226506317
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1199764653
Short name T413
Test name
Test status
Simulation time 22497898 ps
CPU time 1.01 seconds
Started Feb 09 06:30:19 AM UTC 25
Finished Feb 09 06:30:21 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199764653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup_pulldown.1199764653
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1543788738
Short name T423
Test name
Test status
Simulation time 167691070 ps
CPU time 5.16 seconds
Started Feb 09 06:30:22 AM UTC 25
Finished Feb 09 06:30:29 AM UTC 25
Peak memory 198848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543788738 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_long_reg_writes_reg_reads.1543788738
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_smoke.638441374
Short name T410
Test name
Test status
Simulation time 54366452 ps
CPU time 1.2 seconds
Started Feb 09 06:30:16 AM UTC 25
Finished Feb 09 06:30:18 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638441374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 28.gpio_smoke.638441374
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_smoke_no_pullup_pulldown.684719285
Short name T414
Test name
Test status
Simulation time 22547954 ps
CPU time 1.13 seconds
Started Feb 09 06:30:19 AM UTC 25
Finished Feb 09 06:30:21 AM UTC 25
Peak memory 197952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684719285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.684719285
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_stress_all.3480240932
Short name T494
Test name
Test status
Simulation time 5717815583 ps
CPU time 47.39 seconds
Started Feb 09 06:30:24 AM UTC 25
Finished Feb 09 06:31:13 AM UTC 25
Peak memory 200956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480240932 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all.3480240932
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/28.gpio_stress_all_with_rand_reset.2379880133
Short name T53
Test name
Test status
Simulation time 21417794609 ps
CPU time 209.02 seconds
Started Feb 09 06:30:26 AM UTC 25
Finished Feb 09 06:33:58 AM UTC 25
Peak memory 206504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2379880133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stres
s_all_with_rand_reset.2379880133
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_alert_test.2193260523
Short name T433
Test name
Test status
Simulation time 49224719 ps
CPU time 0.88 seconds
Started Feb 09 06:30:34 AM UTC 25
Finished Feb 09 06:30:36 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193260523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2193260523
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_dout_din_regs_random_rw.3354771675
Short name T428
Test name
Test status
Simulation time 64554522 ps
CPU time 1.34 seconds
Started Feb 09 06:30:29 AM UTC 25
Finished Feb 09 06:30:32 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354771675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3354771675
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_filter_stress.1263006522
Short name T460
Test name
Test status
Simulation time 2570224456 ps
CPU time 24.32 seconds
Started Feb 09 06:30:31 AM UTC 25
Finished Feb 09 06:30:57 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263006522 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress.1263006522
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_full_random.2514011783
Short name T431
Test name
Test status
Simulation time 56965105 ps
CPU time 1.29 seconds
Started Feb 09 06:30:32 AM UTC 25
Finished Feb 09 06:30:35 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514011783 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2514011783
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_intr_rand_pgm.4053683673
Short name T429
Test name
Test status
Simulation time 52392797 ps
CPU time 1.89 seconds
Started Feb 09 06:30:29 AM UTC 25
Finished Feb 09 06:30:32 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053683673 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4053683673
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2333103590
Short name T432
Test name
Test status
Simulation time 61407698 ps
CPU time 3.56 seconds
Started Feb 09 06:30:30 AM UTC 25
Finished Feb 09 06:30:35 AM UTC 25
Peak memory 200720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333103590 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2333103590
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_rand_intr_trigger.238539341
Short name T430
Test name
Test status
Simulation time 36875989 ps
CPU time 1.82 seconds
Started Feb 09 06:30:30 AM UTC 25
Finished Feb 09 06:30:33 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238539341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.238539341
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_random_dout_din.408462977
Short name T427
Test name
Test status
Simulation time 108718527 ps
CPU time 1.72 seconds
Started Feb 09 06:30:28 AM UTC 25
Finished Feb 09 06:30:31 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408462977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.gpio_random_dout_din.408462977
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3642719051
Short name T426
Test name
Test status
Simulation time 87882253 ps
CPU time 1.07 seconds
Started Feb 09 06:30:28 AM UTC 25
Finished Feb 09 06:30:30 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642719051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup_pulldown.3642719051
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_random_long_reg_writes_reg_reads.166708341
Short name T440
Test name
Test status
Simulation time 433254890 ps
CPU time 7.69 seconds
Started Feb 09 06:30:32 AM UTC 25
Finished Feb 09 06:30:41 AM UTC 25
Peak memory 198604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166708341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_long_reg_writes_reg_reads.166708341
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_smoke.3901610490
Short name T425
Test name
Test status
Simulation time 110288250 ps
CPU time 1.39 seconds
Started Feb 09 06:30:27 AM UTC 25
Finished Feb 09 06:30:29 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901610490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.gpio_smoke.3901610490
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_smoke_no_pullup_pulldown.80261611
Short name T424
Test name
Test status
Simulation time 189371643 ps
CPU time 1.17 seconds
Started Feb 09 06:30:27 AM UTC 25
Finished Feb 09 06:30:29 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80261611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.80261611
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/29.gpio_stress_all.1794900307
Short name T701
Test name
Test status
Simulation time 76487305272 ps
CPU time 264.68 seconds
Started Feb 09 06:30:33 AM UTC 25
Finished Feb 09 06:35:01 AM UTC 25
Peak memory 200920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794900307 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all.1794900307
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_alert_test.1770073918
Short name T137
Test name
Test status
Simulation time 14670786 ps
CPU time 0.54 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770073918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1770073918
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_dout_din_regs_random_rw.4101148597
Short name T35
Test name
Test status
Simulation time 16084711 ps
CPU time 0.72 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101148597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4101148597
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_filter_stress.2459251352
Short name T28
Test name
Test status
Simulation time 914437038 ps
CPU time 3.87 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459251352 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress.2459251352
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_full_random.1529132472
Short name T139
Test name
Test status
Simulation time 155738432 ps
CPU time 0.89 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529132472 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1529132472
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_intr_rand_pgm.2357591514
Short name T136
Test name
Test status
Simulation time 98729890 ps
CPU time 1.43 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357591514 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2357591514
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2926405520
Short name T127
Test name
Test status
Simulation time 225866290 ps
CPU time 1.19 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926405520 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2926405520
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_rand_intr_trigger.1917516482
Short name T146
Test name
Test status
Simulation time 282007936 ps
CPU time 2.9 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:34 AM UTC 25
Peak memory 198660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917516482 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.1917516482
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_random_dout_din.2825116066
Short name T39
Test name
Test status
Simulation time 45141504 ps
CPU time 0.9 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825116066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.gpio_random_dout_din.2825116066
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1015724603
Short name T38
Test name
Test status
Simulation time 489073157 ps
CPU time 1.13 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015724603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_pulldown.1015724603
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_sec_cm.36587967
Short name T76
Test name
Test status
Simulation time 271156254 ps
CPU time 0.77 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 235340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36587967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.36587967
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_smoke.299803474
Short name T138
Test name
Test status
Simulation time 204283163 ps
CPU time 1.6 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299803474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.gpio_smoke.299803474
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_smoke_no_pullup_pulldown.3816221549
Short name T131
Test name
Test status
Simulation time 55747050 ps
CPU time 1.19 seconds
Started Feb 09 06:28:29 AM UTC 25
Finished Feb 09 06:28:32 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816221549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3816221549
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/3.gpio_stress_all.3197724310
Short name T474
Test name
Test status
Simulation time 26949779674 ps
CPU time 150.36 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:31:04 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197724310 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all.3197724310
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_alert_test.776279501
Short name T446
Test name
Test status
Simulation time 24272412 ps
CPU time 0.86 seconds
Started Feb 09 06:30:45 AM UTC 25
Finished Feb 09 06:30:47 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776279501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.776279501
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_dout_din_regs_random_rw.175256128
Short name T439
Test name
Test status
Simulation time 288797589 ps
CPU time 1.19 seconds
Started Feb 09 06:30:39 AM UTC 25
Finished Feb 09 06:30:41 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175256128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.175256128
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_filter_stress.1479146902
Short name T478
Test name
Test status
Simulation time 890149651 ps
CPU time 21.88 seconds
Started Feb 09 06:30:42 AM UTC 25
Finished Feb 09 06:31:06 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479146902 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress.1479146902
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_full_random.1545465246
Short name T411
Test name
Test status
Simulation time 131827872 ps
CPU time 1.39 seconds
Started Feb 09 06:30:43 AM UTC 25
Finished Feb 09 06:30:46 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545465246 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1545465246
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_intr_rand_pgm.1081413993
Short name T442
Test name
Test status
Simulation time 260932116 ps
CPU time 1.2 seconds
Started Feb 09 06:30:40 AM UTC 25
Finished Feb 09 06:30:42 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081413993 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1081413993
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2607714565
Short name T444
Test name
Test status
Simulation time 61227526 ps
CPU time 3.03 seconds
Started Feb 09 06:30:40 AM UTC 25
Finished Feb 09 06:30:44 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607714565 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2607714565
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_rand_intr_trigger.2243618640
Short name T443
Test name
Test status
Simulation time 25188168 ps
CPU time 1.38 seconds
Started Feb 09 06:30:40 AM UTC 25
Finished Feb 09 06:30:43 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243618640 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.2243618640
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_random_dout_din.3734215730
Short name T437
Test name
Test status
Simulation time 22294999 ps
CPU time 1.1 seconds
Started Feb 09 06:30:37 AM UTC 25
Finished Feb 09 06:30:39 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734215730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.gpio_random_dout_din.3734215730
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1564328576
Short name T441
Test name
Test status
Simulation time 306434837 ps
CPU time 1.78 seconds
Started Feb 09 06:30:39 AM UTC 25
Finished Feb 09 06:30:42 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564328576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup_pulldown.1564328576
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3814150808
Short name T448
Test name
Test status
Simulation time 138478558 ps
CPU time 5.47 seconds
Started Feb 09 06:30:42 AM UTC 25
Finished Feb 09 06:30:49 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814150808 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_long_reg_writes_reg_reads.3814150808
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_smoke.718352655
Short name T436
Test name
Test status
Simulation time 143427136 ps
CPU time 1.97 seconds
Started Feb 09 06:30:36 AM UTC 25
Finished Feb 09 06:30:39 AM UTC 25
Peak memory 198108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718352655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 30.gpio_smoke.718352655
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_smoke_no_pullup_pulldown.1058199132
Short name T435
Test name
Test status
Simulation time 24443166 ps
CPU time 1.16 seconds
Started Feb 09 06:30:36 AM UTC 25
Finished Feb 09 06:30:38 AM UTC 25
Peak memory 198148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058199132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1058199132
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/30.gpio_stress_all.3995090047
Short name T482
Test name
Test status
Simulation time 8937944166 ps
CPU time 22.83 seconds
Started Feb 09 06:30:43 AM UTC 25
Finished Feb 09 06:31:08 AM UTC 25
Peak memory 200992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995090047 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all.3995090047
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_alert_test.4018893593
Short name T464
Test name
Test status
Simulation time 46856579 ps
CPU time 0.85 seconds
Started Feb 09 06:30:56 AM UTC 25
Finished Feb 09 06:30:58 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018893593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4018893593
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_dout_din_regs_random_rw.3863795068
Short name T454
Test name
Test status
Simulation time 197049042 ps
CPU time 1.41 seconds
Started Feb 09 06:30:50 AM UTC 25
Finished Feb 09 06:30:52 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863795068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3863795068
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_filter_stress.2362384422
Short name T512
Test name
Test status
Simulation time 592700652 ps
CPU time 29.4 seconds
Started Feb 09 06:30:52 AM UTC 25
Finished Feb 09 06:31:23 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362384422 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stress.2362384422
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_full_random.3973486367
Short name T459
Test name
Test status
Simulation time 231294035 ps
CPU time 1.3 seconds
Started Feb 09 06:30:53 AM UTC 25
Finished Feb 09 06:30:55 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973486367 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3973486367
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_intr_rand_pgm.3931437466
Short name T455
Test name
Test status
Simulation time 122630603 ps
CPU time 1.5 seconds
Started Feb 09 06:30:51 AM UTC 25
Finished Feb 09 06:30:53 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931437466 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3931437466
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3421860818
Short name T456
Test name
Test status
Simulation time 29428213 ps
CPU time 1.79 seconds
Started Feb 09 06:30:52 AM UTC 25
Finished Feb 09 06:30:55 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421860818 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3421860818
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_rand_intr_trigger.2351243262
Short name T462
Test name
Test status
Simulation time 141499347 ps
CPU time 4.39 seconds
Started Feb 09 06:30:52 AM UTC 25
Finished Feb 09 06:30:57 AM UTC 25
Peak memory 198704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351243262 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.2351243262
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_random_dout_din.868652478
Short name T450
Test name
Test status
Simulation time 20065108 ps
CPU time 1.09 seconds
Started Feb 09 06:30:49 AM UTC 25
Finished Feb 09 06:30:51 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868652478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.gpio_random_dout_din.868652478
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1710709090
Short name T451
Test name
Test status
Simulation time 156862814 ps
CPU time 1.37 seconds
Started Feb 09 06:30:49 AM UTC 25
Finished Feb 09 06:30:51 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710709090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_pulldown.1710709090
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3617786371
Short name T19
Test name
Test status
Simulation time 1079366193 ps
CPU time 4.19 seconds
Started Feb 09 06:30:53 AM UTC 25
Finished Feb 09 06:30:58 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617786371 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_long_reg_writes_reg_reads.3617786371
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_smoke.1205201519
Short name T449
Test name
Test status
Simulation time 75887159 ps
CPU time 1.85 seconds
Started Feb 09 06:30:46 AM UTC 25
Finished Feb 09 06:30:49 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205201519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.gpio_smoke.1205201519
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_smoke_no_pullup_pulldown.1061711079
Short name T452
Test name
Test status
Simulation time 215547849 ps
CPU time 1.74 seconds
Started Feb 09 06:30:47 AM UTC 25
Finished Feb 09 06:30:51 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061711079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1061711079
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/31.gpio_stress_all.878892783
Short name T582
Test name
Test status
Simulation time 76888158519 ps
CPU time 78.33 seconds
Started Feb 09 06:30:54 AM UTC 25
Finished Feb 09 06:32:14 AM UTC 25
Peak memory 200832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878892783 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all.878892783
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_alert_test.1463489076
Short name T475
Test name
Test status
Simulation time 119546441 ps
CPU time 0.82 seconds
Started Feb 09 06:31:02 AM UTC 25
Finished Feb 09 06:31:04 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463489076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1463489076
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_dout_din_regs_random_rw.3176015233
Short name T470
Test name
Test status
Simulation time 52049714 ps
CPU time 1.07 seconds
Started Feb 09 06:30:59 AM UTC 25
Finished Feb 09 06:31:01 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176015233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3176015233
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_filter_stress.2500135077
Short name T524
Test name
Test status
Simulation time 8131586225 ps
CPU time 27.48 seconds
Started Feb 09 06:31:00 AM UTC 25
Finished Feb 09 06:31:30 AM UTC 25
Peak memory 200908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500135077 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stress.2500135077
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_full_random.1771507000
Short name T472
Test name
Test status
Simulation time 75472247 ps
CPU time 1.42 seconds
Started Feb 09 06:31:00 AM UTC 25
Finished Feb 09 06:31:03 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771507000 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1771507000
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_intr_rand_pgm.446257559
Short name T469
Test name
Test status
Simulation time 19970316 ps
CPU time 0.97 seconds
Started Feb 09 06:30:59 AM UTC 25
Finished Feb 09 06:31:01 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446257559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.446257559
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4248013118
Short name T480
Test name
Test status
Simulation time 173456862 ps
CPU time 4.93 seconds
Started Feb 09 06:31:00 AM UTC 25
Finished Feb 09 06:31:06 AM UTC 25
Peak memory 200944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248013118 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4248013118
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_rand_intr_trigger.228280119
Short name T473
Test name
Test status
Simulation time 1177191410 ps
CPU time 2.74 seconds
Started Feb 09 06:31:00 AM UTC 25
Finished Feb 09 06:31:04 AM UTC 25
Peak memory 198656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228280119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.228280119
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_random_dout_din.3106495854
Short name T468
Test name
Test status
Simulation time 63570966 ps
CPU time 1.54 seconds
Started Feb 09 06:30:57 AM UTC 25
Finished Feb 09 06:31:00 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106495854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.gpio_random_dout_din.3106495854
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2130015342
Short name T471
Test name
Test status
Simulation time 178241917 ps
CPU time 1.51 seconds
Started Feb 09 06:30:59 AM UTC 25
Finished Feb 09 06:31:01 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130015342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup_pulldown.2130015342
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2906961107
Short name T484
Test name
Test status
Simulation time 545313747 ps
CPU time 6.42 seconds
Started Feb 09 06:31:00 AM UTC 25
Finished Feb 09 06:31:08 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906961107 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_long_reg_writes_reg_reads.2906961107
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_smoke.3333949944
Short name T465
Test name
Test status
Simulation time 58742814 ps
CPU time 1.39 seconds
Started Feb 09 06:30:56 AM UTC 25
Finished Feb 09 06:30:59 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333949944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.gpio_smoke.3333949944
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_smoke_no_pullup_pulldown.1394802007
Short name T467
Test name
Test status
Simulation time 69021121 ps
CPU time 2 seconds
Started Feb 09 06:30:56 AM UTC 25
Finished Feb 09 06:31:00 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394802007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1394802007
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/32.gpio_stress_all.1977462756
Short name T700
Test name
Test status
Simulation time 15648855859 ps
CPU time 219.98 seconds
Started Feb 09 06:31:01 AM UTC 25
Finished Feb 09 06:34:45 AM UTC 25
Peak memory 200780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977462756 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all.1977462756
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_alert_test.3558468486
Short name T489
Test name
Test status
Simulation time 30201342 ps
CPU time 0.82 seconds
Started Feb 09 06:31:09 AM UTC 25
Finished Feb 09 06:31:11 AM UTC 25
Peak memory 198116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558468486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3558468486
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_dout_din_regs_random_rw.539111371
Short name T486
Test name
Test status
Simulation time 52741264 ps
CPU time 1.09 seconds
Started Feb 09 06:31:06 AM UTC 25
Finished Feb 09 06:31:08 AM UTC 25
Peak memory 198452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539111371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.539111371
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_filter_stress.2275927306
Short name T476
Test name
Test status
Simulation time 1983368176 ps
CPU time 19.11 seconds
Started Feb 09 06:31:07 AM UTC 25
Finished Feb 09 06:31:27 AM UTC 25
Peak memory 198804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275927306 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stress.2275927306
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_full_random.1175974509
Short name T488
Test name
Test status
Simulation time 686061454 ps
CPU time 1.22 seconds
Started Feb 09 06:31:08 AM UTC 25
Finished Feb 09 06:31:10 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175974509 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1175974509
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_intr_rand_pgm.1742697732
Short name T483
Test name
Test status
Simulation time 19960284 ps
CPU time 0.89 seconds
Started Feb 09 06:31:06 AM UTC 25
Finished Feb 09 06:31:08 AM UTC 25
Peak memory 198452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742697732 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1742697732
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_intr_with_filter_rand_intr_event.362069383
Short name T491
Test name
Test status
Simulation time 301768448 ps
CPU time 3.36 seconds
Started Feb 09 06:31:07 AM UTC 25
Finished Feb 09 06:31:11 AM UTC 25
Peak memory 200960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362069383 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.362069383
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_rand_intr_trigger.3464131058
Short name T487
Test name
Test status
Simulation time 52573333 ps
CPU time 2.35 seconds
Started Feb 09 06:31:06 AM UTC 25
Finished Feb 09 06:31:09 AM UTC 25
Peak memory 198768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464131058 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.3464131058
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_random_dout_din.2799901615
Short name T481
Test name
Test status
Simulation time 268554129 ps
CPU time 1.38 seconds
Started Feb 09 06:31:04 AM UTC 25
Finished Feb 09 06:31:07 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799901615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.gpio_random_dout_din.2799901615
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.383331529
Short name T485
Test name
Test status
Simulation time 20078155 ps
CPU time 1 seconds
Started Feb 09 06:31:06 AM UTC 25
Finished Feb 09 06:31:08 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383331529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_pulldown.383331529
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2453318131
Short name T490
Test name
Test status
Simulation time 51052643 ps
CPU time 3.29 seconds
Started Feb 09 06:31:07 AM UTC 25
Finished Feb 09 06:31:11 AM UTC 25
Peak memory 198600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453318131 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_long_reg_writes_reg_reads.2453318131
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_smoke.267566466
Short name T477
Test name
Test status
Simulation time 106327328 ps
CPU time 1.54 seconds
Started Feb 09 06:31:02 AM UTC 25
Finished Feb 09 06:31:05 AM UTC 25
Peak memory 198328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267566466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.gpio_smoke.267566466
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_smoke_no_pullup_pulldown.1512189813
Short name T479
Test name
Test status
Simulation time 40597079 ps
CPU time 1.23 seconds
Started Feb 09 06:31:03 AM UTC 25
Finished Feb 09 06:31:06 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512189813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1512189813
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/33.gpio_stress_all.781201660
Short name T697
Test name
Test status
Simulation time 54512012009 ps
CPU time 196.01 seconds
Started Feb 09 06:31:08 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 200776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781201660 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all.781201660
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_alert_test.3527440170
Short name T503
Test name
Test status
Simulation time 26345889 ps
CPU time 0.86 seconds
Started Feb 09 06:31:16 AM UTC 25
Finished Feb 09 06:31:18 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527440170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3527440170
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_dout_din_regs_random_rw.3828793508
Short name T498
Test name
Test status
Simulation time 20954380 ps
CPU time 1.11 seconds
Started Feb 09 06:31:12 AM UTC 25
Finished Feb 09 06:31:15 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828793508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3828793508
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_filter_stress.3292017161
Short name T551
Test name
Test status
Simulation time 2032230941 ps
CPU time 32.67 seconds
Started Feb 09 06:31:14 AM UTC 25
Finished Feb 09 06:31:48 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292017161 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stress.3292017161
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_full_random.3665280297
Short name T502
Test name
Test status
Simulation time 69324180 ps
CPU time 1.36 seconds
Started Feb 09 06:31:15 AM UTC 25
Finished Feb 09 06:31:17 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665280297 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3665280297
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_intr_rand_pgm.2281702319
Short name T499
Test name
Test status
Simulation time 124157323 ps
CPU time 1.33 seconds
Started Feb 09 06:31:12 AM UTC 25
Finished Feb 09 06:31:15 AM UTC 25
Peak memory 198228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281702319 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2281702319
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1720666725
Short name T500
Test name
Test status
Simulation time 200806019 ps
CPU time 1.36 seconds
Started Feb 09 06:31:12 AM UTC 25
Finished Feb 09 06:31:15 AM UTC 25
Peak memory 198436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720666725 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1720666725
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_rand_intr_trigger.1116837831
Short name T501
Test name
Test status
Simulation time 53071400 ps
CPU time 2.36 seconds
Started Feb 09 06:31:12 AM UTC 25
Finished Feb 09 06:31:16 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116837831 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.1116837831
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_random_dout_din.916072788
Short name T495
Test name
Test status
Simulation time 62752515 ps
CPU time 1.63 seconds
Started Feb 09 06:31:10 AM UTC 25
Finished Feb 09 06:31:14 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916072788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.gpio_random_dout_din.916072788
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2885379407
Short name T497
Test name
Test status
Simulation time 628040917 ps
CPU time 1.78 seconds
Started Feb 09 06:31:11 AM UTC 25
Finished Feb 09 06:31:14 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885379407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup_pulldown.2885379407
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1795918153
Short name T509
Test name
Test status
Simulation time 1487172601 ps
CPU time 5.47 seconds
Started Feb 09 06:31:14 AM UTC 25
Finished Feb 09 06:31:20 AM UTC 25
Peak memory 198812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795918153 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_long_reg_writes_reg_reads.1795918153
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_smoke.1051797080
Short name T493
Test name
Test status
Simulation time 82173403 ps
CPU time 2.2 seconds
Started Feb 09 06:31:09 AM UTC 25
Finished Feb 09 06:31:13 AM UTC 25
Peak memory 198676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051797080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.gpio_smoke.1051797080
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_smoke_no_pullup_pulldown.3499800472
Short name T492
Test name
Test status
Simulation time 279929590 ps
CPU time 1.36 seconds
Started Feb 09 06:31:09 AM UTC 25
Finished Feb 09 06:31:12 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499800472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3499800472
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_stress_all.2964169219
Short name T643
Test name
Test status
Simulation time 9902927735 ps
CPU time 94.59 seconds
Started Feb 09 06:31:15 AM UTC 25
Finished Feb 09 06:32:52 AM UTC 25
Peak memory 200780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964169219 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all.2964169219
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/34.gpio_stress_all_with_rand_reset.969268249
Short name T706
Test name
Test status
Simulation time 31252036953 ps
CPU time 802.11 seconds
Started Feb 09 06:31:16 AM UTC 25
Finished Feb 09 06:44:48 AM UTC 25
Peak memory 206668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=969268249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress
_all_with_rand_reset.969268249
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_alert_test.3582619045
Short name T516
Test name
Test status
Simulation time 38404948 ps
CPU time 0.84 seconds
Started Feb 09 06:31:23 AM UTC 25
Finished Feb 09 06:31:25 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582619045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3582619045
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_dout_din_regs_random_rw.292715202
Short name T510
Test name
Test status
Simulation time 22432659 ps
CPU time 1.08 seconds
Started Feb 09 06:31:19 AM UTC 25
Finished Feb 09 06:31:21 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292715202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.292715202
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_filter_stress.1926959621
Short name T536
Test name
Test status
Simulation time 1580878778 ps
CPU time 13.94 seconds
Started Feb 09 06:31:21 AM UTC 25
Finished Feb 09 06:31:37 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926959621 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress.1926959621
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_full_random.806866042
Short name T513
Test name
Test status
Simulation time 221705754 ps
CPU time 1.45 seconds
Started Feb 09 06:31:21 AM UTC 25
Finished Feb 09 06:31:24 AM UTC 25
Peak memory 198348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806866042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.806866042
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_intr_rand_pgm.2297013781
Short name T511
Test name
Test status
Simulation time 164509849 ps
CPU time 1.57 seconds
Started Feb 09 06:31:19 AM UTC 25
Finished Feb 09 06:31:22 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297013781 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2297013781
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_intr_with_filter_rand_intr_event.733273906
Short name T457
Test name
Test status
Simulation time 315545772 ps
CPU time 3.99 seconds
Started Feb 09 06:31:20 AM UTC 25
Finished Feb 09 06:31:25 AM UTC 25
Peak memory 198828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733273906 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.733273906
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_rand_intr_trigger.2442654384
Short name T514
Test name
Test status
Simulation time 159831977 ps
CPU time 2.96 seconds
Started Feb 09 06:31:20 AM UTC 25
Finished Feb 09 06:31:24 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442654384 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.2442654384
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_random_dout_din.4094665214
Short name T505
Test name
Test status
Simulation time 67323301 ps
CPU time 1.12 seconds
Started Feb 09 06:31:17 AM UTC 25
Finished Feb 09 06:31:19 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094665214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 35.gpio_random_dout_din.4094665214
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2696554009
Short name T508
Test name
Test status
Simulation time 44776822 ps
CPU time 0.96 seconds
Started Feb 09 06:31:18 AM UTC 25
Finished Feb 09 06:31:20 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696554009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup_pulldown.2696554009
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2300765872
Short name T518
Test name
Test status
Simulation time 116277335 ps
CPU time 3.08 seconds
Started Feb 09 06:31:21 AM UTC 25
Finished Feb 09 06:31:26 AM UTC 25
Peak memory 198604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300765872 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_long_reg_writes_reg_reads.2300765872
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_smoke.2924642919
Short name T504
Test name
Test status
Simulation time 196116488 ps
CPU time 1.51 seconds
Started Feb 09 06:31:16 AM UTC 25
Finished Feb 09 06:31:18 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924642919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.gpio_smoke.2924642919
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_smoke_no_pullup_pulldown.1822155854
Short name T507
Test name
Test status
Simulation time 37186937 ps
CPU time 1.79 seconds
Started Feb 09 06:31:17 AM UTC 25
Finished Feb 09 06:31:20 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822155854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1822155854
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/35.gpio_stress_all.2128379858
Short name T696
Test name
Test status
Simulation time 46749840438 ps
CPU time 181.26 seconds
Started Feb 09 06:31:23 AM UTC 25
Finished Feb 09 06:34:27 AM UTC 25
Peak memory 200776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128379858 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all.2128379858
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_alert_test.3105355821
Short name T526
Test name
Test status
Simulation time 42035568 ps
CPU time 0.82 seconds
Started Feb 09 06:31:30 AM UTC 25
Finished Feb 09 06:31:31 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105355821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3105355821
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_dout_din_regs_random_rw.1970815549
Short name T522
Test name
Test status
Simulation time 48999433 ps
CPU time 1.38 seconds
Started Feb 09 06:31:26 AM UTC 25
Finished Feb 09 06:31:29 AM UTC 25
Peak memory 198316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970815549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1970815549
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_filter_stress.129010789
Short name T564
Test name
Test status
Simulation time 7127637578 ps
CPU time 28.36 seconds
Started Feb 09 06:31:27 AM UTC 25
Finished Feb 09 06:31:57 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129010789 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stress.129010789
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_full_random.446253380
Short name T525
Test name
Test status
Simulation time 98571637 ps
CPU time 1.24 seconds
Started Feb 09 06:31:28 AM UTC 25
Finished Feb 09 06:31:31 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446253380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.446253380
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_intr_rand_pgm.3233813782
Short name T520
Test name
Test status
Simulation time 32270646 ps
CPU time 1.11 seconds
Started Feb 09 06:31:26 AM UTC 25
Finished Feb 09 06:31:28 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233813782 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3233813782
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3223597776
Short name T523
Test name
Test status
Simulation time 19858866 ps
CPU time 1.31 seconds
Started Feb 09 06:31:27 AM UTC 25
Finished Feb 09 06:31:30 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223597776 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3223597776
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_rand_intr_trigger.1579107060
Short name T527
Test name
Test status
Simulation time 483349176 ps
CPU time 4.26 seconds
Started Feb 09 06:31:26 AM UTC 25
Finished Feb 09 06:31:32 AM UTC 25
Peak memory 198716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579107060 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.1579107060
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_random_dout_din.301118854
Short name T466
Test name
Test status
Simulation time 123764374 ps
CPU time 1.22 seconds
Started Feb 09 06:31:25 AM UTC 25
Finished Feb 09 06:31:27 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301118854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.gpio_random_dout_din.301118854
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.423129570
Short name T521
Test name
Test status
Simulation time 112212945 ps
CPU time 1.22 seconds
Started Feb 09 06:31:26 AM UTC 25
Finished Feb 09 06:31:29 AM UTC 25
Peak memory 198364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423129570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_pulldown.423129570
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2722591647
Short name T528
Test name
Test status
Simulation time 29803616 ps
CPU time 2.14 seconds
Started Feb 09 06:31:28 AM UTC 25
Finished Feb 09 06:31:32 AM UTC 25
Peak memory 198640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722591647 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_long_reg_writes_reg_reads.2722591647
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_smoke.453068933
Short name T458
Test name
Test status
Simulation time 128014262 ps
CPU time 1.76 seconds
Started Feb 09 06:31:24 AM UTC 25
Finished Feb 09 06:31:27 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453068933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 36.gpio_smoke.453068933
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_smoke_no_pullup_pulldown.1083528225
Short name T445
Test name
Test status
Simulation time 196605950 ps
CPU time 1.22 seconds
Started Feb 09 06:31:25 AM UTC 25
Finished Feb 09 06:31:27 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083528225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1083528225
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/36.gpio_stress_all.865545795
Short name T637
Test name
Test status
Simulation time 6745908930 ps
CPU time 77.54 seconds
Started Feb 09 06:31:28 AM UTC 25
Finished Feb 09 06:32:48 AM UTC 25
Peak memory 200780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865545795 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all.865545795
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_alert_test.2359757231
Short name T537
Test name
Test status
Simulation time 20753067 ps
CPU time 0.81 seconds
Started Feb 09 06:31:35 AM UTC 25
Finished Feb 09 06:31:37 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359757231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2359757231
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_dout_din_regs_random_rw.1338999293
Short name T533
Test name
Test status
Simulation time 153389742 ps
CPU time 1.43 seconds
Started Feb 09 06:31:32 AM UTC 25
Finished Feb 09 06:31:34 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338999293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1338999293
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_filter_stress.265278729
Short name T567
Test name
Test status
Simulation time 901492891 ps
CPU time 25.33 seconds
Started Feb 09 06:31:33 AM UTC 25
Finished Feb 09 06:32:00 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265278729 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress.265278729
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_full_random.3633942932
Short name T535
Test name
Test status
Simulation time 69334688 ps
CPU time 0.93 seconds
Started Feb 09 06:31:34 AM UTC 25
Finished Feb 09 06:31:36 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633942932 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3633942932
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_intr_rand_pgm.2126187552
Short name T534
Test name
Test status
Simulation time 83718060 ps
CPU time 2.04 seconds
Started Feb 09 06:31:33 AM UTC 25
Finished Feb 09 06:31:36 AM UTC 25
Peak memory 198096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126187552 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2126187552
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1297236845
Short name T539
Test name
Test status
Simulation time 246458761 ps
CPU time 3.82 seconds
Started Feb 09 06:31:33 AM UTC 25
Finished Feb 09 06:31:38 AM UTC 25
Peak memory 200404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297236845 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1297236845
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_rand_intr_trigger.513720770
Short name T540
Test name
Test status
Simulation time 116605038 ps
CPU time 4.3 seconds
Started Feb 09 06:31:33 AM UTC 25
Finished Feb 09 06:31:38 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513720770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.513720770
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_random_dout_din.2651423634
Short name T531
Test name
Test status
Simulation time 30237682 ps
CPU time 0.97 seconds
Started Feb 09 06:31:31 AM UTC 25
Finished Feb 09 06:31:33 AM UTC 25
Peak memory 198368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651423634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.gpio_random_dout_din.2651423634
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2089886165
Short name T532
Test name
Test status
Simulation time 51576335 ps
CPU time 1.73 seconds
Started Feb 09 06:31:31 AM UTC 25
Finished Feb 09 06:31:34 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089886165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup_pulldown.2089886165
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_random_long_reg_writes_reg_reads.228769967
Short name T538
Test name
Test status
Simulation time 114156220 ps
CPU time 3.22 seconds
Started Feb 09 06:31:33 AM UTC 25
Finished Feb 09 06:31:38 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228769967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_long_reg_writes_reg_reads.228769967
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_smoke.2424469900
Short name T530
Test name
Test status
Simulation time 274639217 ps
CPU time 1.96 seconds
Started Feb 09 06:31:30 AM UTC 25
Finished Feb 09 06:31:33 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424469900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.gpio_smoke.2424469900
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_smoke_no_pullup_pulldown.2879797948
Short name T529
Test name
Test status
Simulation time 136482615 ps
CPU time 1.3 seconds
Started Feb 09 06:31:30 AM UTC 25
Finished Feb 09 06:31:32 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879797948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2879797948
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_stress_all.2277562143
Short name T699
Test name
Test status
Simulation time 10599007606 ps
CPU time 185.69 seconds
Started Feb 09 06:31:34 AM UTC 25
Finished Feb 09 06:34:43 AM UTC 25
Peak memory 200836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277562143 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all.2277562143
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/37.gpio_stress_all_with_rand_reset.3907205478
Short name T85
Test name
Test status
Simulation time 185995505324 ps
CPU time 678.48 seconds
Started Feb 09 06:31:34 AM UTC 25
Finished Feb 09 06:43:01 AM UTC 25
Peak memory 215404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3907205478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stres
s_all_with_rand_reset.3907205478
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_alert_test.2649193539
Short name T550
Test name
Test status
Simulation time 12124085 ps
CPU time 0.84 seconds
Started Feb 09 06:31:45 AM UTC 25
Finished Feb 09 06:31:47 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649193539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2649193539
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_dout_din_regs_random_rw.208423576
Short name T544
Test name
Test status
Simulation time 27373925 ps
CPU time 1.08 seconds
Started Feb 09 06:31:39 AM UTC 25
Finished Feb 09 06:31:41 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208423576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.208423576
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_filter_stress.3173988943
Short name T560
Test name
Test status
Simulation time 144934016 ps
CPU time 11.6 seconds
Started Feb 09 06:31:41 AM UTC 25
Finished Feb 09 06:31:54 AM UTC 25
Peak memory 198696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173988943 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stress.3173988943
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_full_random.2950226062
Short name T547
Test name
Test status
Simulation time 58400786 ps
CPU time 1.28 seconds
Started Feb 09 06:31:42 AM UTC 25
Finished Feb 09 06:31:44 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950226062 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2950226062
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_intr_rand_pgm.271921816
Short name T546
Test name
Test status
Simulation time 58448215 ps
CPU time 1.48 seconds
Started Feb 09 06:31:39 AM UTC 25
Finished Feb 09 06:31:41 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271921816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.271921816
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2628057793
Short name T549
Test name
Test status
Simulation time 149997420 ps
CPU time 4.69 seconds
Started Feb 09 06:31:41 AM UTC 25
Finished Feb 09 06:31:47 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628057793 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2628057793
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_rand_intr_trigger.2867513198
Short name T548
Test name
Test status
Simulation time 100669148 ps
CPU time 4.33 seconds
Started Feb 09 06:31:40 AM UTC 25
Finished Feb 09 06:31:45 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867513198 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.2867513198
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_random_dout_din.320930096
Short name T542
Test name
Test status
Simulation time 221740766 ps
CPU time 1.37 seconds
Started Feb 09 06:31:37 AM UTC 25
Finished Feb 09 06:31:40 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320930096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.gpio_random_dout_din.320930096
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2850776286
Short name T545
Test name
Test status
Simulation time 553861911 ps
CPU time 1.51 seconds
Started Feb 09 06:31:39 AM UTC 25
Finished Feb 09 06:31:41 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850776286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_pulldown.2850776286
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2181688924
Short name T552
Test name
Test status
Simulation time 474864231 ps
CPU time 5.05 seconds
Started Feb 09 06:31:42 AM UTC 25
Finished Feb 09 06:31:48 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181688924 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_long_reg_writes_reg_reads.2181688924
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_smoke.3912971110
Short name T541
Test name
Test status
Simulation time 196482547 ps
CPU time 1.21 seconds
Started Feb 09 06:31:37 AM UTC 25
Finished Feb 09 06:31:40 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912971110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.gpio_smoke.3912971110
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_smoke_no_pullup_pulldown.1548802109
Short name T543
Test name
Test status
Simulation time 123407721 ps
CPU time 1.87 seconds
Started Feb 09 06:31:37 AM UTC 25
Finished Feb 09 06:31:40 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548802109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1548802109
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_stress_all.1037675378
Short name T588
Test name
Test status
Simulation time 2393163802 ps
CPU time 36.26 seconds
Started Feb 09 06:31:42 AM UTC 25
Finished Feb 09 06:32:20 AM UTC 25
Peak memory 200912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037675378 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all.1037675378
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/38.gpio_stress_all_with_rand_reset.1421670095
Short name T81
Test name
Test status
Simulation time 50782883820 ps
CPU time 492.34 seconds
Started Feb 09 06:31:42 AM UTC 25
Finished Feb 09 06:40:01 AM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1421670095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stres
s_all_with_rand_reset.1421670095
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_alert_test.3418147766
Short name T563
Test name
Test status
Simulation time 41069660 ps
CPU time 0.84 seconds
Started Feb 09 06:31:55 AM UTC 25
Finished Feb 09 06:31:57 AM UTC 25
Peak memory 198380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418147766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3418147766
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_dout_din_regs_random_rw.665620762
Short name T557
Test name
Test status
Simulation time 203447245 ps
CPU time 1.35 seconds
Started Feb 09 06:31:49 AM UTC 25
Finished Feb 09 06:31:52 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665620762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.665620762
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_filter_stress.939752702
Short name T585
Test name
Test status
Simulation time 675839300 ps
CPU time 23.08 seconds
Started Feb 09 06:31:52 AM UTC 25
Finished Feb 09 06:32:17 AM UTC 25
Peak memory 198676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939752702 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stress.939752702
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_full_random.2767187436
Short name T562
Test name
Test status
Simulation time 210975687 ps
CPU time 1.4 seconds
Started Feb 09 06:31:53 AM UTC 25
Finished Feb 09 06:31:56 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767187436 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2767187436
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_intr_rand_pgm.1343829646
Short name T556
Test name
Test status
Simulation time 60313012 ps
CPU time 1.14 seconds
Started Feb 09 06:31:49 AM UTC 25
Finished Feb 09 06:31:52 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343829646 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1343829646
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1862610318
Short name T561
Test name
Test status
Simulation time 39703436 ps
CPU time 1.43 seconds
Started Feb 09 06:31:51 AM UTC 25
Finished Feb 09 06:31:54 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862610318 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1862610318
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_rand_intr_trigger.2126546925
Short name T559
Test name
Test status
Simulation time 46527203 ps
CPU time 1.64 seconds
Started Feb 09 06:31:50 AM UTC 25
Finished Feb 09 06:31:53 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126546925 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.2126546925
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_random_dout_din.3578357737
Short name T555
Test name
Test status
Simulation time 427674897 ps
CPU time 1.44 seconds
Started Feb 09 06:31:48 AM UTC 25
Finished Feb 09 06:31:51 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578357737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.gpio_random_dout_din.3578357737
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2088635310
Short name T558
Test name
Test status
Simulation time 111126013 ps
CPU time 1.96 seconds
Started Feb 09 06:31:49 AM UTC 25
Finished Feb 09 06:31:52 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088635310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_pulldown.2088635310
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2584883542
Short name T565
Test name
Test status
Simulation time 177025389 ps
CPU time 4.27 seconds
Started Feb 09 06:31:52 AM UTC 25
Finished Feb 09 06:31:58 AM UTC 25
Peak memory 198708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584883542 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_long_reg_writes_reg_reads.2584883542
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_smoke.3567752387
Short name T553
Test name
Test status
Simulation time 311963244 ps
CPU time 1.14 seconds
Started Feb 09 06:31:46 AM UTC 25
Finished Feb 09 06:31:48 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567752387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.gpio_smoke.3567752387
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_smoke_no_pullup_pulldown.3396830993
Short name T554
Test name
Test status
Simulation time 300466543 ps
CPU time 1.42 seconds
Started Feb 09 06:31:47 AM UTC 25
Finished Feb 09 06:31:50 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396830993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3396830993
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_stress_all.56548572
Short name T95
Test name
Test status
Simulation time 9084352528 ps
CPU time 149.47 seconds
Started Feb 09 06:31:54 AM UTC 25
Finished Feb 09 06:34:26 AM UTC 25
Peak memory 200952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56548572 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all.56548572
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/39.gpio_stress_all_with_rand_reset.499788406
Short name T84
Test name
Test status
Simulation time 23000463926 ps
CPU time 656.01 seconds
Started Feb 09 06:31:55 AM UTC 25
Finished Feb 09 06:42:59 AM UTC 25
Peak memory 206468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=499788406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress
_all_with_rand_reset.499788406
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_alert_test.3043995332
Short name T147
Test name
Test status
Simulation time 13792846 ps
CPU time 0.51 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:34 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043995332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3043995332
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_dout_din_regs_random_rw.3651440342
Short name T140
Test name
Test status
Simulation time 175016800 ps
CPU time 0.55 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651440342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3651440342
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_filter_stress.3046706346
Short name T175
Test name
Test status
Simulation time 171185010 ps
CPU time 7.69 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046706346 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress.3046706346
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_full_random.501982933
Short name T18
Test name
Test status
Simulation time 309196225 ps
CPU time 0.94 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501982933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.501982933
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_intr_rand_pgm.3877069137
Short name T145
Test name
Test status
Simulation time 146597563 ps
CPU time 1.07 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:34 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877069137 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3877069137
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3832045717
Short name T11
Test name
Test status
Simulation time 79329818 ps
CPU time 2.81 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 200724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832045717 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3832045717
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_rand_intr_trigger.3986216114
Short name T26
Test name
Test status
Simulation time 168182538 ps
CPU time 3.06 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986216114 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.3986216114
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_random_dout_din.2097213614
Short name T142
Test name
Test status
Simulation time 37547550 ps
CPU time 1.05 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097213614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.gpio_random_dout_din.2097213614
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2304438670
Short name T144
Test name
Test status
Simulation time 71382209 ps
CPU time 1.13 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:34 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304438670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_pulldown.2304438670
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2376404271
Short name T3
Test name
Test status
Simulation time 1504424608 ps
CPU time 4.04 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:38 AM UTC 25
Peak memory 198808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376404271 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_long_reg_writes_reg_reads.2376404271
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_sec_cm.1340634135
Short name T20
Test name
Test status
Simulation time 199679210 ps
CPU time 0.86 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 235388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340634135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1340634135
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_smoke.2530378667
Short name T141
Test name
Test status
Simulation time 232436629 ps
CPU time 0.98 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:33 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530378667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.gpio_smoke.2530378667
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_smoke_no_pullup_pulldown.2375529138
Short name T143
Test name
Test status
Simulation time 276465707 ps
CPU time 1.14 seconds
Started Feb 09 06:28:31 AM UTC 25
Finished Feb 09 06:28:34 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375529138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2375529138
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/4.gpio_stress_all.1210842826
Short name T371
Test name
Test status
Simulation time 21056367490 ps
CPU time 77.37 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:29:52 AM UTC 25
Peak memory 200920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210842826 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all.1210842826
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_alert_test.2478822321
Short name T577
Test name
Test status
Simulation time 20150347 ps
CPU time 0.84 seconds
Started Feb 09 06:32:08 AM UTC 25
Finished Feb 09 06:32:10 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478822321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2478822321
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_dout_din_regs_random_rw.1365093278
Short name T571
Test name
Test status
Simulation time 167730318 ps
CPU time 0.93 seconds
Started Feb 09 06:32:00 AM UTC 25
Finished Feb 09 06:32:02 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365093278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1365093278
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_filter_stress.3147121553
Short name T605
Test name
Test status
Simulation time 802509173 ps
CPU time 26.81 seconds
Started Feb 09 06:32:02 AM UTC 25
Finished Feb 09 06:32:30 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147121553 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress.3147121553
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_full_random.64777396
Short name T575
Test name
Test status
Simulation time 276261759 ps
CPU time 1.24 seconds
Started Feb 09 06:32:04 AM UTC 25
Finished Feb 09 06:32:07 AM UTC 25
Peak memory 198380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64777396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.64777396
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_intr_rand_pgm.3855150387
Short name T572
Test name
Test status
Simulation time 221558658 ps
CPU time 1.4 seconds
Started Feb 09 06:32:01 AM UTC 25
Finished Feb 09 06:32:04 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855150387 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3855150387
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2970454519
Short name T576
Test name
Test status
Simulation time 90871879 ps
CPU time 4.79 seconds
Started Feb 09 06:32:01 AM UTC 25
Finished Feb 09 06:32:07 AM UTC 25
Peak memory 198812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970454519 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2970454519
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_rand_intr_trigger.1075378368
Short name T573
Test name
Test status
Simulation time 131631395 ps
CPU time 3.56 seconds
Started Feb 09 06:32:01 AM UTC 25
Finished Feb 09 06:32:06 AM UTC 25
Peak memory 198756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075378368 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.1075378368
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_random_dout_din.78389450
Short name T568
Test name
Test status
Simulation time 21141643 ps
CPU time 1.05 seconds
Started Feb 09 06:31:58 AM UTC 25
Finished Feb 09 06:32:00 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78389450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dou
t_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.gpio_random_dout_din.78389450
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4136866224
Short name T570
Test name
Test status
Simulation time 29916390 ps
CPU time 1.57 seconds
Started Feb 09 06:31:59 AM UTC 25
Finished Feb 09 06:32:02 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136866224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup_pulldown.4136866224
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2599615621
Short name T578
Test name
Test status
Simulation time 1232570984 ps
CPU time 5.88 seconds
Started Feb 09 06:32:03 AM UTC 25
Finished Feb 09 06:32:10 AM UTC 25
Peak memory 200712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599615621 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_long_reg_writes_reg_reads.2599615621
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_smoke.1930504132
Short name T566
Test name
Test status
Simulation time 86852289 ps
CPU time 1.32 seconds
Started Feb 09 06:31:57 AM UTC 25
Finished Feb 09 06:31:59 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930504132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.gpio_smoke.1930504132
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_smoke_no_pullup_pulldown.1649808217
Short name T569
Test name
Test status
Simulation time 250308964 ps
CPU time 1.58 seconds
Started Feb 09 06:31:58 AM UTC 25
Finished Feb 09 06:32:00 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649808217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1649808217
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/40.gpio_stress_all.907292198
Short name T91
Test name
Test status
Simulation time 9431539843 ps
CPU time 114.81 seconds
Started Feb 09 06:32:06 AM UTC 25
Finished Feb 09 06:34:03 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907292198 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all.907292198
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_alert_test.3294034752
Short name T592
Test name
Test status
Simulation time 23582907 ps
CPU time 0.86 seconds
Started Feb 09 06:32:20 AM UTC 25
Finished Feb 09 06:32:22 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294034752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3294034752
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_dout_din_regs_random_rw.2846416619
Short name T584
Test name
Test status
Simulation time 81773494 ps
CPU time 1.02 seconds
Started Feb 09 06:32:14 AM UTC 25
Finished Feb 09 06:32:16 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846416619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2846416619
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_filter_stress.2137696780
Short name T594
Test name
Test status
Simulation time 605849898 ps
CPU time 5.47 seconds
Started Feb 09 06:32:17 AM UTC 25
Finished Feb 09 06:32:24 AM UTC 25
Peak memory 198860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137696780 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stress.2137696780
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_full_random.4266236676
Short name T590
Test name
Test status
Simulation time 99889946 ps
CPU time 1.09 seconds
Started Feb 09 06:32:19 AM UTC 25
Finished Feb 09 06:32:21 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266236676 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.4266236676
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_intr_rand_pgm.2541248032
Short name T586
Test name
Test status
Simulation time 79478122 ps
CPU time 1.8 seconds
Started Feb 09 06:32:15 AM UTC 25
Finished Feb 09 06:32:18 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541248032 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2541248032
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_intr_with_filter_rand_intr_event.663213357
Short name T587
Test name
Test status
Simulation time 370990765 ps
CPU time 1.97 seconds
Started Feb 09 06:32:16 AM UTC 25
Finished Feb 09 06:32:19 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663213357 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.663213357
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_rand_intr_trigger.3275267669
Short name T589
Test name
Test status
Simulation time 292257792 ps
CPU time 3.79 seconds
Started Feb 09 06:32:15 AM UTC 25
Finished Feb 09 06:32:20 AM UTC 25
Peak memory 198732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275267669 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.3275267669
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_random_dout_din.2934733090
Short name T580
Test name
Test status
Simulation time 29354439 ps
CPU time 1.5 seconds
Started Feb 09 06:32:11 AM UTC 25
Finished Feb 09 06:32:13 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934733090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.gpio_random_dout_din.2934733090
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2228942927
Short name T583
Test name
Test status
Simulation time 70228914 ps
CPU time 1.3 seconds
Started Feb 09 06:32:13 AM UTC 25
Finished Feb 09 06:32:15 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228942927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup_pulldown.2228942927
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4205739492
Short name T598
Test name
Test status
Simulation time 634729747 ps
CPU time 7.05 seconds
Started Feb 09 06:32:18 AM UTC 25
Finished Feb 09 06:32:26 AM UTC 25
Peak memory 198808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205739492 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_long_reg_writes_reg_reads.4205739492
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_smoke.3434786807
Short name T579
Test name
Test status
Simulation time 107743325 ps
CPU time 1.92 seconds
Started Feb 09 06:32:09 AM UTC 25
Finished Feb 09 06:32:12 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434786807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.gpio_smoke.3434786807
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_smoke_no_pullup_pulldown.1305861430
Short name T581
Test name
Test status
Simulation time 269066357 ps
CPU time 1.78 seconds
Started Feb 09 06:32:11 AM UTC 25
Finished Feb 09 06:32:14 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305861430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1305861430
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/41.gpio_stress_all.2831109221
Short name T607
Test name
Test status
Simulation time 3993706710 ps
CPU time 49.37 seconds
Started Feb 09 06:32:20 AM UTC 25
Finished Feb 09 06:33:12 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831109221 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all.2831109221
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_alert_test.1983390770
Short name T609
Test name
Test status
Simulation time 38578146 ps
CPU time 0.76 seconds
Started Feb 09 06:32:30 AM UTC 25
Finished Feb 09 06:32:32 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983390770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1983390770
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_dout_din_regs_random_rw.2271570603
Short name T601
Test name
Test status
Simulation time 31834124 ps
CPU time 0.94 seconds
Started Feb 09 06:32:25 AM UTC 25
Finished Feb 09 06:32:27 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271570603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2271570603
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_filter_stress.1161525057
Short name T616
Test name
Test status
Simulation time 409440206 ps
CPU time 5.17 seconds
Started Feb 09 06:32:27 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 198868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161525057 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stress.1161525057
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_full_random.3301206861
Short name T606
Test name
Test status
Simulation time 1270162199 ps
CPU time 1.66 seconds
Started Feb 09 06:32:28 AM UTC 25
Finished Feb 09 06:32:30 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301206861 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3301206861
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_intr_rand_pgm.2280117031
Short name T602
Test name
Test status
Simulation time 52883531 ps
CPU time 1.43 seconds
Started Feb 09 06:32:26 AM UTC 25
Finished Feb 09 06:32:29 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280117031 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2280117031
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_intr_with_filter_rand_intr_event.476206759
Short name T608
Test name
Test status
Simulation time 748344820 ps
CPU time 3.76 seconds
Started Feb 09 06:32:26 AM UTC 25
Finished Feb 09 06:32:31 AM UTC 25
Peak memory 198676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476206759 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.476206759
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_rand_intr_trigger.427815873
Short name T603
Test name
Test status
Simulation time 149947319 ps
CPU time 1.58 seconds
Started Feb 09 06:32:26 AM UTC 25
Finished Feb 09 06:32:29 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427815873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.427815873
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_random_dout_din.4281701568
Short name T599
Test name
Test status
Simulation time 352872516 ps
CPU time 1.39 seconds
Started Feb 09 06:32:24 AM UTC 25
Finished Feb 09 06:32:27 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281701568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.gpio_random_dout_din.4281701568
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.38393106
Short name T600
Test name
Test status
Simulation time 113761816 ps
CPU time 1.72 seconds
Started Feb 09 06:32:24 AM UTC 25
Finished Feb 09 06:32:27 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38393106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_pulldown.38393106
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3677095778
Short name T604
Test name
Test status
Simulation time 538124626 ps
CPU time 1.62 seconds
Started Feb 09 06:32:27 AM UTC 25
Finished Feb 09 06:32:30 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677095778 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_long_reg_writes_reg_reads.3677095778
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_smoke.3986849399
Short name T597
Test name
Test status
Simulation time 981958824 ps
CPU time 1.48 seconds
Started Feb 09 06:32:23 AM UTC 25
Finished Feb 09 06:32:25 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986849399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.gpio_smoke.3986849399
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_smoke_no_pullup_pulldown.96902378
Short name T596
Test name
Test status
Simulation time 413666623 ps
CPU time 1.37 seconds
Started Feb 09 06:32:23 AM UTC 25
Finished Feb 09 06:32:25 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96902378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.96902378
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/42.gpio_stress_all.610341429
Short name T698
Test name
Test status
Simulation time 22563475387 ps
CPU time 123.52 seconds
Started Feb 09 06:32:29 AM UTC 25
Finished Feb 09 06:34:35 AM UTC 25
Peak memory 200848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610341429 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all.610341429
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_alert_test.4277230670
Short name T622
Test name
Test status
Simulation time 78722066 ps
CPU time 0.84 seconds
Started Feb 09 06:32:36 AM UTC 25
Finished Feb 09 06:32:38 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277230670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4277230670
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_dout_din_regs_random_rw.247333317
Short name T617
Test name
Test status
Simulation time 22694319 ps
CPU time 1.15 seconds
Started Feb 09 06:32:32 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247333317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.247333317
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_filter_stress.3313530362
Short name T644
Test name
Test status
Simulation time 2083050515 ps
CPU time 16.94 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:32:53 AM UTC 25
Peak memory 198784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313530362 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress.3313530362
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_full_random.3942295909
Short name T620
Test name
Test status
Simulation time 83360232 ps
CPU time 1.17 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:32:37 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942295909 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3942295909
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_intr_rand_pgm.3922333746
Short name T619
Test name
Test status
Simulation time 264961286 ps
CPU time 1.49 seconds
Started Feb 09 06:32:32 AM UTC 25
Finished Feb 09 06:32:35 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922333746 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3922333746
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3023706553
Short name T624
Test name
Test status
Simulation time 60964004 ps
CPU time 3.46 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:32:39 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023706553 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3023706553
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_rand_intr_trigger.2354409135
Short name T625
Test name
Test status
Simulation time 192154202 ps
CPU time 4.01 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:32:39 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354409135 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.2354409135
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_random_dout_din.3021635303
Short name T612
Test name
Test status
Simulation time 95959374 ps
CPU time 1.6 seconds
Started Feb 09 06:32:31 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021635303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.gpio_random_dout_din.3021635303
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2029357249
Short name T618
Test name
Test status
Simulation time 23494072 ps
CPU time 1.29 seconds
Started Feb 09 06:32:32 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029357249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup_pulldown.2029357249
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_random_long_reg_writes_reg_reads.193852835
Short name T631
Test name
Test status
Simulation time 385491726 ps
CPU time 7.02 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:32:43 AM UTC 25
Peak memory 198768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193852835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_long_reg_writes_reg_reads.193852835
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_smoke.2418677964
Short name T615
Test name
Test status
Simulation time 238707437 ps
CPU time 1.61 seconds
Started Feb 09 06:32:31 AM UTC 25
Finished Feb 09 06:32:34 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418677964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.gpio_smoke.2418677964
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_smoke_no_pullup_pulldown.3963548646
Short name T611
Test name
Test status
Simulation time 626978020 ps
CPU time 1.2 seconds
Started Feb 09 06:32:31 AM UTC 25
Finished Feb 09 06:32:33 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963548646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3963548646
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/43.gpio_stress_all.1318553091
Short name T672
Test name
Test status
Simulation time 5300638068 ps
CPU time 39.37 seconds
Started Feb 09 06:32:34 AM UTC 25
Finished Feb 09 06:33:15 AM UTC 25
Peak memory 200852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318553091 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all.1318553091
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_alert_test.2267882835
Short name T636
Test name
Test status
Simulation time 12755102 ps
CPU time 0.85 seconds
Started Feb 09 06:32:45 AM UTC 25
Finished Feb 09 06:32:47 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267882835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2267882835
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_dout_din_regs_random_rw.371434290
Short name T629
Test name
Test status
Simulation time 16125159 ps
CPU time 0.92 seconds
Started Feb 09 06:32:39 AM UTC 25
Finished Feb 09 06:32:41 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371434290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.371434290
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_filter_stress.3661267388
Short name T645
Test name
Test status
Simulation time 572268303 ps
CPU time 11.39 seconds
Started Feb 09 06:32:41 AM UTC 25
Finished Feb 09 06:32:54 AM UTC 25
Peak memory 198804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661267388 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress.3661267388
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_full_random.198367090
Short name T632
Test name
Test status
Simulation time 249196323 ps
CPU time 1.37 seconds
Started Feb 09 06:32:42 AM UTC 25
Finished Feb 09 06:32:45 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198367090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.198367090
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_intr_rand_pgm.688485077
Short name T630
Test name
Test status
Simulation time 40247690 ps
CPU time 1.15 seconds
Started Feb 09 06:32:40 AM UTC 25
Finished Feb 09 06:32:42 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688485077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.688485077
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_intr_with_filter_rand_intr_event.330715162
Short name T635
Test name
Test status
Simulation time 297980840 ps
CPU time 4.47 seconds
Started Feb 09 06:32:41 AM UTC 25
Finished Feb 09 06:32:47 AM UTC 25
Peak memory 201012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330715162 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.330715162
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_rand_intr_trigger.608257450
Short name T634
Test name
Test status
Simulation time 283883574 ps
CPU time 4.77 seconds
Started Feb 09 06:32:40 AM UTC 25
Finished Feb 09 06:32:46 AM UTC 25
Peak memory 198748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608257450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.608257450
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_random_dout_din.2002857225
Short name T626
Test name
Test status
Simulation time 47184648 ps
CPU time 1.53 seconds
Started Feb 09 06:32:38 AM UTC 25
Finished Feb 09 06:32:41 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002857225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.gpio_random_dout_din.2002857225
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3411072577
Short name T627
Test name
Test status
Simulation time 46869951 ps
CPU time 1.63 seconds
Started Feb 09 06:32:38 AM UTC 25
Finished Feb 09 06:32:41 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411072577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup_pulldown.3411072577
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3957977961
Short name T633
Test name
Test status
Simulation time 198768444 ps
CPU time 2.48 seconds
Started Feb 09 06:32:42 AM UTC 25
Finished Feb 09 06:32:46 AM UTC 25
Peak memory 200744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957977961 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_long_reg_writes_reg_reads.3957977961
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_smoke.2602733388
Short name T623
Test name
Test status
Simulation time 79996884 ps
CPU time 1.77 seconds
Started Feb 09 06:32:36 AM UTC 25
Finished Feb 09 06:32:39 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602733388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.gpio_smoke.2602733388
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_smoke_no_pullup_pulldown.2114934941
Short name T628
Test name
Test status
Simulation time 121748161 ps
CPU time 1.79 seconds
Started Feb 09 06:32:38 AM UTC 25
Finished Feb 09 06:32:41 AM UTC 25
Peak memory 198368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114934941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2114934941
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/44.gpio_stress_all.4119583412
Short name T703
Test name
Test status
Simulation time 25339007998 ps
CPU time 207.37 seconds
Started Feb 09 06:32:43 AM UTC 25
Finished Feb 09 06:36:14 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119583412 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all.4119583412
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_alert_test.2383031533
Short name T651
Test name
Test status
Simulation time 25553117 ps
CPU time 0.85 seconds
Started Feb 09 06:32:55 AM UTC 25
Finished Feb 09 06:32:57 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383031533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2383031533
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_dout_din_regs_random_rw.3715961418
Short name T641
Test name
Test status
Simulation time 73520283 ps
CPU time 1.25 seconds
Started Feb 09 06:32:49 AM UTC 25
Finished Feb 09 06:32:51 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715961418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3715961418
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_filter_stress.1217855589
Short name T663
Test name
Test status
Simulation time 1942008860 ps
CPU time 13.41 seconds
Started Feb 09 06:32:52 AM UTC 25
Finished Feb 09 06:33:07 AM UTC 25
Peak memory 198720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217855589 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stress.1217855589
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_full_random.1394464492
Short name T647
Test name
Test status
Simulation time 72588672 ps
CPU time 1.47 seconds
Started Feb 09 06:32:52 AM UTC 25
Finished Feb 09 06:32:55 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394464492 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1394464492
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_intr_rand_pgm.3878531670
Short name T646
Test name
Test status
Simulation time 55826806 ps
CPU time 1.99 seconds
Started Feb 09 06:32:51 AM UTC 25
Finished Feb 09 06:32:54 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878531670 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3878531670
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_intr_with_filter_rand_intr_event.54723058
Short name T648
Test name
Test status
Simulation time 335885804 ps
CPU time 3.08 seconds
Started Feb 09 06:32:51 AM UTC 25
Finished Feb 09 06:32:55 AM UTC 25
Peak memory 198828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54723058 -assert nopostproc +UVM_T
ESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.54723058
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_rand_intr_trigger.3385695391
Short name T650
Test name
Test status
Simulation time 520368546 ps
CPU time 4.1 seconds
Started Feb 09 06:32:51 AM UTC 25
Finished Feb 09 06:32:56 AM UTC 25
Peak memory 198804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385695391 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.3385695391
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_random_dout_din.4218153392
Short name T640
Test name
Test status
Simulation time 101635963 ps
CPU time 1.24 seconds
Started Feb 09 06:32:48 AM UTC 25
Finished Feb 09 06:32:50 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218153392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.gpio_random_dout_din.4218153392
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2494960217
Short name T642
Test name
Test status
Simulation time 133476599 ps
CPU time 1.35 seconds
Started Feb 09 06:32:49 AM UTC 25
Finished Feb 09 06:32:51 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494960217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup_pulldown.2494960217
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2067258013
Short name T649
Test name
Test status
Simulation time 300002193 ps
CPU time 1.97 seconds
Started Feb 09 06:32:52 AM UTC 25
Finished Feb 09 06:32:55 AM UTC 25
Peak memory 198448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067258013 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_long_reg_writes_reg_reads.2067258013
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_smoke.2849896472
Short name T639
Test name
Test status
Simulation time 157341879 ps
CPU time 2.15 seconds
Started Feb 09 06:32:46 AM UTC 25
Finished Feb 09 06:32:50 AM UTC 25
Peak memory 198656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849896472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.gpio_smoke.2849896472
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_smoke_no_pullup_pulldown.34242405
Short name T638
Test name
Test status
Simulation time 50899273 ps
CPU time 1.92 seconds
Started Feb 09 06:32:47 AM UTC 25
Finished Feb 09 06:32:50 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34242405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.34242405
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/45.gpio_stress_all.1466555059
Short name T704
Test name
Test status
Simulation time 36182189192 ps
CPU time 207.3 seconds
Started Feb 09 06:32:53 AM UTC 25
Finished Feb 09 06:36:24 AM UTC 25
Peak memory 200916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466555059 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all.1466555059
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_alert_test.51007229
Short name T664
Test name
Test status
Simulation time 13696739 ps
CPU time 0.88 seconds
Started Feb 09 06:33:05 AM UTC 25
Finished Feb 09 06:33:07 AM UTC 25
Peak memory 198404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51007229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.51007229
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_dout_din_regs_random_rw.1302873960
Short name T657
Test name
Test status
Simulation time 68369607 ps
CPU time 0.94 seconds
Started Feb 09 06:32:59 AM UTC 25
Finished Feb 09 06:33:01 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302873960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1302873960
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_filter_stress.2822844657
Short name T682
Test name
Test status
Simulation time 1865738835 ps
CPU time 28.33 seconds
Started Feb 09 06:33:00 AM UTC 25
Finished Feb 09 06:33:30 AM UTC 25
Peak memory 198548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822844657 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stress.2822844657
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_full_random.2135366557
Short name T661
Test name
Test status
Simulation time 65657099 ps
CPU time 1.48 seconds
Started Feb 09 06:33:02 AM UTC 25
Finished Feb 09 06:33:05 AM UTC 25
Peak memory 198268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135366557 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2135366557
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_intr_rand_pgm.245901085
Short name T659
Test name
Test status
Simulation time 55949672 ps
CPU time 1.53 seconds
Started Feb 09 06:32:59 AM UTC 25
Finished Feb 09 06:33:01 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245901085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.245901085
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4213860177
Short name T660
Test name
Test status
Simulation time 70146344 ps
CPU time 3.09 seconds
Started Feb 09 06:33:00 AM UTC 25
Finished Feb 09 06:33:04 AM UTC 25
Peak memory 200536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213860177 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.4213860177
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_rand_intr_trigger.3406482080
Short name T658
Test name
Test status
Simulation time 26201517 ps
CPU time 1.28 seconds
Started Feb 09 06:32:59 AM UTC 25
Finished Feb 09 06:33:01 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406482080 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.3406482080
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_random_dout_din.173648349
Short name T654
Test name
Test status
Simulation time 17803331 ps
CPU time 0.99 seconds
Started Feb 09 06:32:56 AM UTC 25
Finished Feb 09 06:32:59 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173648349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.gpio_random_dout_din.173648349
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.76514959
Short name T656
Test name
Test status
Simulation time 347332738 ps
CPU time 1.74 seconds
Started Feb 09 06:32:57 AM UTC 25
Finished Feb 09 06:33:00 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76514959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup_pulldown.76514959
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2057739623
Short name T662
Test name
Test status
Simulation time 912723205 ps
CPU time 2.63 seconds
Started Feb 09 06:33:01 AM UTC 25
Finished Feb 09 06:33:05 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057739623 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_long_reg_writes_reg_reads.2057739623
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_smoke.2326732058
Short name T653
Test name
Test status
Simulation time 37430099 ps
CPU time 1.22 seconds
Started Feb 09 06:32:55 AM UTC 25
Finished Feb 09 06:32:58 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326732058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.gpio_smoke.2326732058
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_smoke_no_pullup_pulldown.1554040389
Short name T655
Test name
Test status
Simulation time 180895553 ps
CPU time 1.81 seconds
Started Feb 09 06:32:56 AM UTC 25
Finished Feb 09 06:32:59 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554040389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1554040389
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/46.gpio_stress_all.1975727974
Short name T702
Test name
Test status
Simulation time 13583806144 ps
CPU time 182.52 seconds
Started Feb 09 06:33:02 AM UTC 25
Finished Feb 09 06:36:08 AM UTC 25
Peak memory 200552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975727974 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all.1975727974
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_alert_test.1154823797
Short name T673
Test name
Test status
Simulation time 14555764 ps
CPU time 0.88 seconds
Started Feb 09 06:33:16 AM UTC 25
Finished Feb 09 06:33:18 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154823797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1154823797
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_dout_din_regs_random_rw.1913305399
Short name T668
Test name
Test status
Simulation time 113724829 ps
CPU time 1.23 seconds
Started Feb 09 06:33:08 AM UTC 25
Finished Feb 09 06:33:11 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913305399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1913305399
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_filter_stress.3275203317
Short name T681
Test name
Test status
Simulation time 206125765 ps
CPU time 14.8 seconds
Started Feb 09 06:33:12 AM UTC 25
Finished Feb 09 06:33:28 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275203317 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress.3275203317
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_full_random.2184901515
Short name T671
Test name
Test status
Simulation time 78888103 ps
CPU time 1.46 seconds
Started Feb 09 06:33:13 AM UTC 25
Finished Feb 09 06:33:15 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184901515 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2184901515
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_intr_rand_pgm.1573264644
Short name T670
Test name
Test status
Simulation time 74976673 ps
CPU time 1.55 seconds
Started Feb 09 06:33:08 AM UTC 25
Finished Feb 09 06:33:11 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573264644 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1573264644
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_intr_with_filter_rand_intr_event.670089825
Short name T595
Test name
Test status
Simulation time 33207268 ps
CPU time 2.05 seconds
Started Feb 09 06:33:11 AM UTC 25
Finished Feb 09 06:33:15 AM UTC 25
Peak memory 198748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670089825 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.670089825
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_rand_intr_trigger.1161692556
Short name T614
Test name
Test status
Simulation time 726036708 ps
CPU time 2.49 seconds
Started Feb 09 06:33:11 AM UTC 25
Finished Feb 09 06:33:15 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161692556 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.1161692556
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_random_dout_din.1638137200
Short name T667
Test name
Test status
Simulation time 82545999 ps
CPU time 1.8 seconds
Started Feb 09 06:33:07 AM UTC 25
Finished Feb 09 06:33:10 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638137200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.gpio_random_dout_din.1638137200
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1284613642
Short name T669
Test name
Test status
Simulation time 129081217 ps
CPU time 1.54 seconds
Started Feb 09 06:33:08 AM UTC 25
Finished Feb 09 06:33:11 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284613642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup_pulldown.1284613642
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3803121121
Short name T675
Test name
Test status
Simulation time 486465338 ps
CPU time 8.42 seconds
Started Feb 09 06:33:12 AM UTC 25
Finished Feb 09 06:33:21 AM UTC 25
Peak memory 198716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803121121 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_long_reg_writes_reg_reads.3803121121
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_smoke.3867220028
Short name T666
Test name
Test status
Simulation time 51090094 ps
CPU time 1.36 seconds
Started Feb 09 06:33:05 AM UTC 25
Finished Feb 09 06:33:08 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867220028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.gpio_smoke.3867220028
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_smoke_no_pullup_pulldown.4190687148
Short name T665
Test name
Test status
Simulation time 180237301 ps
CPU time 1.28 seconds
Started Feb 09 06:33:05 AM UTC 25
Finished Feb 09 06:33:07 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190687148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4190687148
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/47.gpio_stress_all.840544377
Short name T87
Test name
Test status
Simulation time 2663423931 ps
CPU time 41.29 seconds
Started Feb 09 06:33:16 AM UTC 25
Finished Feb 09 06:33:59 AM UTC 25
Peak memory 201036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840544377 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all.840544377
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_alert_test.3785138421
Short name T687
Test name
Test status
Simulation time 27382425 ps
CPU time 0.85 seconds
Started Feb 09 06:33:34 AM UTC 25
Finished Feb 09 06:33:36 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785138421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3785138421
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_dout_din_regs_random_rw.2205995440
Short name T679
Test name
Test status
Simulation time 38269102 ps
CPU time 1.33 seconds
Started Feb 09 06:33:22 AM UTC 25
Finished Feb 09 06:33:25 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205995440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2205995440
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_filter_stress.1004826398
Short name T93
Test name
Test status
Simulation time 777860512 ps
CPU time 36.35 seconds
Started Feb 09 06:33:27 AM UTC 25
Finished Feb 09 06:34:05 AM UTC 25
Peak memory 198728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004826398 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress.1004826398
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_full_random.1752493649
Short name T685
Test name
Test status
Simulation time 46038009 ps
CPU time 1 seconds
Started Feb 09 06:33:30 AM UTC 25
Finished Feb 09 06:33:33 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752493649 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1752493649
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_intr_rand_pgm.2170390408
Short name T680
Test name
Test status
Simulation time 184757268 ps
CPU time 1.37 seconds
Started Feb 09 06:33:24 AM UTC 25
Finished Feb 09 06:33:27 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170390408 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2170390408
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1069730770
Short name T684
Test name
Test status
Simulation time 93305791 ps
CPU time 4.74 seconds
Started Feb 09 06:33:25 AM UTC 25
Finished Feb 09 06:33:31 AM UTC 25
Peak memory 198960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069730770 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1069730770
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_rand_intr_trigger.645876719
Short name T683
Test name
Test status
Simulation time 86797377 ps
CPU time 3.77 seconds
Started Feb 09 06:33:25 AM UTC 25
Finished Feb 09 06:33:30 AM UTC 25
Peak memory 198724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645876719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.645876719
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_random_dout_din.790459625
Short name T677
Test name
Test status
Simulation time 45574574 ps
CPU time 1.37 seconds
Started Feb 09 06:33:21 AM UTC 25
Finished Feb 09 06:33:23 AM UTC 25
Peak memory 198388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790459625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.gpio_random_dout_din.790459625
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3675900914
Short name T678
Test name
Test status
Simulation time 21750765 ps
CPU time 1.02 seconds
Started Feb 09 06:33:22 AM UTC 25
Finished Feb 09 06:33:24 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675900914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup_pulldown.3675900914
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4176875619
Short name T686
Test name
Test status
Simulation time 548816294 ps
CPU time 5.38 seconds
Started Feb 09 06:33:28 AM UTC 25
Finished Feb 09 06:33:35 AM UTC 25
Peak memory 198736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176875619 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_long_reg_writes_reg_reads.4176875619
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_smoke.283951338
Short name T674
Test name
Test status
Simulation time 120679046 ps
CPU time 1.66 seconds
Started Feb 09 06:33:17 AM UTC 25
Finished Feb 09 06:33:20 AM UTC 25
Peak memory 198332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283951338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 48.gpio_smoke.283951338
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_smoke_no_pullup_pulldown.143549516
Short name T676
Test name
Test status
Simulation time 61449472 ps
CPU time 1.47 seconds
Started Feb 09 06:33:19 AM UTC 25
Finished Feb 09 06:33:22 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143549516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.143549516
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_stress_all.391956805
Short name T94
Test name
Test status
Simulation time 1839676973 ps
CPU time 35.02 seconds
Started Feb 09 06:33:32 AM UTC 25
Finished Feb 09 06:34:08 AM UTC 25
Peak memory 200768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391956805 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all.391956805
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/48.gpio_stress_all_with_rand_reset.1887853107
Short name T712
Test name
Test status
Simulation time 1357658429337 ps
CPU time 1312.75 seconds
Started Feb 09 06:33:32 AM UTC 25
Finished Feb 09 06:55:38 AM UTC 25
Peak memory 209932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1887853107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stres
s_all_with_rand_reset.1887853107
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_alert_test.1199665118
Short name T92
Test name
Test status
Simulation time 118463444 ps
CPU time 0.85 seconds
Started Feb 09 06:34:02 AM UTC 25
Finished Feb 09 06:34:04 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199665118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1199665118
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_dout_din_regs_random_rw.1233960146
Short name T692
Test name
Test status
Simulation time 154165981 ps
CPU time 1.34 seconds
Started Feb 09 06:33:42 AM UTC 25
Finished Feb 09 06:33:44 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233960146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1233960146
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_filter_stress.3947222146
Short name T88
Test name
Test status
Simulation time 2617545843 ps
CPU time 8.5 seconds
Started Feb 09 06:33:50 AM UTC 25
Finished Feb 09 06:34:00 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947222146 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stress.3947222146
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_full_random.3532155474
Short name T89
Test name
Test status
Simulation time 692053363 ps
CPU time 1.3 seconds
Started Feb 09 06:33:59 AM UTC 25
Finished Feb 09 06:34:02 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532155474 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3532155474
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_intr_rand_pgm.1030147976
Short name T693
Test name
Test status
Simulation time 429620466 ps
CPU time 2.15 seconds
Started Feb 09 06:33:43 AM UTC 25
Finished Feb 09 06:33:46 AM UTC 25
Peak memory 198668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030147976 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1030147976
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2788940641
Short name T695
Test name
Test status
Simulation time 316695873 ps
CPU time 3.82 seconds
Started Feb 09 06:33:47 AM UTC 25
Finished Feb 09 06:33:52 AM UTC 25
Peak memory 200920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788940641 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2788940641
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_rand_intr_trigger.1966413192
Short name T694
Test name
Test status
Simulation time 791848576 ps
CPU time 3.28 seconds
Started Feb 09 06:33:45 AM UTC 25
Finished Feb 09 06:33:49 AM UTC 25
Peak memory 198664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966413192 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.1966413192
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_random_dout_din.1547411267
Short name T690
Test name
Test status
Simulation time 44451595 ps
CPU time 1.05 seconds
Started Feb 09 06:33:39 AM UTC 25
Finished Feb 09 06:33:41 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547411267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.gpio_random_dout_din.1547411267
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.566754620
Short name T691
Test name
Test status
Simulation time 165317947 ps
CPU time 1.45 seconds
Started Feb 09 06:33:40 AM UTC 25
Finished Feb 09 06:33:43 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566754620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_pulldown.566754620
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2107468969
Short name T90
Test name
Test status
Simulation time 499288200 ps
CPU time 7.76 seconds
Started Feb 09 06:33:53 AM UTC 25
Finished Feb 09 06:34:02 AM UTC 25
Peak memory 200728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107468969 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_long_reg_writes_reg_reads.2107468969
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_smoke.1868211212
Short name T688
Test name
Test status
Simulation time 47077717 ps
CPU time 1.13 seconds
Started Feb 09 06:33:36 AM UTC 25
Finished Feb 09 06:33:38 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868211212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.gpio_smoke.1868211212
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_smoke_no_pullup_pulldown.394684256
Short name T689
Test name
Test status
Simulation time 62206666 ps
CPU time 1.19 seconds
Started Feb 09 06:33:37 AM UTC 25
Finished Feb 09 06:33:39 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394684256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.394684256
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/49.gpio_stress_all.2653004767
Short name T705
Test name
Test status
Simulation time 33009769079 ps
CPU time 157.54 seconds
Started Feb 09 06:33:59 AM UTC 25
Finished Feb 09 06:36:40 AM UTC 25
Peak memory 200856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653004767 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all.2653004767
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_alert_test.2606539045
Short name T133
Test name
Test status
Simulation time 14253023 ps
CPU time 0.52 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 197604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606539045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2606539045
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_dout_din_regs_random_rw.315636887
Short name T31
Test name
Test status
Simulation time 90423298 ps
CPU time 0.69 seconds
Started Feb 09 06:28:33 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315636887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.315636887
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_filter_stress.693105559
Short name T268
Test name
Test status
Simulation time 11884039682 ps
CPU time 25.9 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:29:01 AM UTC 25
Peak memory 198856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693105559 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress.693105559
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_full_random.781174371
Short name T27
Test name
Test status
Simulation time 106165539 ps
CPU time 0.64 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781174371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.781174371
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_intr_rand_pgm.342522221
Short name T152
Test name
Test status
Simulation time 345546245 ps
CPU time 1.19 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342522221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.342522221
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3910355659
Short name T15
Test name
Test status
Simulation time 71675742 ps
CPU time 2.63 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:38 AM UTC 25
Peak memory 198828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910355659 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3910355659
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_rand_intr_trigger.1160851105
Short name T17
Test name
Test status
Simulation time 113903403 ps
CPU time 2.93 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:38 AM UTC 25
Peak memory 198744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160851105 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.1160851105
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_random_dout_din.1097007183
Short name T22
Test name
Test status
Simulation time 52436219 ps
CPU time 0.66 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097007183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.gpio_random_dout_din.1097007183
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2197175205
Short name T25
Test name
Test status
Simulation time 237368230 ps
CPU time 0.88 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197175205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_pulldown.2197175205
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2855389898
Short name T13
Test name
Test status
Simulation time 47564533 ps
CPU time 1.74 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 198376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855389898 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_long_reg_writes_reg_reads.2855389898
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_smoke.3827428507
Short name T21
Test name
Test status
Simulation time 40821374 ps
CPU time 0.95 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827428507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.gpio_smoke.3827428507
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_smoke_no_pullup_pulldown.707001176
Short name T24
Test name
Test status
Simulation time 387448161 ps
CPU time 0.91 seconds
Started Feb 09 06:28:32 AM UTC 25
Finished Feb 09 06:28:35 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707001176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.707001176
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_stress_all.2529159701
Short name T320
Test name
Test status
Simulation time 4392034210 ps
CPU time 45.69 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:29:22 AM UTC 25
Peak memory 200776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529159701 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all.2529159701
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/5.gpio_stress_all_with_rand_reset.2009188967
Short name T83
Test name
Test status
Simulation time 144121248669 ps
CPU time 813.43 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:42:17 AM UTC 25
Peak memory 206668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2009188967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress
_all_with_rand_reset.2009188967
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_alert_test.2188102686
Short name T148
Test name
Test status
Simulation time 36868667 ps
CPU time 0.54 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188102686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2188102686
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_dout_din_regs_random_rw.663495893
Short name T154
Test name
Test status
Simulation time 107374275 ps
CPU time 0.81 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663495893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_
regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.663495893
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_filter_stress.1351726190
Short name T207
Test name
Test status
Simulation time 362352263 ps
CPU time 9.11 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 198716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351726190 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress.1351726190
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_full_random.3585235021
Short name T2
Test name
Test status
Simulation time 133985210 ps
CPU time 0.76 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585235021 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3585235021
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_intr_rand_pgm.4036694798
Short name T14
Test name
Test status
Simulation time 31442224 ps
CPU time 0.8 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036694798 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4036694798
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2025299678
Short name T16
Test name
Test status
Simulation time 148776270 ps
CPU time 1.51 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:38 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025299678 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2025299678
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_rand_intr_trigger.944440023
Short name T157
Test name
Test status
Simulation time 149451217 ps
CPU time 2.04 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944440023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.944440023
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_random_dout_din.779455702
Short name T150
Test name
Test status
Simulation time 33238266 ps
CPU time 0.68 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779455702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.gpio_random_dout_din.779455702
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.718804997
Short name T153
Test name
Test status
Simulation time 75569931 ps
CPU time 0.81 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 198452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718804997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_pulldown.718804997
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1749822277
Short name T155
Test name
Test status
Simulation time 47429205 ps
CPU time 1.6 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:28:38 AM UTC 25
Peak memory 200396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749822277 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_long_reg_writes_reg_reads.1749822277
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_smoke.973110308
Short name T151
Test name
Test status
Simulation time 73557210 ps
CPU time 0.81 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:36 AM UTC 25
Peak memory 197600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973110308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.gpio_smoke.973110308
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_smoke_no_pullup_pulldown.355263996
Short name T12
Test name
Test status
Simulation time 60644115 ps
CPU time 1.15 seconds
Started Feb 09 06:28:34 AM UTC 25
Finished Feb 09 06:28:37 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355263996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.355263996
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_stress_all.1267579210
Short name T496
Test name
Test status
Simulation time 7743473652 ps
CPU time 169.81 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:31:28 AM UTC 25
Peak memory 200892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267579210 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all.1267579210
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/6.gpio_stress_all_with_rand_reset.3015153487
Short name T709
Test name
Test status
Simulation time 225977857740 ps
CPU time 1123.99 seconds
Started Feb 09 06:28:35 AM UTC 25
Finished Feb 09 06:47:33 AM UTC 25
Peak memory 206580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3015153487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress
_all_with_rand_reset.3015153487
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_alert_test.3500769326
Short name T162
Test name
Test status
Simulation time 17508796 ps
CPU time 0.68 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500769326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3500769326
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_dout_din_regs_random_rw.3455015461
Short name T158
Test name
Test status
Simulation time 118386955 ps
CPU time 0.87 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455015461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3455015461
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_filter_stress.3222348836
Short name T224
Test name
Test status
Simulation time 480778703 ps
CPU time 11.45 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:49 AM UTC 25
Peak memory 198688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222348836 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress.3222348836
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_full_random.768689940
Short name T164
Test name
Test status
Simulation time 52545886 ps
CPU time 0.95 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768689940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.768689940
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_intr_rand_pgm.1352701730
Short name T161
Test name
Test status
Simulation time 399220597 ps
CPU time 1.25 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352701730 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1352701730
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_intr_with_filter_rand_intr_event.789858237
Short name T172
Test name
Test status
Simulation time 82938305 ps
CPU time 3.05 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789858237 -assert nopostproc +UVM_
TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.789858237
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_rand_intr_trigger.3043909073
Short name T173
Test name
Test status
Simulation time 502906623 ps
CPU time 2.95 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043909073 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.3043909073
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_random_dout_din.1808954618
Short name T160
Test name
Test status
Simulation time 27347637 ps
CPU time 1.17 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808954618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.gpio_random_dout_din.1808954618
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3431540170
Short name T159
Test name
Test status
Simulation time 44528548 ps
CPU time 0.91 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431540170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_pulldown.3431540170
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1655166807
Short name T183
Test name
Test status
Simulation time 302827722 ps
CPU time 4.22 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655166807 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_long_reg_writes_reg_reads.1655166807
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_smoke.3376905976
Short name T134
Test name
Test status
Simulation time 278235836 ps
CPU time 0.93 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376905976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.gpio_smoke.3376905976
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_smoke_no_pullup_pulldown.1003106531
Short name T156
Test name
Test status
Simulation time 53306319 ps
CPU time 0.88 seconds
Started Feb 09 06:28:36 AM UTC 25
Finished Feb 09 06:28:39 AM UTC 25
Peak memory 198360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003106531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1003106531
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/7.gpio_stress_all.3677477764
Short name T381
Test name
Test status
Simulation time 11980134939 ps
CPU time 80.54 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:30:00 AM UTC 25
Peak memory 200892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677477764 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all.3677477764
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_alert_test.4172609303
Short name T176
Test name
Test status
Simulation time 11925948 ps
CPU time 0.71 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172609303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4172609303
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_dout_din_regs_random_rw.1685725066
Short name T163
Test name
Test status
Simulation time 100929233 ps
CPU time 0.69 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685725066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1685725066
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_filter_stress.1080563478
Short name T193
Test name
Test status
Simulation time 1010764355 ps
CPU time 4.3 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:44 AM UTC 25
Peak memory 198796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080563478 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.1080563478
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_full_random.3606734718
Short name T174
Test name
Test status
Simulation time 27194527 ps
CPU time 0.66 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606734718 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3606734718
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_intr_rand_pgm.3570266192
Short name T168
Test name
Test status
Simulation time 70793700 ps
CPU time 0.84 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570266192 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3570266192
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3546979370
Short name T171
Test name
Test status
Simulation time 29617206 ps
CPU time 1.27 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546979370 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3546979370
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_rand_intr_trigger.3783227216
Short name T170
Test name
Test status
Simulation time 90157589 ps
CPU time 1.07 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:41 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783227216 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.3783227216
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_random_dout_din.2148288303
Short name T166
Test name
Test status
Simulation time 53832876 ps
CPU time 0.92 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148288303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_d
out_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.gpio_random_dout_din.2148288303
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.86633473
Short name T169
Test name
Test status
Simulation time 63649344 ps
CPU time 1.19 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86633473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_pulldown.86633473
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2669695998
Short name T184
Test name
Test status
Simulation time 129475638 ps
CPU time 1.76 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669695998 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_long_reg_writes_reg_reads.2669695998
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_smoke.916459523
Short name T165
Test name
Test status
Simulation time 113508916 ps
CPU time 0.97 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916459523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.gpio_smoke.916459523
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_smoke_no_pullup_pulldown.4201522515
Short name T167
Test name
Test status
Simulation time 46362926 ps
CPU time 0.94 seconds
Started Feb 09 06:28:38 AM UTC 25
Finished Feb 09 06:28:40 AM UTC 25
Peak memory 198260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201522515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.4201522515
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_stress_all.2794560128
Short name T461
Test name
Test status
Simulation time 53051726237 ps
CPU time 135.15 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:30:57 AM UTC 25
Peak memory 201024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794560128 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all.2794560128
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/8.gpio_stress_all_with_rand_reset.1066950101
Short name T80
Test name
Test status
Simulation time 131210897111 ps
CPU time 589.6 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:38:37 AM UTC 25
Peak memory 215380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=100000000
00 +stress_seq=gpio_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1066950101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress
_all_with_rand_reset.1066950101
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_alert_test.291024398
Short name T186
Test name
Test status
Simulation time 13685034 ps
CPU time 0.51 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291024398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.291024398
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_dout_din_regs_random_rw.1057608631
Short name T177
Test name
Test status
Simulation time 36656443 ps
CPU time 0.72 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057608631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din
_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1057608631
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_dout_din_regs_random_rw/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_filter_stress.788402872
Short name T258
Test name
Test status
Simulation time 4869038250 ps
CPU time 16.81 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:58 AM UTC 25
Peak memory 198792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788402872 -assert nopostproc +UVM_TESTNAME=gpio_b
ase_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.788402872
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_filter_stress/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_full_random.4038876784
Short name T187
Test name
Test status
Simulation time 239798456 ps
CPU time 0.64 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:28:43 AM UTC 25
Peak memory 198396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038876784 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4038876784
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_full_random/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_intr_rand_pgm.806214170
Short name T180
Test name
Test status
Simulation time 90211060 ps
CPU time 0.71 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806214170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.806214170
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_intr_rand_pgm/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4082919377
Short name T185
Test name
Test status
Simulation time 58165418 ps
CPU time 1.38 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082919377 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4082919377
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_rand_intr_trigger.2599749749
Short name T196
Test name
Test status
Simulation time 456496964 ps
CPU time 3.3 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:44 AM UTC 25
Peak memory 198680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599749749 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.2599749749
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_rand_intr_trigger/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_random_dout_din.959301535
Short name T182
Test name
Test status
Simulation time 491196996 ps
CPU time 1.22 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959301535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_do
ut_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.gpio_random_dout_din.959301535
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_random_dout_din/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.791880856
Short name T181
Test name
Test status
Simulation time 58546937 ps
CPU time 1.19 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791880856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_pulldown.791880856
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2550121669
Short name T203
Test name
Test status
Simulation time 107607503 ps
CPU time 4.31 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:46 AM UTC 25
Peak memory 200704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550121669 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_long_reg_writes_reg_reads.2550121669
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_smoke.2650269584
Short name T179
Test name
Test status
Simulation time 146907826 ps
CPU time 1.01 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650269584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.gpio_smoke.2650269584
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_smoke/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_smoke_no_pullup_pulldown.1256952905
Short name T178
Test name
Test status
Simulation time 152949312 ps
CPU time 1.12 seconds
Started Feb 09 06:28:39 AM UTC 25
Finished Feb 09 06:28:42 AM UTC 25
Peak memory 198332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256952905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1256952905
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/default/9.gpio_stress_all.2956598663
Short name T332
Test name
Test status
Simulation time 1644250781 ps
CPU time 45.42 seconds
Started Feb 09 06:28:41 AM UTC 25
Finished Feb 09 06:29:28 AM UTC 25
Peak memory 200848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956598663 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/gpio-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all.2956598663
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.951797400
Short name T845
Test name
Test status
Simulation time 53312028 ps
CPU time 1.77 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:01 AM UTC 25
Peak memory 198636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951797400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 0.gpio_smoke_en_cdc_prim.951797400
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837371075
Short name T841
Test name
Test status
Simulation time 27463610 ps
CPU time 0.99 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 197940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837371075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837371075
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3049843755
Short name T843
Test name
Test status
Simulation time 120953807 ps
CPU time 1.51 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 198448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049843755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3049843755
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876697382
Short name T846
Test name
Test status
Simulation time 177116060 ps
CPU time 1.77 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:01 AM UTC 25
Peak memory 198560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876697382 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876697382
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1709435035
Short name T862
Test name
Test status
Simulation time 74951827 ps
CPU time 1.56 seconds
Started Feb 09 06:35:01 AM UTC 25
Finished Feb 09 06:35:04 AM UTC 25
Peak memory 198624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709435035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1709435035
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1002624591
Short name T861
Test name
Test status
Simulation time 82497567 ps
CPU time 1.5 seconds
Started Feb 09 06:35:01 AM UTC 25
Finished Feb 09 06:35:04 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002624591 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1002624591
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.533495441
Short name T860
Test name
Test status
Simulation time 150676024 ps
CPU time 1.3 seconds
Started Feb 09 06:35:01 AM UTC 25
Finished Feb 09 06:35:04 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533495441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 11.gpio_smoke_en_cdc_prim.533495441
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768713881
Short name T863
Test name
Test status
Simulation time 36571122 ps
CPU time 1.51 seconds
Started Feb 09 06:35:02 AM UTC 25
Finished Feb 09 06:35:04 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768713881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768713881
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2362002611
Short name T868
Test name
Test status
Simulation time 130208060 ps
CPU time 1.52 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362002611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2362002611
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3893241766
Short name T867
Test name
Test status
Simulation time 287005479 ps
CPU time 1.29 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:05 AM UTC 25
Peak memory 198620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893241766 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3893241766
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2011923483
Short name T866
Test name
Test status
Simulation time 42226792 ps
CPU time 1.21 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:05 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011923483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2011923483
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594797506
Short name T874
Test name
Test status
Simulation time 73269337 ps
CPU time 1.86 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594797506 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594797506
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.665116249
Short name T865
Test name
Test status
Simulation time 60819705 ps
CPU time 1.12 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:05 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665116249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 14.gpio_smoke_en_cdc_prim.665116249
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558388466
Short name T869
Test name
Test status
Simulation time 525295050 ps
CPU time 1.35 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558388466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558388466
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3437162999
Short name T872
Test name
Test status
Simulation time 62360471 ps
CPU time 1.63 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437162999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3437162999
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539963272
Short name T864
Test name
Test status
Simulation time 31173903 ps
CPU time 1.08 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:05 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539963272 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539963272
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4269916705
Short name T870
Test name
Test status
Simulation time 411796598 ps
CPU time 1.37 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269916705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4269916705
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509150314
Short name T873
Test name
Test status
Simulation time 160920239 ps
CPU time 1.6 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509150314 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509150314
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2444436276
Short name T871
Test name
Test status
Simulation time 169817103 ps
CPU time 1.36 seconds
Started Feb 09 06:35:03 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444436276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2444436276
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908943533
Short name T877
Test name
Test status
Simulation time 59223188 ps
CPU time 1.11 seconds
Started Feb 09 06:35:04 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908943533 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908943533
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1269058692
Short name T875
Test name
Test status
Simulation time 113880904 ps
CPU time 1.01 seconds
Started Feb 09 06:35:04 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269058692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1269058692
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3646846923
Short name T876
Test name
Test status
Simulation time 110692123 ps
CPU time 1.01 seconds
Started Feb 09 06:35:04 AM UTC 25
Finished Feb 09 06:35:06 AM UTC 25
Peak memory 198200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646846923 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3646846923
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2003711797
Short name T878
Test name
Test status
Simulation time 36281466 ps
CPU time 1.49 seconds
Started Feb 09 06:35:04 AM UTC 25
Finished Feb 09 06:35:07 AM UTC 25
Peak memory 198628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003711797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2003711797
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4090057472
Short name T881
Test name
Test status
Simulation time 37945378 ps
CPU time 1.28 seconds
Started Feb 09 06:35:05 AM UTC 25
Finished Feb 09 06:35:08 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090057472 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4090057472
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1356944071
Short name T840
Test name
Test status
Simulation time 201283502 ps
CPU time 0.94 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 197988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356944071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1356944071
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532510010
Short name T844
Test name
Test status
Simulation time 33864361 ps
CPU time 1.46 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532510010 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532510010
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2661116069
Short name T880
Test name
Test status
Simulation time 29915356 ps
CPU time 1.1 seconds
Started Feb 09 06:35:05 AM UTC 25
Finished Feb 09 06:35:08 AM UTC 25
Peak memory 198624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661116069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2661116069
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471878642
Short name T879
Test name
Test status
Simulation time 99483073 ps
CPU time 1.06 seconds
Started Feb 09 06:35:05 AM UTC 25
Finished Feb 09 06:35:08 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471878642 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471878642
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2649889188
Short name T892
Test name
Test status
Simulation time 655572959 ps
CPU time 2.01 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649889188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2649889188
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114880556
Short name T887
Test name
Test status
Simulation time 235021430 ps
CPU time 1.6 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114880556 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114880556
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3645495194
Short name T884
Test name
Test status
Simulation time 58218542 ps
CPU time 1.34 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:09 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645495194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3645495194
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2012257799
Short name T882
Test name
Test status
Simulation time 40085939 ps
CPU time 1.24 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:09 AM UTC 25
Peak memory 198620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012257799 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2012257799
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3238600109
Short name T885
Test name
Test status
Simulation time 52749009 ps
CPU time 1.4 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:09 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238600109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3238600109
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3133337938
Short name T890
Test name
Test status
Simulation time 62901729 ps
CPU time 1.76 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133337938 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3133337938
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.597441654
Short name T888
Test name
Test status
Simulation time 59839122 ps
CPU time 1.71 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597441654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 24.gpio_smoke_en_cdc_prim.597441654
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913043093
Short name T883
Test name
Test status
Simulation time 134581920 ps
CPU time 1.01 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:09 AM UTC 25
Peak memory 198512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913043093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913043093
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.207753579
Short name T891
Test name
Test status
Simulation time 173784134 ps
CPU time 1.73 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207753579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 25.gpio_smoke_en_cdc_prim.207753579
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.202873867
Short name T893
Test name
Test status
Simulation time 56509568 ps
CPU time 1.74 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202873867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.202873867
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3903002719
Short name T886
Test name
Test status
Simulation time 89387152 ps
CPU time 1.38 seconds
Started Feb 09 06:35:07 AM UTC 25
Finished Feb 09 06:35:09 AM UTC 25
Peak memory 198672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903002719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3903002719
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2434086710
Short name T889
Test name
Test status
Simulation time 305297628 ps
CPU time 1.93 seconds
Started Feb 09 06:35:08 AM UTC 25
Finished Feb 09 06:35:11 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434086710 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2434086710
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3117850513
Short name T894
Test name
Test status
Simulation time 32427829 ps
CPU time 0.97 seconds
Started Feb 09 06:35:08 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117850513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3117850513
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486305941
Short name T896
Test name
Test status
Simulation time 271889439 ps
CPU time 1.47 seconds
Started Feb 09 06:35:08 AM UTC 25
Finished Feb 09 06:35:11 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486305941 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486305941
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1599537920
Short name T895
Test name
Test status
Simulation time 36299279 ps
CPU time 1.09 seconds
Started Feb 09 06:35:08 AM UTC 25
Finished Feb 09 06:35:10 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599537920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1599537920
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587288962
Short name T898
Test name
Test status
Simulation time 110346057 ps
CPU time 1.37 seconds
Started Feb 09 06:35:09 AM UTC 25
Finished Feb 09 06:35:12 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587288962 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587288962
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3586575650
Short name T899
Test name
Test status
Simulation time 90988880 ps
CPU time 2.05 seconds
Started Feb 09 06:35:09 AM UTC 25
Finished Feb 09 06:35:12 AM UTC 25
Peak memory 198748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586575650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3586575650
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.399556348
Short name T897
Test name
Test status
Simulation time 35298697 ps
CPU time 1.16 seconds
Started Feb 09 06:35:09 AM UTC 25
Finished Feb 09 06:35:12 AM UTC 25
Peak memory 198512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399556348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.399556348
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.828020124
Short name T842
Test name
Test status
Simulation time 49418443 ps
CPU time 1.28 seconds
Started Feb 09 06:34:58 AM UTC 25
Finished Feb 09 06:35:00 AM UTC 25
Peak memory 198636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828020124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 3.gpio_smoke_en_cdc_prim.828020124
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730125161
Short name T847
Test name
Test status
Simulation time 148980808 ps
CPU time 1.31 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:01 AM UTC 25
Peak memory 198560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730125161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730125161
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2694915102
Short name T908
Test name
Test status
Simulation time 204963462 ps
CPU time 2.15 seconds
Started Feb 09 06:35:10 AM UTC 25
Finished Feb 09 06:35:14 AM UTC 25
Peak memory 198896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694915102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2694915102
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2654478932
Short name T904
Test name
Test status
Simulation time 62361408 ps
CPU time 1.69 seconds
Started Feb 09 06:35:10 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654478932 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2654478932
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2672197110
Short name T900
Test name
Test status
Simulation time 29131884 ps
CPU time 1.34 seconds
Started Feb 09 06:35:10 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672197110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2672197110
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3241050508
Short name T903
Test name
Test status
Simulation time 59110487 ps
CPU time 1.49 seconds
Started Feb 09 06:35:10 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241050508 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3241050508
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2701323833
Short name T901
Test name
Test status
Simulation time 228361407 ps
CPU time 1.3 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701323833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2701323833
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1377233580
Short name T902
Test name
Test status
Simulation time 135147868 ps
CPU time 1.4 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377233580 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1377233580
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1259812838
Short name T907
Test name
Test status
Simulation time 138469882 ps
CPU time 1.55 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259812838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1259812838
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2287307455
Short name T906
Test name
Test status
Simulation time 70758388 ps
CPU time 1.46 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287307455 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2287307455
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2353166130
Short name T909
Test name
Test status
Simulation time 284137122 ps
CPU time 2.12 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:14 AM UTC 25
Peak memory 198840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353166130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2353166130
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408093791
Short name T905
Test name
Test status
Simulation time 35320160 ps
CPU time 1.32 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:13 AM UTC 25
Peak memory 198480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408093791 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408093791
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2893727713
Short name T910
Test name
Test status
Simulation time 688163615 ps
CPU time 2.14 seconds
Started Feb 09 06:35:11 AM UTC 25
Finished Feb 09 06:35:14 AM UTC 25
Peak memory 198784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893727713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2893727713
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159167034
Short name T914
Test name
Test status
Simulation time 47673204 ps
CPU time 1.83 seconds
Started Feb 09 06:35:12 AM UTC 25
Finished Feb 09 06:35:15 AM UTC 25
Peak memory 198368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159167034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159167034
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.815697742
Short name T911
Test name
Test status
Simulation time 83790085 ps
CPU time 1.35 seconds
Started Feb 09 06:35:12 AM UTC 25
Finished Feb 09 06:35:14 AM UTC 25
Peak memory 198308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815697742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 36.gpio_smoke_en_cdc_prim.815697742
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3316528588
Short name T912
Test name
Test status
Simulation time 206022666 ps
CPU time 1.26 seconds
Started Feb 09 06:35:12 AM UTC 25
Finished Feb 09 06:35:14 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316528588 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3316528588
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2051198264
Short name T915
Test name
Test status
Simulation time 382199634 ps
CPU time 1.8 seconds
Started Feb 09 06:35:12 AM UTC 25
Finished Feb 09 06:35:15 AM UTC 25
Peak memory 198636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051198264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2051198264
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1153997598
Short name T913
Test name
Test status
Simulation time 37177900 ps
CPU time 1.34 seconds
Started Feb 09 06:35:12 AM UTC 25
Finished Feb 09 06:35:15 AM UTC 25
Peak memory 198620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153997598 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1153997598
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1388216306
Short name T916
Test name
Test status
Simulation time 67281966 ps
CPU time 1.34 seconds
Started Feb 09 06:35:13 AM UTC 25
Finished Feb 09 06:35:16 AM UTC 25
Peak memory 198604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388216306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1388216306
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916114619
Short name T917
Test name
Test status
Simulation time 137054073 ps
CPU time 1.44 seconds
Started Feb 09 06:35:13 AM UTC 25
Finished Feb 09 06:35:16 AM UTC 25
Peak memory 198544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916114619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916114619
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3174810673
Short name T924
Test name
Test status
Simulation time 100465601 ps
CPU time 1.82 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174810673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3174810673
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4092281507
Short name T919
Test name
Test status
Simulation time 63091435 ps
CPU time 1.23 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092281507 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4092281507
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1153046971
Short name T848
Test name
Test status
Simulation time 104993870 ps
CPU time 1.35 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:01 AM UTC 25
Peak memory 198504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153046971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1153046971
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258640683
Short name T849
Test name
Test status
Simulation time 57635388 ps
CPU time 1.45 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258640683 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258640683
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1075733489
Short name T918
Test name
Test status
Simulation time 20469833 ps
CPU time 1.08 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075733489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1075733489
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912609424
Short name T922
Test name
Test status
Simulation time 164261571 ps
CPU time 1.58 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912609424 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3912609424
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3237075895
Short name T921
Test name
Test status
Simulation time 24700311 ps
CPU time 1.23 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237075895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3237075895
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4091646085
Short name T920
Test name
Test status
Simulation time 36989531 ps
CPU time 1.09 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091646085 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4091646085
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1655007264
Short name T926
Test name
Test status
Simulation time 41419580 ps
CPU time 1.69 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655007264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1655007264
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4035975852
Short name T925
Test name
Test status
Simulation time 48515917 ps
CPU time 1.49 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035975852 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4035975852
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3921422955
Short name T923
Test name
Test status
Simulation time 137137399 ps
CPU time 1.47 seconds
Started Feb 09 06:35:14 AM UTC 25
Finished Feb 09 06:35:17 AM UTC 25
Peak memory 198628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921422955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3921422955
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3704757506
Short name T928
Test name
Test status
Simulation time 102793615 ps
CPU time 1.16 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:18 AM UTC 25
Peak memory 198532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704757506 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3704757506
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1502149115
Short name T930
Test name
Test status
Simulation time 22475507 ps
CPU time 1.16 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:18 AM UTC 25
Peak memory 198644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502149115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1502149115
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279270783
Short name T932
Test name
Test status
Simulation time 307021783 ps
CPU time 1.69 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:19 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279270783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en
_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279270783
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4270802278
Short name T927
Test name
Test status
Simulation time 46496798 ps
CPU time 1 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:18 AM UTC 25
Peak memory 198684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270802278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4270802278
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2565308348
Short name T929
Test name
Test status
Simulation time 79596287 ps
CPU time 1.08 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:18 AM UTC 25
Peak memory 198620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565308348 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2565308348
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.544716642
Short name T933
Test name
Test status
Simulation time 78603098 ps
CPU time 2.03 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:19 AM UTC 25
Peak memory 199096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544716642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 46.gpio_smoke_en_cdc_prim.544716642
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777577393
Short name T931
Test name
Test status
Simulation time 107672372 ps
CPU time 1.25 seconds
Started Feb 09 06:35:16 AM UTC 25
Finished Feb 09 06:35:18 AM UTC 25
Peak memory 198560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777577393 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777577393
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.300299955
Short name T935
Test name
Test status
Simulation time 346669892 ps
CPU time 1.62 seconds
Started Feb 09 06:35:17 AM UTC 25
Finished Feb 09 06:35:20 AM UTC 25
Peak memory 198448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300299955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 47.gpio_smoke_en_cdc_prim.300299955
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3996646752
Short name T936
Test name
Test status
Simulation time 49145745 ps
CPU time 1.93 seconds
Started Feb 09 06:35:17 AM UTC 25
Finished Feb 09 06:35:20 AM UTC 25
Peak memory 198400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996646752 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3996646752
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.970374396
Short name T934
Test name
Test status
Simulation time 295217538 ps
CPU time 1.42 seconds
Started Feb 09 06:35:17 AM UTC 25
Finished Feb 09 06:35:20 AM UTC 25
Peak memory 198348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970374396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 48.gpio_smoke_en_cdc_prim.970374396
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2457149654
Short name T939
Test name
Test status
Simulation time 103118775 ps
CPU time 1.69 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:35:21 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457149654 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2457149654
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.903043040
Short name T937
Test name
Test status
Simulation time 161269744 ps
CPU time 1.04 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:35:20 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903043040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 49.gpio_smoke_en_cdc_prim.903043040
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470642025
Short name T938
Test name
Test status
Simulation time 57492047 ps
CPU time 1.46 seconds
Started Feb 09 06:35:18 AM UTC 25
Finished Feb 09 06:35:21 AM UTC 25
Peak memory 198512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470642025 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470642025
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.138846714
Short name T853
Test name
Test status
Simulation time 288357581 ps
CPU time 1.51 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138846714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 5.gpio_smoke_en_cdc_prim.138846714
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515060864
Short name T850
Test name
Test status
Simulation time 274073651 ps
CPU time 1.38 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515060864 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515060864
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.272923122
Short name T851
Test name
Test status
Simulation time 77179185 ps
CPU time 1.43 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272923122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_log
/dev/null -cm_name 6.gpio_smoke_en_cdc_prim.272923122
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1951256573
Short name T852
Test name
Test status
Simulation time 212494482 ps
CPU time 1.47 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951256573 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1951256573
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3834072711
Short name T854
Test name
Test status
Simulation time 625406994 ps
CPU time 1.68 seconds
Started Feb 09 06:34:59 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834072711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3834072711
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.5369939
Short name T856
Test name
Test status
Simulation time 30576724 ps
CPU time 1.02 seconds
Started Feb 09 06:35:00 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5369939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_c
dc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.5369939
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3727940976
Short name T855
Test name
Test status
Simulation time 41165704 ps
CPU time 0.96 seconds
Started Feb 09 06:35:00 AM UTC 25
Finished Feb 09 06:35:02 AM UTC 25
Peak memory 198564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727940976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3727940976
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937088859
Short name T858
Test name
Test status
Simulation time 57450401 ps
CPU time 1.89 seconds
Started Feb 09 06:35:00 AM UTC 25
Finished Feb 09 06:35:03 AM UTC 25
Peak memory 198572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937088859 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937088859
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3660593038
Short name T857
Test name
Test status
Simulation time 115080285 ps
CPU time 1.13 seconds
Started Feb 09 06:35:00 AM UTC 25
Finished Feb 09 06:35:03 AM UTC 25
Peak memory 198456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660593038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims.vdb -cm_lo
g /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3660593038
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_smoke_en_cdc_prim/latest

Test location /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045362688
Short name T859
Test name
Test status
Simulation time 189801448 ps
CPU time 1.13 seconds
Started Feb 09 06:35:01 AM UTC 25
Finished Feb 09 06:35:04 AM UTC 25
Peak memory 198568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/gpio-sim-vcs/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045362688 -assert nopostproc +UVM_TESTNAME=gpio_base_test
+UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/gpio-sim-vcs/coverage/e
n_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045362688
Directory /workspaces/repo/scratch/os_regression/gpio-sim-vcs/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest