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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 937
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1941391764 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:33 PM PDT 24 163764376 ps
T758 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2114867350 Apr 23 12:29:46 PM PDT 24 Apr 23 12:29:48 PM PDT 24 21387688 ps
T759 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1114417172 Apr 23 12:23:25 PM PDT 24 Apr 23 12:23:27 PM PDT 24 45706578 ps
T760 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1161398905 Apr 23 12:29:54 PM PDT 24 Apr 23 12:29:56 PM PDT 24 49338233 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1082511690 Apr 23 12:22:33 PM PDT 24 Apr 23 12:22:35 PM PDT 24 144476504 ps
T761 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4040187727 Apr 23 12:23:55 PM PDT 24 Apr 23 12:23:58 PM PDT 24 99113096 ps
T762 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.352674923 Apr 23 12:29:36 PM PDT 24 Apr 23 12:29:38 PM PDT 24 32297682 ps
T763 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3096980772 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:33 PM PDT 24 27810689 ps
T764 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3373378389 Apr 23 12:30:04 PM PDT 24 Apr 23 12:30:05 PM PDT 24 16636214 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2427799850 Apr 23 12:23:20 PM PDT 24 Apr 23 12:23:22 PM PDT 24 82951603 ps
T766 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3403523884 Apr 23 12:23:21 PM PDT 24 Apr 23 12:23:22 PM PDT 24 147308366 ps
T767 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2112080449 Apr 23 12:29:52 PM PDT 24 Apr 23 12:29:53 PM PDT 24 12898235 ps
T768 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3850221085 Apr 23 12:29:39 PM PDT 24 Apr 23 12:29:40 PM PDT 24 73729769 ps
T769 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2894911010 Apr 23 12:29:56 PM PDT 24 Apr 23 12:29:57 PM PDT 24 34424179 ps
T770 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.69747521 Apr 23 12:29:40 PM PDT 24 Apr 23 12:29:42 PM PDT 24 70583544 ps
T771 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2686088109 Apr 23 12:21:52 PM PDT 24 Apr 23 12:21:53 PM PDT 24 105523585 ps
T772 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2904826791 Apr 23 12:29:36 PM PDT 24 Apr 23 12:29:40 PM PDT 24 823086020 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3902346538 Apr 23 12:29:40 PM PDT 24 Apr 23 12:29:42 PM PDT 24 110890343 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2733782569 Apr 23 12:23:40 PM PDT 24 Apr 23 12:23:41 PM PDT 24 12179837 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.935380919 Apr 23 12:22:33 PM PDT 24 Apr 23 12:22:35 PM PDT 24 23039579 ps
T776 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1251887021 Apr 23 12:29:50 PM PDT 24 Apr 23 12:29:52 PM PDT 24 25137461 ps
T777 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2294351012 Apr 23 12:24:11 PM PDT 24 Apr 23 12:24:15 PM PDT 24 273349152 ps
T43 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1165201411 Apr 23 12:29:35 PM PDT 24 Apr 23 12:29:38 PM PDT 24 122480548 ps
T778 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2268416081 Apr 23 12:29:53 PM PDT 24 Apr 23 12:29:54 PM PDT 24 14709248 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2674651859 Apr 23 12:23:23 PM PDT 24 Apr 23 12:23:25 PM PDT 24 10759849 ps
T780 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3783144822 Apr 23 12:23:28 PM PDT 24 Apr 23 12:23:30 PM PDT 24 93726683 ps
T781 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1752684339 Apr 23 12:29:51 PM PDT 24 Apr 23 12:29:53 PM PDT 24 33406189 ps
T782 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4017502132 Apr 23 12:29:35 PM PDT 24 Apr 23 12:29:37 PM PDT 24 21394629 ps
T783 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3970313458 Apr 23 12:29:52 PM PDT 24 Apr 23 12:29:54 PM PDT 24 67908919 ps
T784 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1091446173 Apr 23 12:29:51 PM PDT 24 Apr 23 12:29:53 PM PDT 24 259650038 ps
T785 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.555970552 Apr 23 12:29:43 PM PDT 24 Apr 23 12:29:46 PM PDT 24 119199104 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.438414970 Apr 23 12:29:42 PM PDT 24 Apr 23 12:29:45 PM PDT 24 266633240 ps
T787 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3304978516 Apr 23 12:29:36 PM PDT 24 Apr 23 12:29:38 PM PDT 24 88561325 ps
T39 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1558753890 Apr 23 12:29:40 PM PDT 24 Apr 23 12:29:42 PM PDT 24 87459985 ps
T788 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3891533980 Apr 23 12:29:52 PM PDT 24 Apr 23 12:29:54 PM PDT 24 300793409 ps
T789 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2600529491 Apr 23 12:29:51 PM PDT 24 Apr 23 12:29:53 PM PDT 24 33554764 ps
T790 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.82798375 Apr 23 12:20:11 PM PDT 24 Apr 23 12:20:13 PM PDT 24 102069269 ps
T40 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3754758332 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:31 PM PDT 24 121113340 ps
T791 /workspace/coverage/cover_reg_top/4.gpio_intr_test.265595261 Apr 23 12:24:15 PM PDT 24 Apr 23 12:24:17 PM PDT 24 18191775 ps
T792 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2761561337 Apr 23 12:29:54 PM PDT 24 Apr 23 12:29:55 PM PDT 24 15128346 ps
T793 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1532799891 Apr 23 12:29:56 PM PDT 24 Apr 23 12:29:58 PM PDT 24 19330970 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.296896340 Apr 23 12:29:49 PM PDT 24 Apr 23 12:29:50 PM PDT 24 16655275 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.60462861 Apr 23 12:23:21 PM PDT 24 Apr 23 12:23:23 PM PDT 24 76388752 ps
T796 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3959590549 Apr 23 12:29:40 PM PDT 24 Apr 23 12:29:42 PM PDT 24 77402742 ps
T797 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4257792940 Apr 23 12:29:52 PM PDT 24 Apr 23 12:29:54 PM PDT 24 50939223 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2046427628 Apr 23 12:18:52 PM PDT 24 Apr 23 12:18:54 PM PDT 24 138940926 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.35985332 Apr 23 12:29:39 PM PDT 24 Apr 23 12:29:41 PM PDT 24 58249912 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2194352479 Apr 23 12:23:21 PM PDT 24 Apr 23 12:23:23 PM PDT 24 29736537 ps
T801 /workspace/coverage/cover_reg_top/47.gpio_intr_test.280831687 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:03 PM PDT 24 49344460 ps
T802 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1034250812 Apr 23 12:29:36 PM PDT 24 Apr 23 12:29:38 PM PDT 24 27837136 ps
T803 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2755577425 Apr 23 12:18:02 PM PDT 24 Apr 23 12:18:05 PM PDT 24 44320582 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2807526734 Apr 23 12:18:53 PM PDT 24 Apr 23 12:18:54 PM PDT 24 113436122 ps
T805 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3548572325 Apr 23 12:23:25 PM PDT 24 Apr 23 12:23:27 PM PDT 24 27908524 ps
T806 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2419594141 Apr 23 12:29:41 PM PDT 24 Apr 23 12:29:42 PM PDT 24 39989283 ps
T807 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.517355356 Apr 23 12:23:32 PM PDT 24 Apr 23 12:23:34 PM PDT 24 446134341 ps
T808 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2767468155 Apr 23 12:29:42 PM PDT 24 Apr 23 12:29:44 PM PDT 24 90881583 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.596882559 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:33 PM PDT 24 84689389 ps
T810 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2706182611 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:03 PM PDT 24 17900186 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.133220019 Apr 23 12:29:46 PM PDT 24 Apr 23 12:29:49 PM PDT 24 194132524 ps
T812 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3721829800 Apr 23 12:24:10 PM PDT 24 Apr 23 12:24:18 PM PDT 24 82305584 ps
T813 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3737063645 Apr 23 12:29:38 PM PDT 24 Apr 23 12:29:41 PM PDT 24 223079578 ps
T814 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1204776605 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:32 PM PDT 24 308524640 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.962335937 Apr 23 12:29:48 PM PDT 24 Apr 23 12:29:50 PM PDT 24 78906880 ps
T816 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2329028770 Apr 23 12:29:43 PM PDT 24 Apr 23 12:29:45 PM PDT 24 102799008 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.777002994 Apr 23 12:24:08 PM PDT 24 Apr 23 12:24:12 PM PDT 24 21251819 ps
T818 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3676764294 Apr 23 12:29:48 PM PDT 24 Apr 23 12:29:49 PM PDT 24 41845880 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.274565622 Apr 23 12:29:48 PM PDT 24 Apr 23 12:29:49 PM PDT 24 13378505 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2693012808 Apr 23 12:23:20 PM PDT 24 Apr 23 12:23:22 PM PDT 24 52546095 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1521797018 Apr 23 12:29:35 PM PDT 24 Apr 23 12:29:37 PM PDT 24 68701710 ps
T822 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2887729041 Apr 23 12:23:24 PM PDT 24 Apr 23 12:23:26 PM PDT 24 22380065 ps
T823 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2536888810 Apr 23 12:21:01 PM PDT 24 Apr 23 12:21:02 PM PDT 24 31546437 ps
T824 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1493484144 Apr 23 12:29:39 PM PDT 24 Apr 23 12:29:40 PM PDT 24 62267547 ps
T825 /workspace/coverage/cover_reg_top/26.gpio_intr_test.465690840 Apr 23 12:29:53 PM PDT 24 Apr 23 12:29:54 PM PDT 24 37349661 ps
T826 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2401483881 Apr 23 12:29:35 PM PDT 24 Apr 23 12:29:38 PM PDT 24 405431890 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.153151908 Apr 23 12:29:36 PM PDT 24 Apr 23 12:29:38 PM PDT 24 93528342 ps
T828 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3499070163 Apr 23 12:29:55 PM PDT 24 Apr 23 12:29:56 PM PDT 24 52174531 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3271694771 Apr 23 12:29:45 PM PDT 24 Apr 23 12:29:47 PM PDT 24 40633167 ps
T830 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3052168314 Apr 23 12:23:28 PM PDT 24 Apr 23 12:23:29 PM PDT 24 35332987 ps
T831 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3484498159 Apr 23 12:23:28 PM PDT 24 Apr 23 12:23:29 PM PDT 24 44944464 ps
T95 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1817658599 Apr 23 12:29:39 PM PDT 24 Apr 23 12:29:40 PM PDT 24 18686515 ps
T832 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3215285320 Apr 23 12:29:52 PM PDT 24 Apr 23 12:29:54 PM PDT 24 17151382 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4180381757 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:34 PM PDT 24 59291610 ps
T97 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1217297567 Apr 23 12:23:24 PM PDT 24 Apr 23 12:23:26 PM PDT 24 14584817 ps
T834 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1316792409 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:33 PM PDT 24 13788315 ps
T835 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1589696811 Apr 23 12:29:39 PM PDT 24 Apr 23 12:29:40 PM PDT 24 26233674 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3751500024 Apr 23 12:21:54 PM PDT 24 Apr 23 12:21:55 PM PDT 24 51114336 ps
T837 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.45941233 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:34 PM PDT 24 261768233 ps
T838 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013175175 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:03 PM PDT 24 56173848 ps
T839 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.456445702 Apr 23 12:21:32 PM PDT 24 Apr 23 12:21:34 PM PDT 24 62301758 ps
T840 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3568553226 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:04 PM PDT 24 304740883 ps
T841 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4229862338 Apr 23 12:23:41 PM PDT 24 Apr 23 12:23:42 PM PDT 24 137707568 ps
T842 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.255630129 Apr 23 12:23:57 PM PDT 24 Apr 23 12:23:59 PM PDT 24 65267184 ps
T843 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1479325127 Apr 23 12:30:04 PM PDT 24 Apr 23 12:30:06 PM PDT 24 38651332 ps
T844 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1567264050 Apr 23 12:24:10 PM PDT 24 Apr 23 12:24:14 PM PDT 24 104547708 ps
T845 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1203114612 Apr 23 12:23:51 PM PDT 24 Apr 23 12:23:54 PM PDT 24 295561692 ps
T846 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908037678 Apr 23 12:23:57 PM PDT 24 Apr 23 12:24:00 PM PDT 24 34884596 ps
T847 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998047494 Apr 23 12:21:38 PM PDT 24 Apr 23 12:21:40 PM PDT 24 36747340 ps
T848 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4198285212 Apr 23 12:18:49 PM PDT 24 Apr 23 12:18:50 PM PDT 24 52884924 ps
T849 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3372353934 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:34 PM PDT 24 179901476 ps
T850 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2396954459 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 123102299 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4284370284 Apr 23 12:30:05 PM PDT 24 Apr 23 12:30:07 PM PDT 24 31507317 ps
T852 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3831189613 Apr 23 12:30:02 PM PDT 24 Apr 23 12:30:04 PM PDT 24 94246124 ps
T853 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4197704573 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 231453211 ps
T854 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3795521566 Apr 23 12:23:23 PM PDT 24 Apr 23 12:23:26 PM PDT 24 433069607 ps
T855 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2489684242 Apr 23 12:30:00 PM PDT 24 Apr 23 12:30:03 PM PDT 24 100354841 ps
T856 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1438391951 Apr 23 12:22:02 PM PDT 24 Apr 23 12:22:03 PM PDT 24 38703527 ps
T857 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.873475635 Apr 23 12:24:11 PM PDT 24 Apr 23 12:24:15 PM PDT 24 48243076 ps
T858 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2295324763 Apr 23 12:20:17 PM PDT 24 Apr 23 12:20:20 PM PDT 24 200545785 ps
T859 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604012513 Apr 23 12:23:35 PM PDT 24 Apr 23 12:23:38 PM PDT 24 335774115 ps
T860 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466841306 Apr 23 12:30:06 PM PDT 24 Apr 23 12:30:08 PM PDT 24 64782455 ps
T861 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2385577356 Apr 23 12:30:00 PM PDT 24 Apr 23 12:30:03 PM PDT 24 146783892 ps
T862 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773357190 Apr 23 12:24:08 PM PDT 24 Apr 23 12:24:17 PM PDT 24 360599617 ps
T863 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1468258676 Apr 23 12:30:10 PM PDT 24 Apr 23 12:30:12 PM PDT 24 95571010 ps
T864 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2923568853 Apr 23 12:18:48 PM PDT 24 Apr 23 12:18:49 PM PDT 24 170298744 ps
T865 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854357440 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:34 PM PDT 24 40617355 ps
T866 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1518027934 Apr 23 12:18:44 PM PDT 24 Apr 23 12:18:45 PM PDT 24 56190383 ps
T867 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2276385926 Apr 23 12:23:36 PM PDT 24 Apr 23 12:23:38 PM PDT 24 215212713 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2899968131 Apr 23 12:23:26 PM PDT 24 Apr 23 12:23:27 PM PDT 24 175979531 ps
T869 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616442211 Apr 23 12:24:11 PM PDT 24 Apr 23 12:24:15 PM PDT 24 58312764 ps
T870 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1198274756 Apr 23 12:19:44 PM PDT 24 Apr 23 12:19:46 PM PDT 24 52071906 ps
T871 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2260535143 Apr 23 12:23:57 PM PDT 24 Apr 23 12:23:59 PM PDT 24 37517265 ps
T872 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1818856456 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:01 PM PDT 24 431074175 ps
T873 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217493939 Apr 23 12:29:58 PM PDT 24 Apr 23 12:30:00 PM PDT 24 117581758 ps
T874 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2818877754 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:34 PM PDT 24 65859884 ps
T875 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193750400 Apr 23 12:30:02 PM PDT 24 Apr 23 12:30:05 PM PDT 24 1485608749 ps
T876 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2194850322 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:01 PM PDT 24 29833539 ps
T877 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2944447700 Apr 23 12:30:09 PM PDT 24 Apr 23 12:30:11 PM PDT 24 209706046 ps
T878 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3537753242 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:04 PM PDT 24 79206955 ps
T879 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2884144079 Apr 23 12:29:56 PM PDT 24 Apr 23 12:29:59 PM PDT 24 54282854 ps
T880 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539020858 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:05 PM PDT 24 23047359 ps
T881 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2625001470 Apr 23 12:23:36 PM PDT 24 Apr 23 12:23:39 PM PDT 24 100934281 ps
T882 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2757850064 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:06 PM PDT 24 60589825 ps
T883 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.472587316 Apr 23 12:23:29 PM PDT 24 Apr 23 12:23:31 PM PDT 24 125500954 ps
T884 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2352239546 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:01 PM PDT 24 60495767 ps
T885 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.501251548 Apr 23 12:30:05 PM PDT 24 Apr 23 12:30:08 PM PDT 24 116073112 ps
T886 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602834307 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:34 PM PDT 24 199122112 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1274395216 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:06 PM PDT 24 231991520 ps
T888 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2236695081 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:06 PM PDT 24 193609982 ps
T889 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2591055222 Apr 23 12:24:15 PM PDT 24 Apr 23 12:24:17 PM PDT 24 318005796 ps
T890 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284440904 Apr 23 12:30:01 PM PDT 24 Apr 23 12:30:03 PM PDT 24 40438435 ps
T891 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154672542 Apr 23 12:21:57 PM PDT 24 Apr 23 12:21:59 PM PDT 24 222998640 ps
T892 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1001798251 Apr 23 12:23:32 PM PDT 24 Apr 23 12:23:34 PM PDT 24 171496773 ps
T893 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1876806574 Apr 23 12:24:08 PM PDT 24 Apr 23 12:24:12 PM PDT 24 170309338 ps
T894 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4214495349 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:34 PM PDT 24 674128974 ps
T895 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908721404 Apr 23 12:21:19 PM PDT 24 Apr 23 12:21:21 PM PDT 24 60448053 ps
T896 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3888244086 Apr 23 12:21:27 PM PDT 24 Apr 23 12:21:29 PM PDT 24 57218908 ps
T897 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2924140450 Apr 23 12:22:58 PM PDT 24 Apr 23 12:23:01 PM PDT 24 166246000 ps
T898 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4283626945 Apr 23 12:30:02 PM PDT 24 Apr 23 12:30:05 PM PDT 24 442515559 ps
T899 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4041779378 Apr 23 12:24:08 PM PDT 24 Apr 23 12:24:12 PM PDT 24 76013320 ps
T900 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3100065787 Apr 23 12:23:26 PM PDT 24 Apr 23 12:23:28 PM PDT 24 66062584 ps
T901 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.274397602 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:01 PM PDT 24 302859432 ps
T902 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749581598 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:02 PM PDT 24 153802758 ps
T903 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3440323384 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:02 PM PDT 24 64569275 ps
T904 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1955716183 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:05 PM PDT 24 46933572 ps
T905 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1578798950 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 35286582 ps
T906 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2393177222 Apr 23 12:30:04 PM PDT 24 Apr 23 12:30:06 PM PDT 24 43718894 ps
T907 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2366356915 Apr 23 12:23:31 PM PDT 24 Apr 23 12:23:34 PM PDT 24 74265831 ps
T908 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1689280565 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:35 PM PDT 24 270614567 ps
T909 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3251266539 Apr 23 12:23:32 PM PDT 24 Apr 23 12:23:35 PM PDT 24 57400756 ps
T910 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1358700010 Apr 23 12:30:07 PM PDT 24 Apr 23 12:30:09 PM PDT 24 465160022 ps
T911 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479621384 Apr 23 12:23:25 PM PDT 24 Apr 23 12:23:27 PM PDT 24 150617659 ps
T912 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.399153851 Apr 23 12:21:29 PM PDT 24 Apr 23 12:21:30 PM PDT 24 97742943 ps
T913 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1977921296 Apr 23 12:22:34 PM PDT 24 Apr 23 12:22:36 PM PDT 24 175249103 ps
T914 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.983271046 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 22478480 ps
T915 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737593459 Apr 23 12:29:59 PM PDT 24 Apr 23 12:30:02 PM PDT 24 176214501 ps
T916 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3125732186 Apr 23 12:19:38 PM PDT 24 Apr 23 12:19:40 PM PDT 24 51420989 ps
T917 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2704255889 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:06 PM PDT 24 35114159 ps
T918 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3306098236 Apr 23 12:23:57 PM PDT 24 Apr 23 12:24:00 PM PDT 24 57842308 ps
T919 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3723608785 Apr 23 12:23:22 PM PDT 24 Apr 23 12:23:25 PM PDT 24 132999251 ps
T920 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2666631309 Apr 23 12:24:10 PM PDT 24 Apr 23 12:24:15 PM PDT 24 372881891 ps
T921 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1358359839 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 74721813 ps
T922 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1498473557 Apr 23 12:22:12 PM PDT 24 Apr 23 12:22:14 PM PDT 24 205965395 ps
T923 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.34561478 Apr 23 12:23:56 PM PDT 24 Apr 23 12:23:58 PM PDT 24 292572845 ps
T924 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549899543 Apr 23 12:30:00 PM PDT 24 Apr 23 12:30:02 PM PDT 24 37194997 ps
T925 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747746543 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 110529441 ps
T926 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1661239244 Apr 23 12:19:52 PM PDT 24 Apr 23 12:19:54 PM PDT 24 182219999 ps
T927 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3260584285 Apr 23 12:23:48 PM PDT 24 Apr 23 12:23:51 PM PDT 24 77227637 ps
T928 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2111293300 Apr 23 12:23:37 PM PDT 24 Apr 23 12:23:39 PM PDT 24 97420466 ps
T929 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.965220559 Apr 23 12:18:47 PM PDT 24 Apr 23 12:18:49 PM PDT 24 42889127 ps
T930 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4254527776 Apr 23 12:30:03 PM PDT 24 Apr 23 12:30:06 PM PDT 24 204546786 ps
T931 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557987277 Apr 23 12:30:11 PM PDT 24 Apr 23 12:30:13 PM PDT 24 104568539 ps
T932 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1349009095 Apr 23 12:21:32 PM PDT 24 Apr 23 12:21:34 PM PDT 24 89333747 ps
T933 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.212447904 Apr 23 12:30:04 PM PDT 24 Apr 23 12:30:06 PM PDT 24 330658499 ps
T934 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768170677 Apr 23 12:21:44 PM PDT 24 Apr 23 12:21:45 PM PDT 24 162835032 ps
T935 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156740998 Apr 23 12:23:54 PM PDT 24 Apr 23 12:23:56 PM PDT 24 208290437 ps
T936 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.87930539 Apr 23 12:29:58 PM PDT 24 Apr 23 12:29:59 PM PDT 24 30451960 ps
T937 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3893256895 Apr 23 12:30:00 PM PDT 24 Apr 23 12:30:03 PM PDT 24 114775058 ps

Test location /workspace/coverage/default/21.gpio_full_random.3239629293
Short name T16
Test name
Test status
Simulation time 129684955 ps
CPU time 1 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 196620 kb
Host smart-5ca82ba7-7ae2-4998-9b82-64b2cfba650d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239629293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3239629293
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.990623286
Short name T133
Test name
Test status
Simulation time 319492375 ps
CPU time 3.55 seconds
Started Apr 23 12:31:04 PM PDT 24
Finished Apr 23 12:31:09 PM PDT 24
Peak memory 198104 kb
Host smart-7ca326ea-04c9-4f3a-8179-d235adc93f51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990623286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.990623286
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.687241042
Short name T25
Test name
Test status
Simulation time 12099397350 ps
CPU time 169.59 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:33:02 PM PDT 24
Peak memory 198236 kb
Host smart-30e05bff-8b7f-4316-86b6-710900f43d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=687241042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.687241042
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3440081440
Short name T1
Test name
Test status
Simulation time 55550226859 ps
CPU time 143.62 seconds
Started Apr 23 12:31:04 PM PDT 24
Finished Apr 23 12:33:29 PM PDT 24
Peak memory 198264 kb
Host smart-c9e1875c-3a17-405f-9f15-89d665eeefef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440081440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3440081440
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1288714759
Short name T30
Test name
Test status
Simulation time 216077854 ps
CPU time 1.39 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:41 PM PDT 24
Peak memory 198120 kb
Host smart-597ede05-28d0-46f0-a5e7-95ffa860c025
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288714759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1288714759
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.536669154
Short name T86
Test name
Test status
Simulation time 68018800 ps
CPU time 0.63 seconds
Started Apr 23 12:24:03 PM PDT 24
Finished Apr 23 12:24:05 PM PDT 24
Peak memory 194148 kb
Host smart-0c0113ae-192e-45f7-af41-ba135b71dee6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536669154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.536669154
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1902932133
Short name T14
Test name
Test status
Simulation time 31836246 ps
CPU time 0.57 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 193748 kb
Host smart-2f0636af-8eee-49eb-aacd-303e217319b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902932133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1902932133
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2035688502
Short name T33
Test name
Test status
Simulation time 82427020 ps
CPU time 0.92 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 214264 kb
Host smart-c4fe7436-591d-44c6-9d0b-acf6447811c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035688502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2035688502
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1534413853
Short name T113
Test name
Test status
Simulation time 625127331 ps
CPU time 0.81 seconds
Started Apr 23 12:29:35 PM PDT 24
Finished Apr 23 12:29:37 PM PDT 24
Peak memory 196972 kb
Host smart-8af42b81-58df-46fd-b195-7197db8e46d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534413853 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1534413853
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1869254177
Short name T37
Test name
Test status
Simulation time 223549003 ps
CPU time 1.19 seconds
Started Apr 23 12:23:18 PM PDT 24
Finished Apr 23 12:23:21 PM PDT 24
Peak memory 197100 kb
Host smart-9baad17e-fa8e-4305-b915-4f13e81e9b3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869254177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1869254177
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1082511690
Short name T93
Test name
Test status
Simulation time 144476504 ps
CPU time 0.89 seconds
Started Apr 23 12:22:33 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 194280 kb
Host smart-744da145-e860-4314-a07b-de44145cff70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082511690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1082511690
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3418162819
Short name T755
Test name
Test status
Simulation time 2489022506 ps
CPU time 3.59 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:19:42 PM PDT 24
Peak memory 198056 kb
Host smart-b14ce543-f706-498b-bdd1-7557933ff7fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418162819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3418162819
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2807526734
Short name T804
Test name
Test status
Simulation time 113436122 ps
CPU time 0.58 seconds
Started Apr 23 12:18:53 PM PDT 24
Finished Apr 23 12:18:54 PM PDT 24
Peak memory 194288 kb
Host smart-0b73c828-b8f7-4783-8289-d0cd753f83e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807526734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2807526734
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.935380919
Short name T775
Test name
Test status
Simulation time 23039579 ps
CPU time 1.14 seconds
Started Apr 23 12:22:33 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 196124 kb
Host smart-81eb9734-1a86-4872-9ceb-9af9b6131504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935380919 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.935380919
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2563920286
Short name T89
Test name
Test status
Simulation time 32983590 ps
CPU time 0.59 seconds
Started Apr 23 12:23:39 PM PDT 24
Finished Apr 23 12:23:40 PM PDT 24
Peak memory 195492 kb
Host smart-94343db6-c9a8-4b9a-aeb8-f8e8f07c933c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563920286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2563920286
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2194352479
Short name T800
Test name
Test status
Simulation time 29736537 ps
CPU time 0.61 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 192852 kb
Host smart-d50e5aa0-7d6c-40df-8ce7-5c36e2af79d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194352479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2194352479
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2887729041
Short name T822
Test name
Test status
Simulation time 22380065 ps
CPU time 0.82 seconds
Started Apr 23 12:23:24 PM PDT 24
Finished Apr 23 12:23:26 PM PDT 24
Peak memory 196156 kb
Host smart-40fe704d-8c3e-45f2-8357-8c227cbf199a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887729041 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2887729041
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3643050673
Short name T730
Test name
Test status
Simulation time 90279884 ps
CPU time 1.32 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 197912 kb
Host smart-82e6c184-157e-429b-8f8a-76e1789997c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643050673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3643050673
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3393173395
Short name T29
Test name
Test status
Simulation time 403229750 ps
CPU time 1.09 seconds
Started Apr 23 12:22:33 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 195980 kb
Host smart-3f08f4c0-c8c2-4306-af8e-4594813db0ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393173395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3393173395
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3199409014
Short name T94
Test name
Test status
Simulation time 14196995 ps
CPU time 0.66 seconds
Started Apr 23 12:21:01 PM PDT 24
Finished Apr 23 12:21:03 PM PDT 24
Peak memory 194432 kb
Host smart-291a612d-4f17-4665-88b4-301fd8b334a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199409014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3199409014
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4083463480
Short name T753
Test name
Test status
Simulation time 2475234836 ps
CPU time 3.05 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 197176 kb
Host smart-9b8ebcc8-93e5-4369-ba0d-baa7f02da8c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083463480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4083463480
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2254492129
Short name T92
Test name
Test status
Simulation time 27803825 ps
CPU time 0.65 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 194868 kb
Host smart-53a59263-87a2-4f29-9e43-66443e61346c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254492129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2254492129
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2536888810
Short name T823
Test name
Test status
Simulation time 31546437 ps
CPU time 0.73 seconds
Started Apr 23 12:21:01 PM PDT 24
Finished Apr 23 12:21:02 PM PDT 24
Peak memory 197580 kb
Host smart-58367966-4d1e-4566-80c5-efba35b2ff3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536888810 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2536888810
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2733782569
Short name T774
Test name
Test status
Simulation time 12179837 ps
CPU time 0.6 seconds
Started Apr 23 12:23:40 PM PDT 24
Finished Apr 23 12:23:41 PM PDT 24
Peak memory 194264 kb
Host smart-e5367814-7eb0-4a01-ba04-7f65aaf6f72e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733782569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2733782569
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3548572325
Short name T805
Test name
Test status
Simulation time 27908524 ps
CPU time 0.57 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 193380 kb
Host smart-a192cf9f-9de2-474e-b677-70e90a4733ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548572325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3548572325
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3403523884
Short name T766
Test name
Test status
Simulation time 147308366 ps
CPU time 0.72 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 195860 kb
Host smart-2ef3ee02-c291-40bb-a68f-580804d5c919
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403523884 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3403523884
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3262448621
Short name T719
Test name
Test status
Simulation time 347285365 ps
CPU time 2.16 seconds
Started Apr 23 12:24:14 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 197788 kb
Host smart-80706d26-d155-4613-a7d5-0e661a9a9d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262448621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3262448621
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1034250812
Short name T802
Test name
Test status
Simulation time 27837136 ps
CPU time 0.68 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 197792 kb
Host smart-7f20f780-a43e-46e5-b9a7-f371af3fbb30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034250812 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1034250812
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2224838407
Short name T84
Test name
Test status
Simulation time 18496486 ps
CPU time 0.62 seconds
Started Apr 23 12:29:34 PM PDT 24
Finished Apr 23 12:29:36 PM PDT 24
Peak memory 193656 kb
Host smart-2dfd16d2-4aa1-4c89-b67e-5f124cfb963d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224838407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2224838407
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2899039000
Short name T713
Test name
Test status
Simulation time 18831995 ps
CPU time 0.59 seconds
Started Apr 23 12:29:42 PM PDT 24
Finished Apr 23 12:29:43 PM PDT 24
Peak memory 193944 kb
Host smart-49773950-798f-4f6b-92d4-b2c98c197692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899039000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2899039000
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2904826791
Short name T772
Test name
Test status
Simulation time 823086020 ps
CPU time 3.29 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 198108 kb
Host smart-d61e9c4e-375c-4d2b-8043-ffaf7675e54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904826791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2904826791
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1165201411
Short name T43
Test name
Test status
Simulation time 122480548 ps
CPU time 1.4 seconds
Started Apr 23 12:29:35 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 198028 kb
Host smart-b536e84c-402b-48de-b2de-bc037cfd38d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165201411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1165201411
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2417419427
Short name T723
Test name
Test status
Simulation time 154968926 ps
CPU time 0.98 seconds
Started Apr 23 12:29:41 PM PDT 24
Finished Apr 23 12:29:43 PM PDT 24
Peak memory 198004 kb
Host smart-216c78b8-b8fa-4902-9a2d-dc7178c386dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417419427 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2417419427
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1817658599
Short name T95
Test name
Test status
Simulation time 18686515 ps
CPU time 0.69 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 194904 kb
Host smart-dfe73ff5-c47a-46a8-b70b-2443a30971d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817658599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1817658599
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1589696811
Short name T835
Test name
Test status
Simulation time 26233674 ps
CPU time 0.61 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 193720 kb
Host smart-f27e56ad-b238-4d70-bf8e-46ea58d60ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589696811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1589696811
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2302890289
Short name T114
Test name
Test status
Simulation time 97901339 ps
CPU time 0.76 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 196012 kb
Host smart-8c973450-9a06-4710-a148-1767b7474b4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302890289 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2302890289
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.438414970
Short name T786
Test name
Test status
Simulation time 266633240 ps
CPU time 1.93 seconds
Started Apr 23 12:29:42 PM PDT 24
Finished Apr 23 12:29:45 PM PDT 24
Peak memory 198080 kb
Host smart-2059154a-8951-42c6-866b-0446dde0b2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438414970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.438414970
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3959590549
Short name T796
Test name
Test status
Simulation time 77402742 ps
CPU time 0.92 seconds
Started Apr 23 12:29:40 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 197944 kb
Host smart-533bbccd-cd21-4d95-b4d4-b1150d537c9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959590549 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3959590549
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2167822788
Short name T744
Test name
Test status
Simulation time 40092750 ps
CPU time 0.61 seconds
Started Apr 23 12:29:41 PM PDT 24
Finished Apr 23 12:29:43 PM PDT 24
Peak memory 194728 kb
Host smart-3d4da2f5-76dd-4c2a-91f3-70a7d2a4759d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167822788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2167822788
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1493484144
Short name T824
Test name
Test status
Simulation time 62267547 ps
CPU time 0.59 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 194376 kb
Host smart-93e8837b-a0f1-45c3-b41b-d961827f2860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493484144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1493484144
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.35985332
Short name T799
Test name
Test status
Simulation time 58249912 ps
CPU time 0.65 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:41 PM PDT 24
Peak memory 195372 kb
Host smart-c85b48eb-fb7c-4270-a209-9b829c3df084
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985332 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.gpio_same_csr_outstanding.35985332
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.364289515
Short name T712
Test name
Test status
Simulation time 166338036 ps
CPU time 1.13 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:41 PM PDT 24
Peak memory 197912 kb
Host smart-4c88c208-e508-485b-b96d-ab9c70d211be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364289515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.364289515
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1558753890
Short name T39
Test name
Test status
Simulation time 87459985 ps
CPU time 0.91 seconds
Started Apr 23 12:29:40 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 197244 kb
Host smart-be0adddc-668f-4971-9166-afc0f5145914
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558753890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1558753890
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1333336668
Short name T747
Test name
Test status
Simulation time 55744862 ps
CPU time 0.77 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 197992 kb
Host smart-783b0f30-ce58-43cb-8695-4355f3a773ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333336668 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1333336668
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2419594141
Short name T806
Test name
Test status
Simulation time 39989283 ps
CPU time 0.55 seconds
Started Apr 23 12:29:41 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 194660 kb
Host smart-791263c7-7534-4c05-b795-b0f1998c9f65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419594141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2419594141
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3251043803
Short name T710
Test name
Test status
Simulation time 24804654 ps
CPU time 0.59 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:44 PM PDT 24
Peak memory 193744 kb
Host smart-2ba3ee5b-e9a2-4e2e-a2ce-514b3d14bbe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251043803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3251043803
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3850221085
Short name T768
Test name
Test status
Simulation time 73729769 ps
CPU time 0.7 seconds
Started Apr 23 12:29:39 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 195568 kb
Host smart-01610dfc-b78e-47d5-8f94-2ec5e6f97630
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850221085 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3850221085
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.555970552
Short name T785
Test name
Test status
Simulation time 119199104 ps
CPU time 1.77 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:46 PM PDT 24
Peak memory 198060 kb
Host smart-86e949a6-ddc6-4b5a-91d1-d82eb0ff294b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555970552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.555970552
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2986996337
Short name T727
Test name
Test status
Simulation time 46114749 ps
CPU time 0.85 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:45 PM PDT 24
Peak memory 197064 kb
Host smart-863a12a2-267b-4ed2-80b2-9a1677019c7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986996337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2986996337
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2329028770
Short name T816
Test name
Test status
Simulation time 102799008 ps
CPU time 0.8 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:45 PM PDT 24
Peak memory 197920 kb
Host smart-1591dcd8-af40-454e-a19c-32ec072e7b66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329028770 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2329028770
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2397897322
Short name T83
Test name
Test status
Simulation time 10261758 ps
CPU time 0.57 seconds
Started Apr 23 12:29:46 PM PDT 24
Finished Apr 23 12:29:47 PM PDT 24
Peak memory 193668 kb
Host smart-aa0b0f9d-2e73-44e2-b6ac-1476171876a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397897322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2397897322
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.689214417
Short name T741
Test name
Test status
Simulation time 12243267 ps
CPU time 0.58 seconds
Started Apr 23 12:29:44 PM PDT 24
Finished Apr 23 12:29:45 PM PDT 24
Peak memory 193796 kb
Host smart-1d3d2ff7-5852-4afa-b5fd-fe6acb2978be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689214417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.689214417
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2091581850
Short name T110
Test name
Test status
Simulation time 116233074 ps
CPU time 0.88 seconds
Started Apr 23 12:29:42 PM PDT 24
Finished Apr 23 12:29:44 PM PDT 24
Peak memory 197504 kb
Host smart-c411cbec-143e-401f-a7c6-3c0897bd4d08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091581850 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2091581850
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3271694771
Short name T829
Test name
Test status
Simulation time 40633167 ps
CPU time 1.08 seconds
Started Apr 23 12:29:45 PM PDT 24
Finished Apr 23 12:29:47 PM PDT 24
Peak memory 198084 kb
Host smart-b73a9334-8a34-4530-805d-c08e62575db7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271694771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3271694771
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2767468155
Short name T808
Test name
Test status
Simulation time 90881583 ps
CPU time 1.15 seconds
Started Apr 23 12:29:42 PM PDT 24
Finished Apr 23 12:29:44 PM PDT 24
Peak memory 198016 kb
Host smart-0d2a20f3-da42-4455-9e49-39173af21969
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767468155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2767468155
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2114867350
Short name T758
Test name
Test status
Simulation time 21387688 ps
CPU time 0.72 seconds
Started Apr 23 12:29:46 PM PDT 24
Finished Apr 23 12:29:48 PM PDT 24
Peak memory 197916 kb
Host smart-8ea8992c-6634-4b79-910d-663d96e29b86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114867350 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2114867350
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2699858340
Short name T82
Test name
Test status
Simulation time 13331494 ps
CPU time 0.63 seconds
Started Apr 23 12:29:46 PM PDT 24
Finished Apr 23 12:29:47 PM PDT 24
Peak memory 194608 kb
Host smart-f9be9dcd-86d0-4d27-b845-874ca522acf8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699858340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2699858340
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3940905990
Short name T711
Test name
Test status
Simulation time 14238531 ps
CPU time 0.58 seconds
Started Apr 23 12:29:45 PM PDT 24
Finished Apr 23 12:29:46 PM PDT 24
Peak memory 193828 kb
Host smart-156cd857-bed0-4d72-9a1c-c263ff997472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940905990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3940905990
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2183754012
Short name T109
Test name
Test status
Simulation time 15988238 ps
CPU time 0.63 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 194792 kb
Host smart-be9f184e-db4b-4d6f-8d85-dc442f2ee7ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183754012 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2183754012
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.133220019
Short name T811
Test name
Test status
Simulation time 194132524 ps
CPU time 2.61 seconds
Started Apr 23 12:29:46 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 198092 kb
Host smart-32d016d0-02e8-4251-8ffa-3075f184af8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133220019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.133220019
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2733748658
Short name T28
Test name
Test status
Simulation time 49199179 ps
CPU time 0.89 seconds
Started Apr 23 12:29:45 PM PDT 24
Finished Apr 23 12:29:46 PM PDT 24
Peak memory 197308 kb
Host smart-54a8a866-4c11-4656-b198-1b29afebcbdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733748658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2733748658
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2698207259
Short name T721
Test name
Test status
Simulation time 102496111 ps
CPU time 0.85 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:45 PM PDT 24
Peak memory 197940 kb
Host smart-2bfdd75e-8bfd-4fc3-881f-b7e361a1994d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698207259 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2698207259
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.67956710
Short name T745
Test name
Test status
Simulation time 13163016 ps
CPU time 0.54 seconds
Started Apr 23 12:29:43 PM PDT 24
Finished Apr 23 12:29:44 PM PDT 24
Peak memory 193364 kb
Host smart-73b141a8-f6f7-46fc-8833-7b664209bfb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67956710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_
csr_rw.67956710
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2723821645
Short name T757
Test name
Test status
Simulation time 13266433 ps
CPU time 0.57 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 193664 kb
Host smart-109206c3-b42a-4b39-ae73-602fbeb207f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723821645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2723821645
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.557843842
Short name T116
Test name
Test status
Simulation time 42357854 ps
CPU time 0.75 seconds
Started Apr 23 12:29:45 PM PDT 24
Finished Apr 23 12:29:46 PM PDT 24
Peak memory 196664 kb
Host smart-061302ab-aa0f-4cc3-88cd-83256740d261
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557843842 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.557843842
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1938747393
Short name T739
Test name
Test status
Simulation time 2083900769 ps
CPU time 2.43 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:50 PM PDT 24
Peak memory 198072 kb
Host smart-4c93f8a7-7c9c-4f69-bb1c-735162a45b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938747393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1938747393
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3858928360
Short name T126
Test name
Test status
Simulation time 49570815 ps
CPU time 0.9 seconds
Started Apr 23 12:29:46 PM PDT 24
Finished Apr 23 12:29:48 PM PDT 24
Peak memory 197136 kb
Host smart-461eb519-fab9-498d-a2bd-39a03ad7c9a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858928360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3858928360
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.962335937
Short name T815
Test name
Test status
Simulation time 78906880 ps
CPU time 1.06 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:50 PM PDT 24
Peak memory 197920 kb
Host smart-ab382e2e-747c-4590-96c1-44c92dfac13d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962335937 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.962335937
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.296896340
Short name T794
Test name
Test status
Simulation time 16655275 ps
CPU time 0.6 seconds
Started Apr 23 12:29:49 PM PDT 24
Finished Apr 23 12:29:50 PM PDT 24
Peak memory 195016 kb
Host smart-c885aedb-2206-4da7-8a96-ea51dbb45ed8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296896340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.296896340
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3847454537
Short name T714
Test name
Test status
Simulation time 40880100 ps
CPU time 0.6 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:48 PM PDT 24
Peak memory 193728 kb
Host smart-61a7c2c0-cfa1-4ba6-862f-4a3288e73f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847454537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3847454537
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1881233907
Short name T107
Test name
Test status
Simulation time 42738785 ps
CPU time 0.87 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 196372 kb
Host smart-10bddda8-8204-46ce-9c99-ade2bf68d724
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881233907 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1881233907
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1249607492
Short name T729
Test name
Test status
Simulation time 115939188 ps
CPU time 2.41 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:52 PM PDT 24
Peak memory 198184 kb
Host smart-4d590095-dfb0-486e-87d8-362288820a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249607492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1249607492
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1453410114
Short name T38
Test name
Test status
Simulation time 303197699 ps
CPU time 1.13 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:50 PM PDT 24
Peak memory 197664 kb
Host smart-b63384f3-3c94-42a4-8175-48affb395501
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453410114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1453410114
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1642661108
Short name T722
Test name
Test status
Simulation time 49001658 ps
CPU time 1.12 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 198140 kb
Host smart-ed986457-c9fa-497c-9182-b978612a3977
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642661108 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1642661108
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.274565622
Short name T819
Test name
Test status
Simulation time 13378505 ps
CPU time 0.6 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 194796 kb
Host smart-e4dcdbae-4718-43b7-a2ce-ad10fcc3269a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274565622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.274565622
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3582031414
Short name T748
Test name
Test status
Simulation time 16597771 ps
CPU time 0.62 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 193744 kb
Host smart-b19bd813-2fe3-4875-9b05-a4d96bcabcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582031414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3582031414
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3676764294
Short name T818
Test name
Test status
Simulation time 41845880 ps
CPU time 0.75 seconds
Started Apr 23 12:29:48 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 196304 kb
Host smart-6e6f3d21-b497-4a8d-9fbc-957ee8f8d87c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676764294 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3676764294
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3037142850
Short name T738
Test name
Test status
Simulation time 57504377 ps
CPU time 1.68 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 198144 kb
Host smart-8522ccf5-973d-4ee3-90a0-ae889689bd1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037142850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3037142850
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3861310599
Short name T42
Test name
Test status
Simulation time 136470184 ps
CPU time 1.2 seconds
Started Apr 23 12:29:47 PM PDT 24
Finished Apr 23 12:29:49 PM PDT 24
Peak memory 198020 kb
Host smart-18c06158-ecd7-42b6-850e-35b044f0a9ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861310599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3861310599
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1251887021
Short name T776
Test name
Test status
Simulation time 25137461 ps
CPU time 0.78 seconds
Started Apr 23 12:29:50 PM PDT 24
Finished Apr 23 12:29:52 PM PDT 24
Peak memory 197896 kb
Host smart-9622ac8c-f8ff-4fe0-a997-0362631e3d84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251887021 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1251887021
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4257792940
Short name T797
Test name
Test status
Simulation time 50939223 ps
CPU time 0.63 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 194944 kb
Host smart-862f4891-b3e7-4a33-957e-3ef4bb4c2e65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257792940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4257792940
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2297586898
Short name T718
Test name
Test status
Simulation time 29783906 ps
CPU time 0.57 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 194456 kb
Host smart-023e3ed0-c9e5-40ee-ba07-8ae911389509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297586898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2297586898
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3970313458
Short name T783
Test name
Test status
Simulation time 67908919 ps
CPU time 0.86 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 196364 kb
Host smart-333a2839-6e97-4e86-9c07-ebd468ad1d57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970313458 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3970313458
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1091446173
Short name T784
Test name
Test status
Simulation time 259650038 ps
CPU time 1.49 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 198184 kb
Host smart-ecdfb1ed-2204-4888-9786-79d6f15f2a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091446173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1091446173
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3891533980
Short name T788
Test name
Test status
Simulation time 300793409 ps
CPU time 0.93 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 197280 kb
Host smart-461f3247-57a0-4475-9b6e-cc907472b820
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891533980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3891533980
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2427799850
Short name T765
Test name
Test status
Simulation time 82951603 ps
CPU time 0.66 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 194712 kb
Host smart-89bbf14c-079e-43c9-b0c1-7af05e35496e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427799850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2427799850
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1941391764
Short name T96
Test name
Test status
Simulation time 163764376 ps
CPU time 2.79 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 196980 kb
Host smart-56260f3c-ea15-4f4f-bc32-19b11a1b81f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941391764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1941391764
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1726590217
Short name T85
Test name
Test status
Simulation time 17005206 ps
CPU time 0.64 seconds
Started Apr 23 12:20:52 PM PDT 24
Finished Apr 23 12:20:53 PM PDT 24
Peak memory 193724 kb
Host smart-8dd20f0e-adae-467e-ac3c-84308fd533cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726590217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1726590217
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2840863824
Short name T735
Test name
Test status
Simulation time 108719544 ps
CPU time 0.92 seconds
Started Apr 23 12:24:02 PM PDT 24
Finished Apr 23 12:24:04 PM PDT 24
Peak memory 197144 kb
Host smart-4f412414-a75b-4bf2-b95c-5de1274e7248
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840863824 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2840863824
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1690709362
Short name T90
Test name
Test status
Simulation time 42432748 ps
CPU time 0.69 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:23:48 PM PDT 24
Peak memory 194008 kb
Host smart-48002a1f-a629-48b2-8ff1-a9a466ef03bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690709362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1690709362
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3052168314
Short name T830
Test name
Test status
Simulation time 35332987 ps
CPU time 0.66 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:23:29 PM PDT 24
Peak memory 192320 kb
Host smart-0c68f616-18d2-400a-bc75-afde57f48183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052168314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3052168314
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2046427628
Short name T798
Test name
Test status
Simulation time 138940926 ps
CPU time 0.86 seconds
Started Apr 23 12:18:52 PM PDT 24
Finished Apr 23 12:18:54 PM PDT 24
Peak memory 197864 kb
Host smart-ccc2cc2e-af1c-4523-a347-bcc2fce164df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046427628 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2046427628
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4180381757
Short name T833
Test name
Test status
Simulation time 59291610 ps
CPU time 3.01 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 197072 kb
Host smart-0e783057-ceef-4287-a83e-a74545e2399d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180381757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4180381757
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.60462861
Short name T795
Test name
Test status
Simulation time 76388752 ps
CPU time 0.85 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 196812 kb
Host smart-3e7588a0-4c59-45fd-a146-5d493070bb6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60462861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_tl_intg_err.60462861
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2600529491
Short name T789
Test name
Test status
Simulation time 33554764 ps
CPU time 0.58 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 194368 kb
Host smart-8f915177-78a5-45b7-9a7b-2b7ae33cd0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600529491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2600529491
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4239652428
Short name T750
Test name
Test status
Simulation time 14608624 ps
CPU time 0.61 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 194356 kb
Host smart-dc772efe-da3c-4fcf-91ed-5a6b986e07b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239652428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4239652428
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.704367880
Short name T746
Test name
Test status
Simulation time 40472721 ps
CPU time 0.6 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 193732 kb
Host smart-570dfe41-d02d-42bb-ac40-ecf10ac5953f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704367880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.704367880
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3215285320
Short name T832
Test name
Test status
Simulation time 17151382 ps
CPU time 0.61 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 194372 kb
Host smart-7c927a06-5fd4-4ebf-9e09-c997544418a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215285320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3215285320
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3084951827
Short name T725
Test name
Test status
Simulation time 29093861 ps
CPU time 0.57 seconds
Started Apr 23 12:29:54 PM PDT 24
Finished Apr 23 12:29:55 PM PDT 24
Peak memory 193696 kb
Host smart-62ad2b6d-5764-45ad-95a7-6f673d0bf3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084951827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3084951827
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1752684339
Short name T781
Test name
Test status
Simulation time 33406189 ps
CPU time 0.59 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 193728 kb
Host smart-9db4e0cc-70ed-4c4f-8596-11b874d52f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752684339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1752684339
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.465690840
Short name T825
Test name
Test status
Simulation time 37349661 ps
CPU time 0.58 seconds
Started Apr 23 12:29:53 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 193756 kb
Host smart-ad30f3d6-8fcf-4874-8b21-7cf86308b307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465690840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.465690840
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2268416081
Short name T778
Test name
Test status
Simulation time 14709248 ps
CPU time 0.59 seconds
Started Apr 23 12:29:53 PM PDT 24
Finished Apr 23 12:29:54 PM PDT 24
Peak memory 193804 kb
Host smart-b82845d4-bf87-43b3-8355-10cd8dd7acc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268416081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2268416081
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2701095962
Short name T743
Test name
Test status
Simulation time 42079745 ps
CPU time 0.58 seconds
Started Apr 23 12:29:51 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 193760 kb
Host smart-5bc40dfe-82bb-41cd-bda7-38bb02ad834b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701095962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2701095962
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2112080449
Short name T767
Test name
Test status
Simulation time 12898235 ps
CPU time 0.63 seconds
Started Apr 23 12:29:52 PM PDT 24
Finished Apr 23 12:29:53 PM PDT 24
Peak memory 193760 kb
Host smart-cca122d1-f5d4-431b-bc49-51d014b22bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112080449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2112080449
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.517355356
Short name T807
Test name
Test status
Simulation time 446134341 ps
CPU time 1.52 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 196820 kb
Host smart-e287af3f-a0c5-4670-b30c-2190319f1727
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517355356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.517355356
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.777002994
Short name T817
Test name
Test status
Simulation time 21251819 ps
CPU time 0.69 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 194352 kb
Host smart-003ef041-f62b-49d8-98b6-4a50ba7b8185
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777002994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.777002994
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2693012808
Short name T820
Test name
Test status
Simulation time 52546095 ps
CPU time 1.25 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 197768 kb
Host smart-4bc05696-5400-4bb1-b24a-e9bdff58014f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693012808 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2693012808
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2674651859
Short name T779
Test name
Test status
Simulation time 10759849 ps
CPU time 0.57 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:25 PM PDT 24
Peak memory 193712 kb
Host smart-d591fad2-0174-499c-bb74-663ae81de295
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674651859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2674651859
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2547429127
Short name T731
Test name
Test status
Simulation time 30180494 ps
CPU time 0.64 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 193440 kb
Host smart-a3ff33a0-1f07-40e6-985f-96289e8f6888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547429127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2547429127
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3484498159
Short name T831
Test name
Test status
Simulation time 44944464 ps
CPU time 0.71 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:23:29 PM PDT 24
Peak memory 195532 kb
Host smart-c446813a-b43e-46ab-a4c3-ba7b3e5d56f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484498159 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3484498159
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3783144822
Short name T780
Test name
Test status
Simulation time 93726683 ps
CPU time 1.07 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:23:30 PM PDT 24
Peak memory 197580 kb
Host smart-67a363bf-e62c-4212-b253-5f6b09d9f171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783144822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3783144822
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1792528730
Short name T36
Test name
Test status
Simulation time 495976206 ps
CPU time 1.38 seconds
Started Apr 23 12:20:52 PM PDT 24
Finished Apr 23 12:20:54 PM PDT 24
Peak memory 196188 kb
Host smart-b1132e82-1b62-4f46-8db0-bf987c0ed3d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792528730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1792528730
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1277500914
Short name T736
Test name
Test status
Simulation time 19745668 ps
CPU time 0.62 seconds
Started Apr 23 12:29:57 PM PDT 24
Finished Apr 23 12:29:58 PM PDT 24
Peak memory 194400 kb
Host smart-a0a71614-59a6-42e7-b06f-78e97e077943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277500914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1277500914
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3373378389
Short name T764
Test name
Test status
Simulation time 16636214 ps
CPU time 0.59 seconds
Started Apr 23 12:30:04 PM PDT 24
Finished Apr 23 12:30:05 PM PDT 24
Peak memory 193712 kb
Host smart-d8ee85f8-17cc-479e-9b9d-c7e4b673e930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373378389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3373378389
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2706182611
Short name T810
Test name
Test status
Simulation time 17900186 ps
CPU time 0.67 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 194348 kb
Host smart-62e14566-27f7-4a60-a606-b77a038294b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706182611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2706182611
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2602631093
Short name T724
Test name
Test status
Simulation time 52096857 ps
CPU time 0.6 seconds
Started Apr 23 12:29:54 PM PDT 24
Finished Apr 23 12:29:55 PM PDT 24
Peak memory 194412 kb
Host smart-4bffac18-47e0-4652-9688-4da4836db7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602631093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2602631093
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1901025684
Short name T732
Test name
Test status
Simulation time 106396447 ps
CPU time 0.56 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 193696 kb
Host smart-a87c7829-c26a-4253-bdaa-57c176c222e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901025684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1901025684
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3265790390
Short name T737
Test name
Test status
Simulation time 14671080 ps
CPU time 0.56 seconds
Started Apr 23 12:29:56 PM PDT 24
Finished Apr 23 12:29:58 PM PDT 24
Peak memory 193672 kb
Host smart-cdff353c-2bed-4f59-8861-84186235911e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265790390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3265790390
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2815582457
Short name T726
Test name
Test status
Simulation time 15293639 ps
CPU time 0.58 seconds
Started Apr 23 12:30:05 PM PDT 24
Finished Apr 23 12:30:07 PM PDT 24
Peak memory 194468 kb
Host smart-38153ed9-634b-43ee-a8ef-a9560252a011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815582457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2815582457
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1003594068
Short name T751
Test name
Test status
Simulation time 62428678 ps
CPU time 0.61 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 193712 kb
Host smart-84268857-a1a2-4cf9-8ed0-bdec590b8cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003594068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1003594068
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2761561337
Short name T792
Test name
Test status
Simulation time 15128346 ps
CPU time 0.56 seconds
Started Apr 23 12:29:54 PM PDT 24
Finished Apr 23 12:29:55 PM PDT 24
Peak memory 194340 kb
Host smart-90b23792-d001-491a-b29c-39567e6ad9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761561337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2761561337
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1369413629
Short name T749
Test name
Test status
Simulation time 18256541 ps
CPU time 0.65 seconds
Started Apr 23 12:29:55 PM PDT 24
Finished Apr 23 12:29:57 PM PDT 24
Peak memory 194412 kb
Host smart-c188d6fc-97e2-4bab-a0dc-ec9d1e0fedbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369413629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1369413629
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1316792409
Short name T834
Test name
Test status
Simulation time 13788315 ps
CPU time 0.67 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 193496 kb
Host smart-0a42a85d-b70d-4816-9ad4-98bfd36a8f88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316792409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1316792409
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.45941233
Short name T837
Test name
Test status
Simulation time 261768233 ps
CPU time 3.23 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 195800 kb
Host smart-9614fbb1-282a-4f76-9887-d80f282c010f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45941233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.45941233
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.596882559
Short name T809
Test name
Test status
Simulation time 84689389 ps
CPU time 0.64 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:33 PM PDT 24
Peak memory 194792 kb
Host smart-1b595523-cde1-4f9d-b786-8fb5f861b902
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596882559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.596882559
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2550122178
Short name T754
Test name
Test status
Simulation time 27030273 ps
CPU time 0.82 seconds
Started Apr 23 12:21:20 PM PDT 24
Finished Apr 23 12:21:21 PM PDT 24
Peak memory 197916 kb
Host smart-35953fe9-6a37-4aa3-b14c-847e93c6dfb4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550122178 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2550122178
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.966124747
Short name T752
Test name
Test status
Simulation time 42178442 ps
CPU time 0.67 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:56 PM PDT 24
Peak memory 194076 kb
Host smart-cedcc5d4-9046-44f9-bd52-d3db4d052d8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966124747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.966124747
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.265595261
Short name T791
Test name
Test status
Simulation time 18191775 ps
CPU time 0.59 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 194396 kb
Host smart-d7ad10bc-4f1e-41ce-a23d-7661df88c6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265595261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.265595261
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3956581242
Short name T115
Test name
Test status
Simulation time 136707071 ps
CPU time 0.93 seconds
Started Apr 23 12:22:58 PM PDT 24
Finished Apr 23 12:23:01 PM PDT 24
Peak memory 194532 kb
Host smart-acdf5447-dfd2-41fa-84c1-8193d70ffc60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956581242 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3956581242
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3721829800
Short name T812
Test name
Test status
Simulation time 82305584 ps
CPU time 1.72 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 197792 kb
Host smart-2c37588e-98ef-41aa-a0c9-911e948d06c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721829800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3721829800
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2294351012
Short name T777
Test name
Test status
Simulation time 273349152 ps
CPU time 0.84 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:15 PM PDT 24
Peak memory 197060 kb
Host smart-93aff481-0618-4d69-a52a-2d681d27be45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294351012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2294351012
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3543622142
Short name T756
Test name
Test status
Simulation time 45198518 ps
CPU time 0.58 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 193780 kb
Host smart-30c0e1fd-fc99-449f-a2d3-a122e45d36a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543622142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3543622142
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1619232491
Short name T742
Test name
Test status
Simulation time 39417781 ps
CPU time 0.6 seconds
Started Apr 23 12:29:55 PM PDT 24
Finished Apr 23 12:29:56 PM PDT 24
Peak memory 194340 kb
Host smart-4c51ade2-5694-4e5d-a5e4-50bf12345ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619232491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1619232491
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.310016311
Short name T734
Test name
Test status
Simulation time 67560054 ps
CPU time 0.57 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 193708 kb
Host smart-c8dc7057-e60a-4740-b1bb-762d8f1cd084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310016311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.310016311
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1532799891
Short name T793
Test name
Test status
Simulation time 19330970 ps
CPU time 0.64 seconds
Started Apr 23 12:29:56 PM PDT 24
Finished Apr 23 12:29:58 PM PDT 24
Peak memory 194444 kb
Host smart-20c9aaa1-3f74-46ac-9434-e10292175031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532799891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1532799891
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1974751255
Short name T720
Test name
Test status
Simulation time 11773936 ps
CPU time 0.54 seconds
Started Apr 23 12:29:55 PM PDT 24
Finished Apr 23 12:29:56 PM PDT 24
Peak memory 193664 kb
Host smart-40f19d25-09a7-4d48-9299-fcad301b99b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974751255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1974751255
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1161398905
Short name T760
Test name
Test status
Simulation time 49338233 ps
CPU time 0.6 seconds
Started Apr 23 12:29:54 PM PDT 24
Finished Apr 23 12:29:56 PM PDT 24
Peak memory 193768 kb
Host smart-4295db46-6ed4-41d9-bc6f-fa2a187c1f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161398905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1161398905
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3555580778
Short name T715
Test name
Test status
Simulation time 43893220 ps
CPU time 0.61 seconds
Started Apr 23 12:29:57 PM PDT 24
Finished Apr 23 12:29:58 PM PDT 24
Peak memory 193764 kb
Host smart-b0ec4365-9e43-4874-a709-c3d788dbf0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555580778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3555580778
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.280831687
Short name T801
Test name
Test status
Simulation time 49344460 ps
CPU time 0.64 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 193640 kb
Host smart-a76c7978-6fb5-44fd-94d2-0ac9d1ff67b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280831687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.280831687
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3499070163
Short name T828
Test name
Test status
Simulation time 52174531 ps
CPU time 0.64 seconds
Started Apr 23 12:29:55 PM PDT 24
Finished Apr 23 12:29:56 PM PDT 24
Peak memory 194500 kb
Host smart-652ee597-5d62-428d-bccd-90a27c8c3233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499070163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3499070163
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2894911010
Short name T769
Test name
Test status
Simulation time 34424179 ps
CPU time 0.59 seconds
Started Apr 23 12:29:56 PM PDT 24
Finished Apr 23 12:29:57 PM PDT 24
Peak memory 194456 kb
Host smart-3cfdc3c4-60ef-456a-9b6b-c0754f4b4902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894911010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2894911010
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1843278452
Short name T716
Test name
Test status
Simulation time 38428891 ps
CPU time 0.74 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 195944 kb
Host smart-4c92467f-bd37-41ec-a7e4-cb6e9f5bc955
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843278452 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1843278452
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.415328692
Short name T88
Test name
Test status
Simulation time 12821240 ps
CPU time 0.62 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 194716 kb
Host smart-21b3d98c-22d2-4f1e-9ba7-eb49dada2319
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415328692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.415328692
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1114417172
Short name T759
Test name
Test status
Simulation time 45706578 ps
CPU time 0.58 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 193428 kb
Host smart-89ea4a5b-e53d-43f7-b539-6c5c95c3d586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114417172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1114417172
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1439199790
Short name T112
Test name
Test status
Simulation time 110538601 ps
CPU time 0.75 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 194936 kb
Host smart-8281c0da-b509-4321-99e8-674ac4f7bea9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439199790 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1439199790
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2755577425
Short name T803
Test name
Test status
Simulation time 44320582 ps
CPU time 2.25 seconds
Started Apr 23 12:18:02 PM PDT 24
Finished Apr 23 12:18:05 PM PDT 24
Peak memory 198124 kb
Host smart-f6f604cc-da3d-48ad-98ea-9c3676c50ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755577425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2755577425
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1204776605
Short name T814
Test name
Test status
Simulation time 308524640 ps
CPU time 1.17 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 196840 kb
Host smart-ab538657-315c-4654-903b-e706a56f004b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204776605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1204776605
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.82798375
Short name T790
Test name
Test status
Simulation time 102069269 ps
CPU time 0.83 seconds
Started Apr 23 12:20:11 PM PDT 24
Finished Apr 23 12:20:13 PM PDT 24
Peak memory 198000 kb
Host smart-93151783-89dd-47f5-a178-19d9adcc5816
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82798375 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.82798375
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1217297567
Short name T97
Test name
Test status
Simulation time 14584817 ps
CPU time 0.61 seconds
Started Apr 23 12:23:24 PM PDT 24
Finished Apr 23 12:23:26 PM PDT 24
Peak memory 194436 kb
Host smart-06431f5d-3fca-4dde-ad5c-c231f84e4541
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217297567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1217297567
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2686088109
Short name T771
Test name
Test status
Simulation time 105523585 ps
CPU time 0.67 seconds
Started Apr 23 12:21:52 PM PDT 24
Finished Apr 23 12:21:53 PM PDT 24
Peak memory 194380 kb
Host smart-2ab99284-f685-423f-9a89-74b8dd8cabcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686088109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2686088109
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.692031401
Short name T111
Test name
Test status
Simulation time 130409977 ps
CPU time 0.76 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:23:30 PM PDT 24
Peak memory 195976 kb
Host smart-0ee8cce1-8d7b-441a-b128-821ded21bf0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692031401 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.692031401
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.430622948
Short name T733
Test name
Test status
Simulation time 22624356 ps
CPU time 1.04 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 197592 kb
Host smart-1679e570-e423-43aa-a547-bc2a569cb7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430622948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.430622948
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3754758332
Short name T40
Test name
Test status
Simulation time 121113340 ps
CPU time 1.35 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 197836 kb
Host smart-27f52b40-5a7d-4226-94a0-05f8620c7421
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754758332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3754758332
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3751500024
Short name T836
Test name
Test status
Simulation time 51114336 ps
CPU time 0.64 seconds
Started Apr 23 12:21:54 PM PDT 24
Finished Apr 23 12:21:55 PM PDT 24
Peak memory 196756 kb
Host smart-f4a2d8f5-46f1-4367-9c8d-344f7b1f4017
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751500024 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3751500024
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.950395076
Short name T87
Test name
Test status
Simulation time 16709639 ps
CPU time 0.59 seconds
Started Apr 23 12:23:24 PM PDT 24
Finished Apr 23 12:23:25 PM PDT 24
Peak memory 194112 kb
Host smart-db57e4c9-dd21-4780-ae57-aa19fa813c4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950395076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.950395076
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3096980772
Short name T763
Test name
Test status
Simulation time 27810689 ps
CPU time 0.58 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 192360 kb
Host smart-1b4fcf33-083b-4b2e-8f91-6270dc9f8bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096980772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3096980772
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3617580059
Short name T108
Test name
Test status
Simulation time 70569340 ps
CPU time 0.82 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 195912 kb
Host smart-d51aa44a-80dd-4d3f-a02c-f206b94b5317
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617580059 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3617580059
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4040187727
Short name T761
Test name
Test status
Simulation time 99113096 ps
CPU time 2.15 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 197788 kb
Host smart-b04ceb3c-3050-4bdf-9d96-7b5e136f2dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040187727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4040187727
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.488574258
Short name T740
Test name
Test status
Simulation time 73262955 ps
CPU time 0.85 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 196240 kb
Host smart-15adc871-6c9e-49a9-b3c5-7e84a875429d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488574258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.488574258
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1521797018
Short name T821
Test name
Test status
Simulation time 68701710 ps
CPU time 0.94 seconds
Started Apr 23 12:29:35 PM PDT 24
Finished Apr 23 12:29:37 PM PDT 24
Peak memory 198004 kb
Host smart-e7e4cb2b-2d70-4e4c-b08b-ed15026eaef7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521797018 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1521797018
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.616503316
Short name T91
Test name
Test status
Simulation time 37737919 ps
CPU time 0.66 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 194352 kb
Host smart-c48cc796-a107-4d64-aa96-7321ba960dbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616503316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.616503316
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.977313773
Short name T717
Test name
Test status
Simulation time 14530554 ps
CPU time 0.55 seconds
Started Apr 23 12:29:37 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 194324 kb
Host smart-36af1109-a792-4aeb-b86d-bc9cc0f682a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977313773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.977313773
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.69747521
Short name T770
Test name
Test status
Simulation time 70583544 ps
CPU time 0.75 seconds
Started Apr 23 12:29:40 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 196932 kb
Host smart-5bbdff07-3ed4-444a-b2a8-566d6a6ceb0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69747521 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.gpio_same_csr_outstanding.69747521
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2401483881
Short name T826
Test name
Test status
Simulation time 405431890 ps
CPU time 1.96 seconds
Started Apr 23 12:29:35 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 198060 kb
Host smart-901d0aa5-1989-49d7-8da0-8db5158a42de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401483881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2401483881
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3737063645
Short name T813
Test name
Test status
Simulation time 223079578 ps
CPU time 1.37 seconds
Started Apr 23 12:29:38 PM PDT 24
Finished Apr 23 12:29:41 PM PDT 24
Peak memory 198020 kb
Host smart-a6632c90-aaed-43a1-930b-01a86337cbab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737063645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3737063645
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3813467667
Short name T728
Test name
Test status
Simulation time 132994823 ps
CPU time 1.65 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 198152 kb
Host smart-4a03b9dc-6d85-48df-9a5f-9fdf31bdd6eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813467667 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3813467667
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4017502132
Short name T782
Test name
Test status
Simulation time 21394629 ps
CPU time 0.59 seconds
Started Apr 23 12:29:35 PM PDT 24
Finished Apr 23 12:29:37 PM PDT 24
Peak memory 194900 kb
Host smart-f11e5b94-6f5e-4825-97d3-0cba9228cc58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017502132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4017502132
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3902346538
Short name T773
Test name
Test status
Simulation time 110890343 ps
CPU time 0.6 seconds
Started Apr 23 12:29:40 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 194608 kb
Host smart-370dadde-2326-4f98-9a87-f304e6e6736d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902346538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3902346538
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.352674923
Short name T762
Test name
Test status
Simulation time 32297682 ps
CPU time 0.63 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 194572 kb
Host smart-949809e8-39cc-43e0-88cc-a8df6949b7f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352674923 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.352674923
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3304978516
Short name T787
Test name
Test status
Simulation time 88561325 ps
CPU time 1.33 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 198132 kb
Host smart-28e2f3a4-99ac-4797-8e9b-f0a2c6e0cbca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304978516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3304978516
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.153151908
Short name T827
Test name
Test status
Simulation time 93528342 ps
CPU time 1.11 seconds
Started Apr 23 12:29:36 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 198204 kb
Host smart-3bb6b93e-6d4b-4556-bb07-d047aae66d15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153151908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.153151908
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3458592258
Short name T494
Test name
Test status
Simulation time 18339813 ps
CPU time 0.63 seconds
Started Apr 23 12:22:34 PM PDT 24
Finished Apr 23 12:22:36 PM PDT 24
Peak memory 194432 kb
Host smart-417367fc-85fe-431b-8a9a-841245eb6e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458592258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3458592258
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2971059329
Short name T100
Test name
Test status
Simulation time 422115653 ps
CPU time 15.57 seconds
Started Apr 23 12:21:14 PM PDT 24
Finished Apr 23 12:21:30 PM PDT 24
Peak memory 195536 kb
Host smart-dc809e69-af9d-456f-b15a-12fe3321c085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971059329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2971059329
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3397373764
Short name T567
Test name
Test status
Simulation time 343852293 ps
CPU time 1.09 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 196608 kb
Host smart-c28d849b-04a3-4d63-9dfa-f9a8eb466c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397373764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3397373764
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3626602057
Short name T558
Test name
Test status
Simulation time 155238968 ps
CPU time 1.25 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 194148 kb
Host smart-9d47fd9a-c6e5-4a4e-ba7b-0588ddd026f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626602057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3626602057
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2641850476
Short name T639
Test name
Test status
Simulation time 94343208 ps
CPU time 3.4 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:40 PM PDT 24
Peak memory 197592 kb
Host smart-39857027-22b6-4deb-bb50-4a0d345e7716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641850476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2641850476
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.861006720
Short name T680
Test name
Test status
Simulation time 291438767 ps
CPU time 2.83 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:19:41 PM PDT 24
Peak memory 198056 kb
Host smart-23ecbb00-45f8-4f11-a6e6-a3024020584d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861006720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.861006720
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4054865191
Short name T67
Test name
Test status
Simulation time 82518300 ps
CPU time 0.74 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 193108 kb
Host smart-76f15be0-7169-46e5-b941-320df26e3264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054865191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4054865191
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.92906949
Short name T439
Test name
Test status
Simulation time 16412592 ps
CPU time 0.73 seconds
Started Apr 23 12:19:02 PM PDT 24
Finished Apr 23 12:19:03 PM PDT 24
Peak memory 194432 kb
Host smart-c9e9c97f-40d1-4da9-9081-cea782465723
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92906949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_p
ulldown.92906949
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3602287145
Short name T217
Test name
Test status
Simulation time 34142077 ps
CPU time 1.54 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 197828 kb
Host smart-e0df6eda-e164-4007-ab08-eb6582e9dc35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602287145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3602287145
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3468398217
Short name T528
Test name
Test status
Simulation time 30269592 ps
CPU time 0.74 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 194348 kb
Host smart-5b12a860-9f6a-4564-96dc-27bad2448e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468398217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3468398217
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.76409115
Short name T245
Test name
Test status
Simulation time 165116626 ps
CPU time 0.89 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 196092 kb
Host smart-96f4f295-bf67-4bc3-a524-08d82d9dc8eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76409115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.76409115
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2703174998
Short name T427
Test name
Test status
Simulation time 35233758794 ps
CPU time 109.13 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 197444 kb
Host smart-e27aa2dc-6713-431c-b0cb-c14aee1149c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703174998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2703174998
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1674135645
Short name T58
Test name
Test status
Simulation time 53023847930 ps
CPU time 1697.59 seconds
Started Apr 23 12:21:16 PM PDT 24
Finished Apr 23 12:49:34 PM PDT 24
Peak memory 198192 kb
Host smart-0f8ec6c6-b12d-4b3e-a65c-ad50b8030b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1674135645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1674135645
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4231037293
Short name T630
Test name
Test status
Simulation time 48913526 ps
CPU time 0.56 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:30:13 PM PDT 24
Peak memory 194004 kb
Host smart-0148afd6-1e80-47b8-99b7-021037e19348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231037293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4231037293
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.470561728
Short name T556
Test name
Test status
Simulation time 25969047 ps
CPU time 0.57 seconds
Started Apr 23 12:22:45 PM PDT 24
Finished Apr 23 12:22:47 PM PDT 24
Peak memory 193928 kb
Host smart-273a4262-0347-4aff-aed4-c8e2c11c5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470561728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.470561728
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3529054197
Short name T192
Test name
Test status
Simulation time 765908349 ps
CPU time 10.2 seconds
Started Apr 23 12:30:07 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 196792 kb
Host smart-7ddca0ce-d0d5-41ff-9124-9806ed665b7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529054197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3529054197
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.467864881
Short name T120
Test name
Test status
Simulation time 190307652 ps
CPU time 0.82 seconds
Started Apr 23 12:30:08 PM PDT 24
Finished Apr 23 12:30:10 PM PDT 24
Peak memory 195944 kb
Host smart-6ae1791b-d926-4790-90ec-0ef6f7a6b3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467864881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.467864881
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.767390231
Short name T130
Test name
Test status
Simulation time 160139868 ps
CPU time 1.25 seconds
Started Apr 23 12:22:34 PM PDT 24
Finished Apr 23 12:22:36 PM PDT 24
Peak memory 196548 kb
Host smart-2a137a72-cc4d-4998-adc2-82f7644c01a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767390231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.767390231
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1680381366
Short name T573
Test name
Test status
Simulation time 328150569 ps
CPU time 1.98 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:30:14 PM PDT 24
Peak memory 197996 kb
Host smart-74e55288-583b-4288-bd97-e21e93e7c2ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680381366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1680381366
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3437405736
Short name T315
Test name
Test status
Simulation time 1373531295 ps
CPU time 2.84 seconds
Started Apr 23 12:30:08 PM PDT 24
Finished Apr 23 12:30:12 PM PDT 24
Peak memory 195876 kb
Host smart-e229e598-3b35-4b79-bed6-a04ebfe1ce79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437405736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3437405736
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.610325230
Short name T225
Test name
Test status
Simulation time 190624377 ps
CPU time 1.13 seconds
Started Apr 23 12:22:33 PM PDT 24
Finished Apr 23 12:22:36 PM PDT 24
Peak memory 195152 kb
Host smart-846426cc-f493-41d8-980f-e589661df63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610325230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.610325230
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2157160756
Short name T526
Test name
Test status
Simulation time 67572119 ps
CPU time 1.01 seconds
Started Apr 23 12:23:39 PM PDT 24
Finished Apr 23 12:23:41 PM PDT 24
Peak memory 194824 kb
Host smart-941fab7c-4a5b-4aef-8cd1-be71f0e0a642
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157160756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2157160756
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2240229672
Short name T184
Test name
Test status
Simulation time 143866950 ps
CPU time 1.68 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 197488 kb
Host smart-607edbd5-8c50-4ac2-8deb-04cb63e41deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240229672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2240229672
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3696261729
Short name T46
Test name
Test status
Simulation time 80651095 ps
CPU time 1 seconds
Started Apr 23 12:30:09 PM PDT 24
Finished Apr 23 12:30:10 PM PDT 24
Peak memory 214772 kb
Host smart-3de59a85-ccd1-4ae2-8293-14e71eb6959b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696261729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3696261729
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2286990275
Short name T594
Test name
Test status
Simulation time 86495197 ps
CPU time 1.07 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 195372 kb
Host smart-a1b087c7-da3c-4288-a1d9-21f7c8b103d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286990275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2286990275
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1601411021
Short name T19
Test name
Test status
Simulation time 270255925 ps
CPU time 1.37 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 194852 kb
Host smart-88f3cb0e-55f8-4e73-b276-9ff12c17e06a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601411021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1601411021
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2137374245
Short name T588
Test name
Test status
Simulation time 63548625140 ps
CPU time 186.92 seconds
Started Apr 23 12:30:09 PM PDT 24
Finished Apr 23 12:33:17 PM PDT 24
Peak memory 198108 kb
Host smart-7f8f23dc-becd-4f92-bb14-356105c6fc7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137374245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2137374245
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2852492346
Short name T645
Test name
Test status
Simulation time 102756638 ps
CPU time 0.54 seconds
Started Apr 23 12:30:30 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 193840 kb
Host smart-54bb863a-e886-4f14-be81-e6b852b62b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852492346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2852492346
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2594804369
Short name T460
Test name
Test status
Simulation time 31492862 ps
CPU time 0.61 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 193996 kb
Host smart-903c8434-b651-4a29-ac3c-8e75134de5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594804369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2594804369
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3975571724
Short name T98
Test name
Test status
Simulation time 1112027500 ps
CPU time 7.44 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 197972 kb
Host smart-3a8bdee7-c9db-45a7-8558-ee56b197bf92
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975571724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3975571724
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.609918548
Short name T20
Test name
Test status
Simulation time 225415889 ps
CPU time 0.82 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:28 PM PDT 24
Peak memory 195856 kb
Host smart-c78cb8d5-6ea4-43a0-92ac-d0260c1c128b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609918548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.609918548
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2959084873
Short name T11
Test name
Test status
Simulation time 86814619 ps
CPU time 1.23 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 196756 kb
Host smart-5ba83873-4cc7-4c85-8284-527a64be6805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959084873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2959084873
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2479810942
Short name T502
Test name
Test status
Simulation time 61259945 ps
CPU time 2.4 seconds
Started Apr 23 12:30:29 PM PDT 24
Finished Apr 23 12:30:33 PM PDT 24
Peak memory 197216 kb
Host smart-782f9e92-ec6b-47d0-aad7-c75074853075
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479810942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2479810942
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4260708294
Short name T418
Test name
Test status
Simulation time 259769115 ps
CPU time 2.42 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:32 PM PDT 24
Peak memory 195760 kb
Host smart-7c87dd37-c876-4739-92ee-1a5d51aa7972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260708294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4260708294
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2890895378
Short name T99
Test name
Test status
Simulation time 111678755 ps
CPU time 1.04 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 195956 kb
Host smart-cfe2b139-85dc-4f67-a181-1b35ed98c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890895378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2890895378
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3521578418
Short name T160
Test name
Test status
Simulation time 32922293 ps
CPU time 0.82 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 195472 kb
Host smart-11dfc591-9651-4dad-9c87-f3484f1f1a0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521578418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3521578418
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.330387926
Short name T10
Test name
Test status
Simulation time 595339533 ps
CPU time 3.64 seconds
Started Apr 23 12:30:30 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 198052 kb
Host smart-9ac2aebf-9cf9-447e-b547-37f095c68044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330387926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.330387926
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3637463506
Short name T211
Test name
Test status
Simulation time 660358356 ps
CPU time 1.47 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 196772 kb
Host smart-db6d539a-3278-42e7-9835-8d17a70fdba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637463506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3637463506
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1644952357
Short name T542
Test name
Test status
Simulation time 257617237 ps
CPU time 1.31 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 196644 kb
Host smart-0f07f73c-fbc2-43c3-ad48-19d1dfe7f26b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644952357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1644952357
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.4291826970
Short name T433
Test name
Test status
Simulation time 18250976577 ps
CPU time 117.23 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:32:29 PM PDT 24
Peak memory 198020 kb
Host smart-4b990014-aff9-42ee-a6ee-1b071f2a66da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291826970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.4291826970
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3752173459
Short name T59
Test name
Test status
Simulation time 132225270743 ps
CPU time 474.55 seconds
Started Apr 23 12:30:29 PM PDT 24
Finished Apr 23 12:38:25 PM PDT 24
Peak memory 198196 kb
Host smart-3a6012a7-32bb-4974-8723-e4c95c331b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3752173459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3752173459
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3582429770
Short name T314
Test name
Test status
Simulation time 36205664 ps
CPU time 0.56 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 192760 kb
Host smart-3d1907f0-cda2-408e-927c-1464e963cf63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582429770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3582429770
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1728699044
Short name T291
Test name
Test status
Simulation time 40876710 ps
CPU time 0.77 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 196072 kb
Host smart-d31c2014-3131-4008-bf10-e2180bc7db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728699044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1728699044
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1787209701
Short name T605
Test name
Test status
Simulation time 1386540453 ps
CPU time 14.02 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 196928 kb
Host smart-a29d36c4-dd9c-4ac7-86ff-ef1e9b393da9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787209701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1787209701
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1883862998
Short name T504
Test name
Test status
Simulation time 123553521 ps
CPU time 0.74 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:30:33 PM PDT 24
Peak memory 194728 kb
Host smart-cdebbf75-56aa-4338-b312-2557746d54f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883862998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1883862998
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3977673637
Short name T601
Test name
Test status
Simulation time 184138995 ps
CPU time 1.35 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 196632 kb
Host smart-6cc565dc-6756-4a4f-a4f0-8045603005b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977673637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3977673637
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3632451259
Short name T103
Test name
Test status
Simulation time 119475038 ps
CPU time 1.4 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 197912 kb
Host smart-3284e0d1-a887-4dda-ac4e-b16b4b48753a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632451259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3632451259
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2744651350
Short name T279
Test name
Test status
Simulation time 86947490 ps
CPU time 2.73 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 197000 kb
Host smart-75dcf1de-7713-4e64-a133-4604c7ceb18e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744651350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2744651350
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2917633608
Short name T168
Test name
Test status
Simulation time 137148617 ps
CPU time 1.26 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 195844 kb
Host smart-ce01c51e-a831-4a6e-92a7-3f3f19085ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917633608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2917633608
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3692152098
Short name T292
Test name
Test status
Simulation time 75292687 ps
CPU time 1.29 seconds
Started Apr 23 12:30:29 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 196996 kb
Host smart-b5744b7a-de29-4c32-aacd-3715e2d812ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692152098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3692152098
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.779059305
Short name T541
Test name
Test status
Simulation time 1342582732 ps
CPU time 4.17 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:38 PM PDT 24
Peak memory 197944 kb
Host smart-75486d98-33fa-4a73-9328-3b953986169b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779059305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.779059305
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2574871962
Short name T540
Test name
Test status
Simulation time 112469838 ps
CPU time 1.01 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:30:33 PM PDT 24
Peak memory 195560 kb
Host smart-e1e3ea92-5d5d-4d49-883f-34b935a17d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574871962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2574871962
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4220352324
Short name T249
Test name
Test status
Simulation time 367295737 ps
CPU time 0.86 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:28 PM PDT 24
Peak memory 195780 kb
Host smart-ced8e7d2-18e0-4d98-9f4c-bf2478a37ccd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220352324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4220352324
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1453232102
Short name T8
Test name
Test status
Simulation time 57128971041 ps
CPU time 162.97 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:33:15 PM PDT 24
Peak memory 198064 kb
Host smart-cc5290de-4272-4d1f-a564-ff925e2baa8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453232102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1453232102
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3296508980
Short name T483
Test name
Test status
Simulation time 21862754 ps
CPU time 0.56 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:38 PM PDT 24
Peak memory 193908 kb
Host smart-19841416-17fc-4f75-a1f2-23ff4cc95d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296508980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3296508980
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2432736882
Short name T178
Test name
Test status
Simulation time 165902906 ps
CPU time 0.71 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 195956 kb
Host smart-cbb04db0-0803-45fc-b134-d6dc150a1919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432736882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2432736882
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.348220188
Short name T385
Test name
Test status
Simulation time 1398860685 ps
CPU time 25.44 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 195532 kb
Host smart-e1065c17-e231-4f30-b61d-83b6882d4b5e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348220188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.348220188
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3690256084
Short name T216
Test name
Test status
Simulation time 130575086 ps
CPU time 0.81 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:39 PM PDT 24
Peak memory 196464 kb
Host smart-eabe1979-1099-4f13-aad6-a215fa0224b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690256084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3690256084
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3152824966
Short name T561
Test name
Test status
Simulation time 76100880 ps
CPU time 0.84 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 195416 kb
Host smart-45fcb2cb-e0ef-427e-885b-3a272b0b1be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152824966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3152824966
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1287204472
Short name T65
Test name
Test status
Simulation time 83800277 ps
CPU time 3.53 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 198048 kb
Host smart-e3cd90ca-6366-4e32-a220-8fe80ebe8240
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287204472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1287204472
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1878203207
Short name T650
Test name
Test status
Simulation time 303363500 ps
CPU time 1.65 seconds
Started Apr 23 12:30:30 PM PDT 24
Finished Apr 23 12:30:33 PM PDT 24
Peak memory 196076 kb
Host smart-2bc60fbc-c29f-49a4-8158-74ab5e9b69a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878203207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1878203207
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1156409945
Short name T459
Test name
Test status
Simulation time 108102184 ps
CPU time 1.27 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 197956 kb
Host smart-c1b4f8f5-160a-40bd-9033-414580bfaf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156409945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1156409945
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.123649532
Short name T404
Test name
Test status
Simulation time 45049100 ps
CPU time 1.1 seconds
Started Apr 23 12:30:33 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 196088 kb
Host smart-71b5fe5c-6dff-4a68-94a8-affc4b04166d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123649532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.123649532
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3504495720
Short name T587
Test name
Test status
Simulation time 207640496 ps
CPU time 3.01 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 198016 kb
Host smart-267411ac-98b9-4546-b881-3682e256f01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504495720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3504495720
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.288814347
Short name T707
Test name
Test status
Simulation time 46493563 ps
CPU time 0.99 seconds
Started Apr 23 12:30:32 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 196184 kb
Host smart-59297400-54e4-4a2c-b6f5-cc0a4561bc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288814347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.288814347
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1722247248
Short name T396
Test name
Test status
Simulation time 147514749 ps
CPU time 1.07 seconds
Started Apr 23 12:30:34 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 195740 kb
Host smart-310a5a4b-2e45-4751-a3b5-7c8987ddd5ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722247248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1722247248
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3324115607
Short name T311
Test name
Test status
Simulation time 5919114320 ps
CPU time 145.8 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:33:08 PM PDT 24
Peak memory 198064 kb
Host smart-8808e918-ca1c-42e2-ae1a-e9994aa50bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324115607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3324115607
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.289093563
Short name T250
Test name
Test status
Simulation time 13052654 ps
CPU time 0.57 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:39 PM PDT 24
Peak memory 192748 kb
Host smart-9921b67c-b6ee-4f5a-9e49-5d6d9116c0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289093563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.289093563
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2481360096
Short name T697
Test name
Test status
Simulation time 63115692 ps
CPU time 0.89 seconds
Started Apr 23 12:30:34 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 196056 kb
Host smart-a0fb69fb-86c8-4b03-94e6-0bf464db57cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481360096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2481360096
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1297650310
Short name T101
Test name
Test status
Simulation time 1033861562 ps
CPU time 5.59 seconds
Started Apr 23 12:30:37 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 197092 kb
Host smart-9d28bee7-a4b9-4d6c-8c14-c0dc00792a40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297650310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1297650310
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1300534033
Short name T227
Test name
Test status
Simulation time 76668302 ps
CPU time 1.12 seconds
Started Apr 23 12:30:37 PM PDT 24
Finished Apr 23 12:30:39 PM PDT 24
Peak memory 196792 kb
Host smart-42d90c65-656d-4b63-9d0c-8e79e5a5f218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300534033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1300534033
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1475399747
Short name T489
Test name
Test status
Simulation time 38416147 ps
CPU time 0.82 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 195780 kb
Host smart-9e8b2ea9-0e79-4211-a302-aa9eaed17dce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475399747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1475399747
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1781453315
Short name T383
Test name
Test status
Simulation time 180179759 ps
CPU time 1.78 seconds
Started Apr 23 12:30:37 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 198032 kb
Host smart-62f38530-64fc-4cdb-b943-58bf436944ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781453315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1781453315
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3272108550
Short name T248
Test name
Test status
Simulation time 132827452 ps
CPU time 2.06 seconds
Started Apr 23 12:30:37 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 197008 kb
Host smart-bcbe8352-7aac-45b0-9f36-062e5094aaf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272108550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3272108550
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.717980773
Short name T356
Test name
Test status
Simulation time 48161698 ps
CPU time 1.16 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 195944 kb
Host smart-bffc6884-917d-4ad8-8730-c37591924335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717980773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.717980773
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3091978356
Short name T472
Test name
Test status
Simulation time 20246295 ps
CPU time 0.68 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:38 PM PDT 24
Peak memory 194960 kb
Host smart-391f7537-8cd5-4408-b7e8-64d7ed02c4fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091978356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3091978356
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1482278822
Short name T684
Test name
Test status
Simulation time 1465590995 ps
CPU time 6.3 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 198016 kb
Host smart-d3d4f195-6b62-49e4-8f57-ae67c1f046da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482278822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1482278822
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3694146341
Short name T617
Test name
Test status
Simulation time 570818728 ps
CPU time 1.03 seconds
Started Apr 23 12:30:35 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 196200 kb
Host smart-f54252dd-4ce6-49ec-b653-a02acd27d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694146341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3694146341
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1114242805
Short name T142
Test name
Test status
Simulation time 260863117 ps
CPU time 1.3 seconds
Started Apr 23 12:30:34 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 198008 kb
Host smart-b8c1c126-5fae-47e5-8d9d-82ada8049be8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114242805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1114242805
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1033253559
Short name T255
Test name
Test status
Simulation time 1434408118 ps
CPU time 34.94 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:31:18 PM PDT 24
Peak memory 197912 kb
Host smart-b8910471-d093-4d75-ae33-24223ee2fc52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033253559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1033253559
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3322538277
Short name T421
Test name
Test status
Simulation time 13764054 ps
CPU time 0.57 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 194088 kb
Host smart-0972bba7-fe7c-4874-ba82-f2151867c38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322538277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3322538277
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.551480527
Short name T449
Test name
Test status
Simulation time 88148927 ps
CPU time 0.72 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 195200 kb
Host smart-66451807-e40a-44b2-9b61-10eb7b663646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551480527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.551480527
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2466424935
Short name T80
Test name
Test status
Simulation time 262431077 ps
CPU time 4.51 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 195972 kb
Host smart-90250dc6-6bc4-40e9-8561-a3d0ccbe9a83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466424935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2466424935
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.903092963
Short name T420
Test name
Test status
Simulation time 136954805 ps
CPU time 0.75 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 194716 kb
Host smart-1b1ca933-88e3-4a18-8bd8-64dd5de3aedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903092963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.903092963
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.854688738
Short name T431
Test name
Test status
Simulation time 24459024 ps
CPU time 0.77 seconds
Started Apr 23 12:30:37 PM PDT 24
Finished Apr 23 12:30:39 PM PDT 24
Peak memory 195608 kb
Host smart-b1d200de-aed0-40ec-bd92-c7cade7ec05a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854688738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.854688738
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.480875530
Short name T408
Test name
Test status
Simulation time 85317596 ps
CPU time 3.13 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 197940 kb
Host smart-1b288217-95d0-4a13-936a-266569d7095d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480875530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.480875530
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.796681670
Short name T219
Test name
Test status
Simulation time 390172273 ps
CPU time 2.99 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 197980 kb
Host smart-a23cf08c-7a54-4313-92c8-9bc974adf67e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796681670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
796681670
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1410972871
Short name T182
Test name
Test status
Simulation time 122208048 ps
CPU time 0.85 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 196452 kb
Host smart-f519b9e5-35ae-4b42-801b-d70bb64a0d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410972871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1410972871
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2871554515
Short name T205
Test name
Test status
Simulation time 47337109 ps
CPU time 0.72 seconds
Started Apr 23 12:30:39 PM PDT 24
Finished Apr 23 12:30:41 PM PDT 24
Peak memory 195396 kb
Host smart-15938006-8ef1-4759-b92a-bb8574c10e94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871554515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2871554515
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3685683441
Short name T597
Test name
Test status
Simulation time 410278654 ps
CPU time 2.04 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 197968 kb
Host smart-ca63d063-420d-4e13-be09-428c725e5009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685683441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3685683441
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.374921098
Short name T602
Test name
Test status
Simulation time 666789728 ps
CPU time 1.14 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 196720 kb
Host smart-948c7425-fffa-44bb-bf61-ed44cbe33113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374921098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.374921098
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3315494445
Short name T410
Test name
Test status
Simulation time 273047890 ps
CPU time 1.17 seconds
Started Apr 23 12:30:36 PM PDT 24
Finished Apr 23 12:30:38 PM PDT 24
Peak memory 196736 kb
Host smart-280d404f-1c0c-4816-8891-b5c38e7a3eb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315494445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3315494445
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.791195818
Short name T593
Test name
Test status
Simulation time 14342854804 ps
CPU time 187.76 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:33:50 PM PDT 24
Peak memory 198092 kb
Host smart-d6d10780-1772-4df2-b563-62dd87b2fae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791195818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.791195818
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3947270106
Short name T61
Test name
Test status
Simulation time 89230713059 ps
CPU time 2290.64 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 01:08:50 PM PDT 24
Peak memory 198172 kb
Host smart-08b7abfd-8ccf-4f75-bc0f-c46aed80d3ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3947270106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3947270106
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.387454978
Short name T212
Test name
Test status
Simulation time 22449940 ps
CPU time 0.59 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 193900 kb
Host smart-30b87112-c8f8-4874-aece-fa9b9b649e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387454978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.387454978
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3015672996
Short name T288
Test name
Test status
Simulation time 82486707 ps
CPU time 0.69 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 194064 kb
Host smart-120f9655-241c-4dfc-9c65-4aca835e42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015672996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3015672996
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.904434580
Short name T106
Test name
Test status
Simulation time 1661590593 ps
CPU time 24.76 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:31:09 PM PDT 24
Peak memory 196656 kb
Host smart-1b7d8a98-fe97-44bc-849a-105d664b1f69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904434580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.904434580
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.88139357
Short name T625
Test name
Test status
Simulation time 85509153 ps
CPU time 0.63 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:41 PM PDT 24
Peak memory 194364 kb
Host smart-c043fec9-d30f-4c51-9bf9-b867b77f082d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88139357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.88139357
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.300501603
Short name T437
Test name
Test status
Simulation time 303366623 ps
CPU time 1.06 seconds
Started Apr 23 12:30:43 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 195956 kb
Host smart-24434b14-bfc5-4661-bab0-1b0fe3780f8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300501603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.300501603
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1689488688
Short name T379
Test name
Test status
Simulation time 41024690 ps
CPU time 0.96 seconds
Started Apr 23 12:30:43 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 196216 kb
Host smart-8c4e925b-203b-4c99-bd63-39f0c7e61b4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689488688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1689488688
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1686616273
Short name T671
Test name
Test status
Simulation time 100548800 ps
CPU time 1.08 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 195736 kb
Host smart-d705d5f9-95d4-479d-adf2-ead800069d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686616273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1686616273
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2921508441
Short name T365
Test name
Test status
Simulation time 117952871 ps
CPU time 1.16 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 196100 kb
Host smart-b394ba02-1828-4a7e-ada9-ebcd5e2dda2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921508441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2921508441
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1232322798
Short name T488
Test name
Test status
Simulation time 101491331 ps
CPU time 0.95 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 196028 kb
Host smart-120cb2e3-747f-4ac6-89fa-0ef20b541805
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232322798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1232322798
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3463441051
Short name T629
Test name
Test status
Simulation time 71917614 ps
CPU time 3.2 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 198000 kb
Host smart-a74cd09f-a0a3-494b-a028-9b2c9d3322b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463441051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3463441051
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2266886177
Short name T688
Test name
Test status
Simulation time 74912964 ps
CPU time 1.23 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 195892 kb
Host smart-17434935-48b2-4c91-821b-6002a6636463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266886177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2266886177
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2361608400
Short name T463
Test name
Test status
Simulation time 160948960 ps
CPU time 1.04 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 195540 kb
Host smart-9f030d17-0ea4-4570-be10-e059da4836d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361608400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2361608400
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4197624874
Short name T213
Test name
Test status
Simulation time 20589603139 ps
CPU time 132.4 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:32:56 PM PDT 24
Peak memory 198148 kb
Host smart-5ba71cad-b684-48ca-a769-bdcdf80aa645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197624874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4197624874
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2997915368
Short name T26
Test name
Test status
Simulation time 57436873935 ps
CPU time 1169.45 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:50:13 PM PDT 24
Peak memory 198144 kb
Host smart-85971eff-52af-4922-860b-d965e85ef8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2997915368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2997915368
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1988415346
Short name T576
Test name
Test status
Simulation time 235301688 ps
CPU time 0.58 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 194068 kb
Host smart-11bdb961-5505-4586-9b69-5fe33aa7d2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988415346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1988415346
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3685990228
Short name T361
Test name
Test status
Simulation time 59896620 ps
CPU time 0.66 seconds
Started Apr 23 12:30:38 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 194136 kb
Host smart-72af1222-3c2c-4179-af48-2d935477eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685990228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3685990228
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3487579563
Short name T201
Test name
Test status
Simulation time 2416967295 ps
CPU time 3.71 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 195564 kb
Host smart-34c5cbba-d371-42dd-8779-7374c0d04874
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487579563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3487579563
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2202298343
Short name T17
Test name
Test status
Simulation time 62982571 ps
CPU time 0.68 seconds
Started Apr 23 12:30:43 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 194660 kb
Host smart-e105c26d-c98f-4b5c-a0ca-fddf741bac6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202298343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2202298343
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.322618570
Short name T438
Test name
Test status
Simulation time 267644964 ps
CPU time 1.28 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 196888 kb
Host smart-53e44b1a-b7b6-42c0-a971-70a79145ff95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322618570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.322618570
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3027904568
Short name T132
Test name
Test status
Simulation time 60565958 ps
CPU time 1.38 seconds
Started Apr 23 12:30:45 PM PDT 24
Finished Apr 23 12:30:47 PM PDT 24
Peak memory 197936 kb
Host smart-b8d5d77a-6457-410a-88ef-c5b1d69aa636
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027904568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3027904568
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2913735206
Short name T683
Test name
Test status
Simulation time 115442767 ps
CPU time 1.3 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 196908 kb
Host smart-007eab5e-02ac-4751-8b70-8259ddab7c3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913735206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2913735206
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2350319057
Short name T310
Test name
Test status
Simulation time 65137567 ps
CPU time 1.05 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 196648 kb
Host smart-2fbf2821-21d1-464b-8d89-e0f3e31fb240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350319057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2350319057
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.92943241
Short name T510
Test name
Test status
Simulation time 359720999 ps
CPU time 1.11 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 195872 kb
Host smart-3daa21a9-2b94-487b-832c-b780ef3cf7cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92943241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup_
pulldown.92943241
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4271774014
Short name T363
Test name
Test status
Simulation time 327475494 ps
CPU time 1.39 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 198012 kb
Host smart-459ab604-6a76-4e0e-a5b0-e0c8007f9756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271774014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4271774014
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.375909713
Short name T118
Test name
Test status
Simulation time 35052728 ps
CPU time 1.14 seconds
Started Apr 23 12:30:40 PM PDT 24
Finished Apr 23 12:30:43 PM PDT 24
Peak memory 195756 kb
Host smart-3dca1d44-3796-44bf-98a8-790c59e5a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375909713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.375909713
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1947802082
Short name T416
Test name
Test status
Simulation time 33550006 ps
CPU time 1.18 seconds
Started Apr 23 12:30:39 PM PDT 24
Finished Apr 23 12:30:40 PM PDT 24
Peak memory 196548 kb
Host smart-01a305ee-1836-46ca-9606-8512c351f647
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947802082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1947802082
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2474575448
Short name T203
Test name
Test status
Simulation time 5496909591 ps
CPU time 37.62 seconds
Started Apr 23 12:30:43 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 198200 kb
Host smart-096f363b-01c6-4f2f-bcb1-fc2c3c64c35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474575448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2474575448
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.540092255
Short name T60
Test name
Test status
Simulation time 86365418566 ps
CPU time 562.37 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:40:07 PM PDT 24
Peak memory 198208 kb
Host smart-44845bd5-4fa7-4200-8c79-a2ae9d90b28c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=540092255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.540092255
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.855655124
Short name T581
Test name
Test status
Simulation time 11059938 ps
CPU time 0.57 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 193920 kb
Host smart-36d2bcd3-cb95-4e2c-9762-02f7fc365a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855655124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.855655124
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.273674674
Short name T18
Test name
Test status
Simulation time 58908009 ps
CPU time 0.67 seconds
Started Apr 23 12:30:43 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 194928 kb
Host smart-fbde4b68-e03c-47ff-95ed-a094c0230636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273674674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.273674674
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.312346050
Short name T613
Test name
Test status
Simulation time 75354735 ps
CPU time 4.52 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:49 PM PDT 24
Peak memory 195724 kb
Host smart-14238da2-bc54-4109-bf68-12d1c03da257
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312346050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.312346050
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3040029234
Short name T188
Test name
Test status
Simulation time 637358355 ps
CPU time 0.94 seconds
Started Apr 23 12:30:44 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 196956 kb
Host smart-a1c918ab-f870-4af8-86d0-f1b88f6a8e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040029234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3040029234
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1390373215
Short name T704
Test name
Test status
Simulation time 278195232 ps
CPU time 1.32 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 196892 kb
Host smart-6066645f-ba84-4be9-9c1c-044e7acc222e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390373215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1390373215
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3700969589
Short name T301
Test name
Test status
Simulation time 48463277 ps
CPU time 2.04 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 198044 kb
Host smart-6f5b4769-60e7-4c85-8d0c-5e79300931a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700969589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3700969589
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2732677693
Short name T223
Test name
Test status
Simulation time 523602600 ps
CPU time 1.74 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 196848 kb
Host smart-b372843f-fd8a-4901-9673-64a6566f9b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732677693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2732677693
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.602266734
Short name T694
Test name
Test status
Simulation time 65242981 ps
CPU time 1.19 seconds
Started Apr 23 12:30:44 PM PDT 24
Finished Apr 23 12:30:47 PM PDT 24
Peak memory 196860 kb
Host smart-90149cd7-7cbb-4224-ad3c-e7dec3462da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602266734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.602266734
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1225140227
Short name T191
Test name
Test status
Simulation time 182895177 ps
CPU time 1.27 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 198056 kb
Host smart-5339d72e-ade1-4f2d-b356-9ad88138e1b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225140227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1225140227
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4240810795
Short name T507
Test name
Test status
Simulation time 1497380751 ps
CPU time 4.98 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 198100 kb
Host smart-faa0112f-3358-42fb-a2f2-dfd106a7f9a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240810795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4240810795
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2376494858
Short name T619
Test name
Test status
Simulation time 41588623 ps
CPU time 1.1 seconds
Started Apr 23 12:30:41 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 195492 kb
Host smart-a4929b82-cf45-4e15-9987-9f04bce01f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376494858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2376494858
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3950793031
Short name T70
Test name
Test status
Simulation time 228454066 ps
CPU time 1.17 seconds
Started Apr 23 12:30:42 PM PDT 24
Finished Apr 23 12:30:46 PM PDT 24
Peak memory 196508 kb
Host smart-7f973504-8adc-408d-ae88-6f285db7d21d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950793031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3950793031
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3263990790
Short name T147
Test name
Test status
Simulation time 134198544210 ps
CPU time 174.62 seconds
Started Apr 23 12:30:47 PM PDT 24
Finished Apr 23 12:33:43 PM PDT 24
Peak memory 198140 kb
Host smart-87062c78-0492-4e59-a386-c6a4f0288d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263990790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3263990790
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.640043775
Short name T287
Test name
Test status
Simulation time 15815715 ps
CPU time 0.61 seconds
Started Apr 23 12:30:49 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 194040 kb
Host smart-c25fad8c-0b3c-4f4d-8213-73c086cf2b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640043775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.640043775
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2883023852
Short name T442
Test name
Test status
Simulation time 201280478 ps
CPU time 0.84 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 196308 kb
Host smart-ebe916b0-4f3b-47c7-a72b-3dcff8b1e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883023852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2883023852
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4010355058
Short name T399
Test name
Test status
Simulation time 393440011 ps
CPU time 19.6 seconds
Started Apr 23 12:30:48 PM PDT 24
Finished Apr 23 12:31:09 PM PDT 24
Peak memory 195504 kb
Host smart-d3c4524f-1820-4922-b2d8-0fe07137e04d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010355058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4010355058
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.771364704
Short name T678
Test name
Test status
Simulation time 345205809 ps
CPU time 1.08 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:47 PM PDT 24
Peak memory 196676 kb
Host smart-4e657611-7f54-4da0-af3e-39ecadc091ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771364704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.771364704
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2544485214
Short name T187
Test name
Test status
Simulation time 23800361 ps
CPU time 0.69 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 194356 kb
Host smart-4955ec8c-7286-4816-b75c-ead324503385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544485214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2544485214
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3945734229
Short name T239
Test name
Test status
Simulation time 99621726 ps
CPU time 2.23 seconds
Started Apr 23 12:30:47 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 198040 kb
Host smart-05fcbf84-ac9b-43a4-b78c-44b857c53d45
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945734229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3945734229
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1101271873
Short name T552
Test name
Test status
Simulation time 359081320 ps
CPU time 3.37 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:51 PM PDT 24
Peak memory 197220 kb
Host smart-aa5e2949-542c-43f2-8d58-9a6a1d0556fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101271873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1101271873
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1111364556
Short name T330
Test name
Test status
Simulation time 86583834 ps
CPU time 0.8 seconds
Started Apr 23 12:30:48 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 196040 kb
Host smart-48f62456-618a-45b5-9440-74b9dfb2d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111364556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1111364556
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2605094726
Short name T473
Test name
Test status
Simulation time 15960810 ps
CPU time 0.77 seconds
Started Apr 23 12:30:47 PM PDT 24
Finished Apr 23 12:30:49 PM PDT 24
Peak memory 195396 kb
Host smart-6b3e9b36-693c-46af-a013-45dc8e861d50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605094726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2605094726
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.527318696
Short name T572
Test name
Test status
Simulation time 59359995 ps
CPU time 2.81 seconds
Started Apr 23 12:30:47 PM PDT 24
Finished Apr 23 12:30:51 PM PDT 24
Peak memory 198016 kb
Host smart-d66be060-562d-4c0b-b5ea-db45c0b52549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527318696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.527318696
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2301914655
Short name T515
Test name
Test status
Simulation time 140801464 ps
CPU time 1.53 seconds
Started Apr 23 12:30:48 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 197996 kb
Host smart-c0a75a0f-c725-4fe7-b60d-dd27ce2dfa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301914655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2301914655
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.669212717
Short name T327
Test name
Test status
Simulation time 68675954 ps
CPU time 1.07 seconds
Started Apr 23 12:30:48 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 195460 kb
Host smart-512dc7bb-20ed-4e3f-a37e-cd1e18dfcf01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669212717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.669212717
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1326689680
Short name T158
Test name
Test status
Simulation time 62099868762 ps
CPU time 133.08 seconds
Started Apr 23 12:30:45 PM PDT 24
Finished Apr 23 12:32:59 PM PDT 24
Peak memory 198100 kb
Host smart-e83454d5-ef3a-4f1c-9cb9-2aaf767ffe75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326689680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1326689680
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2782397541
Short name T563
Test name
Test status
Simulation time 298589839708 ps
CPU time 1754.42 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 01:00:01 PM PDT 24
Peak memory 198172 kb
Host smart-6641dd97-71c9-44d2-ab00-b60053af46e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2782397541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2782397541
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.221412998
Short name T490
Test name
Test status
Simulation time 40170338 ps
CPU time 0.57 seconds
Started Apr 23 12:30:50 PM PDT 24
Finished Apr 23 12:30:51 PM PDT 24
Peak memory 193892 kb
Host smart-06483a4b-fd4d-4ebd-a261-a6be1673e613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221412998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.221412998
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3908976996
Short name T283
Test name
Test status
Simulation time 24455842 ps
CPU time 0.8 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:30:53 PM PDT 24
Peak memory 195408 kb
Host smart-f5861a4b-3d3d-4036-b118-e0078d4ffa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908976996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3908976996
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1758971688
Short name T590
Test name
Test status
Simulation time 1580487032 ps
CPU time 15.28 seconds
Started Apr 23 12:30:49 PM PDT 24
Finished Apr 23 12:31:05 PM PDT 24
Peak memory 196412 kb
Host smart-cab283a1-1610-4216-9d48-ad423b40a63e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758971688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1758971688
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1472582371
Short name T628
Test name
Test status
Simulation time 223228535 ps
CPU time 0.94 seconds
Started Apr 23 12:30:50 PM PDT 24
Finished Apr 23 12:30:51 PM PDT 24
Peak memory 197916 kb
Host smart-c145c529-9c2d-4d89-8718-cc1d817aa885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472582371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1472582371
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1745157180
Short name T600
Test name
Test status
Simulation time 176732017 ps
CPU time 1.14 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 195968 kb
Host smart-bb5e5c0b-b079-43e3-8188-960f0aaa9f2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745157180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1745157180
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.730650162
Short name T371
Test name
Test status
Simulation time 346020258 ps
CPU time 3.52 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 198148 kb
Host smart-26246e3a-ba35-41e9-a3e7-b5d55caba9e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730650162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.730650162
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1813328430
Short name T705
Test name
Test status
Simulation time 327064449 ps
CPU time 3.26 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 198068 kb
Host smart-a2bfa3df-5d8d-48ce-a949-4dcc1232b0eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813328430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1813328430
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3062563567
Short name T165
Test name
Test status
Simulation time 149160940 ps
CPU time 1 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 195940 kb
Host smart-13d4b17e-625e-46cd-8d01-fb89577a75fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062563567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3062563567
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2399571843
Short name T368
Test name
Test status
Simulation time 309868909 ps
CPU time 1.2 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 198084 kb
Host smart-0a067131-5806-4e20-8d21-512398c271b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399571843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2399571843
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2315180423
Short name T657
Test name
Test status
Simulation time 65191140 ps
CPU time 1.59 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 198116 kb
Host smart-6d5a66e3-99e9-4544-83a1-3bf0f474d9a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315180423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2315180423
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1413172606
Short name T548
Test name
Test status
Simulation time 81660234 ps
CPU time 0.85 seconds
Started Apr 23 12:30:47 PM PDT 24
Finished Apr 23 12:30:49 PM PDT 24
Peak memory 195316 kb
Host smart-806d7fbb-fcdd-42dd-a1cf-c46c94ce2971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413172606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1413172606
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2675566241
Short name T348
Test name
Test status
Simulation time 365849977 ps
CPU time 1.5 seconds
Started Apr 23 12:30:46 PM PDT 24
Finished Apr 23 12:30:49 PM PDT 24
Peak memory 196364 kb
Host smart-10ad5a6c-7ebd-462e-975e-b94c66e5ba84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675566241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2675566241
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3622988350
Short name T272
Test name
Test status
Simulation time 19534025739 ps
CPU time 153.17 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:33:25 PM PDT 24
Peak memory 198124 kb
Host smart-5fb4daf9-1206-4048-97d3-09981f501f7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622988350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3622988350
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.659410894
Short name T606
Test name
Test status
Simulation time 96700681650 ps
CPU time 2221.24 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 01:07:53 PM PDT 24
Peak memory 198204 kb
Host smart-a701c2fe-d711-45a5-b13a-32afabc4b75a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=659410894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.659410894
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1639908004
Short name T649
Test name
Test status
Simulation time 11865458 ps
CPU time 0.56 seconds
Started Apr 23 12:30:14 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 194036 kb
Host smart-e36429a0-35f2-4814-94e2-69c7d1b8ac4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639908004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1639908004
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3433783891
Short name T199
Test name
Test status
Simulation time 243529399 ps
CPU time 0.86 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 195972 kb
Host smart-bd58702e-bac6-4eee-b45a-190441880fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433783891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3433783891
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.541165303
Short name T47
Test name
Test status
Simulation time 3126501210 ps
CPU time 20.92 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:30:34 PM PDT 24
Peak memory 196844 kb
Host smart-8140ded4-cb9f-49fc-9398-758c22300481
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541165303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.541165303
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4009415016
Short name T258
Test name
Test status
Simulation time 79826874 ps
CPU time 0.65 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 194592 kb
Host smart-70548b86-3cb5-4b38-bf06-1b91af7bcec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009415016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4009415016
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1505241384
Short name T696
Test name
Test status
Simulation time 362409013 ps
CPU time 1.4 seconds
Started Apr 23 12:30:09 PM PDT 24
Finished Apr 23 12:30:12 PM PDT 24
Peak memory 197160 kb
Host smart-ae15ffa4-8f98-416d-be99-981623ba0762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505241384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1505241384
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2520616418
Short name T161
Test name
Test status
Simulation time 37626487 ps
CPU time 1.53 seconds
Started Apr 23 12:30:12 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 197020 kb
Host smart-db208afe-afb6-4e49-a3e1-492ce1f5a98d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520616418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2520616418
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2572000854
Short name T150
Test name
Test status
Simulation time 123141043 ps
CPU time 2.9 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196712 kb
Host smart-640bba0f-5acd-42ff-bf22-8a99f8798954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572000854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2572000854
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.252176085
Short name T214
Test name
Test status
Simulation time 90872487 ps
CPU time 1.15 seconds
Started Apr 23 12:30:14 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 198100 kb
Host smart-03124fa1-b964-4272-83bc-7237a8b53ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252176085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.252176085
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3512393707
Short name T603
Test name
Test status
Simulation time 52675748 ps
CPU time 0.99 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:16 PM PDT 24
Peak memory 196016 kb
Host smart-a61e20e9-7963-4c41-aedd-ec465238de3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512393707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3512393707
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.960231113
Short name T350
Test name
Test status
Simulation time 66398587 ps
CPU time 1.59 seconds
Started Apr 23 12:30:12 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 198008 kb
Host smart-94db6b5b-8cde-4f4d-81b1-d102ffb81eaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960231113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.960231113
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.705807623
Short name T31
Test name
Test status
Simulation time 128412100 ps
CPU time 0.8 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:22 PM PDT 24
Peak memory 213628 kb
Host smart-648c87b8-07c2-4bba-87c3-87128bfdca5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705807623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.705807623
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.604174217
Short name T271
Test name
Test status
Simulation time 478655394 ps
CPU time 1.32 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 196368 kb
Host smart-b0136fdf-07c6-43ee-b14f-ea78f05deeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604174217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.604174217
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4090388035
Short name T244
Test name
Test status
Simulation time 26992885 ps
CPU time 0.81 seconds
Started Apr 23 12:30:14 PM PDT 24
Finished Apr 23 12:30:16 PM PDT 24
Peak memory 195184 kb
Host smart-4855d4b5-2ee8-4654-b2ff-c831f2f722ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090388035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4090388035
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4262512738
Short name T2
Test name
Test status
Simulation time 42098092373 ps
CPU time 92.07 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 198112 kb
Host smart-4dee3559-de3d-4fa5-928d-49581b1fc713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262512738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4262512738
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3955517600
Short name T534
Test name
Test status
Simulation time 119683334 ps
CPU time 0.63 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:30:52 PM PDT 24
Peak memory 194044 kb
Host smart-c5b095b0-8ffa-4100-9dda-7feb42b913c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955517600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3955517600
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3922135620
Short name T462
Test name
Test status
Simulation time 82976222 ps
CPU time 0.84 seconds
Started Apr 23 12:30:49 PM PDT 24
Finished Apr 23 12:30:51 PM PDT 24
Peak memory 196088 kb
Host smart-58f60110-977b-4a48-8a99-c3df515b0b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922135620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3922135620
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1206576346
Short name T169
Test name
Test status
Simulation time 614816081 ps
CPU time 16.77 seconds
Started Apr 23 12:30:49 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 195508 kb
Host smart-9bf376e4-44f2-4b54-bf85-c5651295518a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206576346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1206576346
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1835033126
Short name T450
Test name
Test status
Simulation time 51757117 ps
CPU time 0.91 seconds
Started Apr 23 12:30:58 PM PDT 24
Finished Apr 23 12:31:01 PM PDT 24
Peak memory 197228 kb
Host smart-07abc31b-8052-4018-9c60-35d065355f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835033126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1835033126
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2762495132
Short name T610
Test name
Test status
Simulation time 315614935 ps
CPU time 1.15 seconds
Started Apr 23 12:30:48 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 196108 kb
Host smart-ee99a0fc-7502-4326-8bc4-1b07c12fbbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762495132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2762495132
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2892767568
Short name T74
Test name
Test status
Simulation time 147668485 ps
CPU time 3 seconds
Started Apr 23 12:30:50 PM PDT 24
Finished Apr 23 12:30:54 PM PDT 24
Peak memory 198036 kb
Host smart-011a996d-1674-41c8-9483-76ee303268f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892767568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2892767568
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4041610103
Short name T145
Test name
Test status
Simulation time 103302257 ps
CPU time 1.89 seconds
Started Apr 23 12:30:50 PM PDT 24
Finished Apr 23 12:30:53 PM PDT 24
Peak memory 196288 kb
Host smart-d52aad6d-b1cc-4f92-8e54-cc5ea127f706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041610103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4041610103
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4233495090
Short name T667
Test name
Test status
Simulation time 115025016 ps
CPU time 1.31 seconds
Started Apr 23 12:30:52 PM PDT 24
Finished Apr 23 12:30:54 PM PDT 24
Peak memory 197020 kb
Host smart-37451a1f-538a-4c88-a865-5f22524750f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233495090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4233495090
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2283796405
Short name T666
Test name
Test status
Simulation time 60529489 ps
CPU time 0.76 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:30:53 PM PDT 24
Peak memory 195332 kb
Host smart-afe35132-0a93-44f0-a03b-e779445dfb74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283796405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2283796405
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1880460116
Short name T340
Test name
Test status
Simulation time 245937647 ps
CPU time 5.72 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 197932 kb
Host smart-7683f1b0-0e1a-46b9-83b3-d13af13d8f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880460116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1880460116
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1108057735
Short name T171
Test name
Test status
Simulation time 73316485 ps
CPU time 1.38 seconds
Started Apr 23 12:30:52 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 196648 kb
Host smart-fb2ce9a5-e638-4895-b450-64de9615fc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108057735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1108057735
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3422277593
Short name T359
Test name
Test status
Simulation time 174019985 ps
CPU time 1.23 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 196288 kb
Host smart-81c2b26b-9dce-4853-8e58-e641f3576a24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422277593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3422277593
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.252061037
Short name T102
Test name
Test status
Simulation time 17272907134 ps
CPU time 57.28 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:31:49 PM PDT 24
Peak memory 198324 kb
Host smart-93fff7a0-ca24-4e97-bb44-6feeee874fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252061037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.252061037
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.823008093
Short name T633
Test name
Test status
Simulation time 31629271 ps
CPU time 0.59 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 193892 kb
Host smart-769c5a04-66dd-4eb7-8e9a-a28bab0d8213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823008093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.823008093
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.545141910
Short name T514
Test name
Test status
Simulation time 99300858 ps
CPU time 0.95 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 195916 kb
Host smart-06956cae-e1ee-4f1f-a32a-7d2578c668a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545141910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.545141910
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3064552075
Short name T329
Test name
Test status
Simulation time 1612752039 ps
CPU time 15.18 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 195528 kb
Host smart-77c063e0-9086-4f3f-9f11-f32e43b27c42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064552075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3064552075
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4024859209
Short name T162
Test name
Test status
Simulation time 169254118 ps
CPU time 0.88 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 196480 kb
Host smart-fd98199d-88de-41f4-873a-13652430b9a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024859209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4024859209
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1716053508
Short name T513
Test name
Test status
Simulation time 54181280 ps
CPU time 2.29 seconds
Started Apr 23 12:30:51 PM PDT 24
Finished Apr 23 12:30:54 PM PDT 24
Peak memory 197972 kb
Host smart-3238f53f-3a97-428a-8ee7-5e612e69ada5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716053508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1716053508
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2242334899
Short name T186
Test name
Test status
Simulation time 473985502 ps
CPU time 2.4 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 197260 kb
Host smart-20d5a247-139b-45e3-94a0-31497ab903c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242334899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2242334899
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2862996710
Short name T484
Test name
Test status
Simulation time 28859327 ps
CPU time 1.08 seconds
Started Apr 23 12:30:52 PM PDT 24
Finished Apr 23 12:30:54 PM PDT 24
Peak memory 195800 kb
Host smart-277602ee-ef2f-4b45-ba1b-5fb945b92a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862996710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2862996710
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.114912917
Short name T536
Test name
Test status
Simulation time 44375742 ps
CPU time 0.96 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 196584 kb
Host smart-9608872e-58ce-439c-b8e6-d3fd8d71d0e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114912917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.114912917
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3829149213
Short name T456
Test name
Test status
Simulation time 890473604 ps
CPU time 3.74 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 198008 kb
Host smart-ee188fd2-b595-4f24-94b0-2e74b78a2c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829149213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3829149213
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.269475048
Short name T360
Test name
Test status
Simulation time 235188464 ps
CPU time 1.06 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:56 PM PDT 24
Peak memory 196520 kb
Host smart-3e1f351e-dc6c-47bd-ab3d-c7a107df05f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269475048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.269475048
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.575621694
Short name T153
Test name
Test status
Simulation time 191785639 ps
CPU time 1.11 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 195832 kb
Host smart-0ec70529-8bd0-4b70-b016-68c36b80df08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575621694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.575621694
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3741122108
Short name T122
Test name
Test status
Simulation time 4057754576 ps
CPU time 101.43 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:32:36 PM PDT 24
Peak memory 198120 kb
Host smart-87d2f17f-c446-42e3-ab76-17d1108504b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741122108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3741122108
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1722833485
Short name T464
Test name
Test status
Simulation time 37743514 ps
CPU time 0.58 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 193880 kb
Host smart-27996ffd-9b23-4b47-a176-c98a3f697035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722833485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1722833485
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3773425388
Short name T125
Test name
Test status
Simulation time 45366521 ps
CPU time 0.84 seconds
Started Apr 23 12:30:56 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 195412 kb
Host smart-fd85319e-2516-42b6-8482-4c51f0c3d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773425388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3773425388
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2811670906
Short name T522
Test name
Test status
Simulation time 1551200689 ps
CPU time 19.81 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:31:17 PM PDT 24
Peak memory 197108 kb
Host smart-58b6b298-7393-48b6-b201-c64f7f971e47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811670906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2811670906
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1918279129
Short name T595
Test name
Test status
Simulation time 98942087 ps
CPU time 0.63 seconds
Started Apr 23 12:30:56 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 195292 kb
Host smart-97c7efb4-fb2b-4e21-b754-ec571dfab7ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918279129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1918279129
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1946823563
Short name T547
Test name
Test status
Simulation time 154740362 ps
CPU time 0.92 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 197236 kb
Host smart-68ee1bcb-5249-477f-a1c0-a126f0155001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946823563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1946823563
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.391364660
Short name T263
Test name
Test status
Simulation time 170787134 ps
CPU time 3.23 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 197824 kb
Host smart-8b97ff75-92b6-4b85-9a6f-3f2245e98f0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391364660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.391364660
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2261598351
Short name T375
Test name
Test status
Simulation time 68858553 ps
CPU time 2.14 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 197016 kb
Host smart-91b3ca59-d55f-41a0-84c7-8284a2e52448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261598351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2261598351
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.964039027
Short name T611
Test name
Test status
Simulation time 37568316 ps
CPU time 0.99 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 195960 kb
Host smart-5bc49ef4-c090-4cc1-85d9-f7113f060c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964039027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.964039027
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2667313075
Short name T139
Test name
Test status
Simulation time 35741365 ps
CPU time 1 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 196024 kb
Host smart-5e2a83ac-b1a1-4cbe-8ceb-c7a6d05c31bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667313075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2667313075
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3030719483
Short name T349
Test name
Test status
Simulation time 416006105 ps
CPU time 2.5 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 198100 kb
Host smart-69657fdb-cb2a-459f-9bfb-36e0e7d0dd5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030719483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3030719483
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1262420443
Short name T264
Test name
Test status
Simulation time 85865969 ps
CPU time 0.88 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 196448 kb
Host smart-9dd96bbb-8b84-4faf-a4f7-763842c6148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262420443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1262420443
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4057286604
Short name T370
Test name
Test status
Simulation time 87714245 ps
CPU time 1.26 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:56 PM PDT 24
Peak memory 196736 kb
Host smart-d88aae7e-84fa-44bf-81e6-735eedcefcd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057286604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4057286604
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.191922460
Short name T445
Test name
Test status
Simulation time 7761369917 ps
CPU time 214.44 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:34:33 PM PDT 24
Peak memory 198044 kb
Host smart-789e398b-aa55-44bb-8cf3-4af68f858ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191922460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.191922460
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.101520132
Short name T253
Test name
Test status
Simulation time 17878657 ps
CPU time 0.59 seconds
Started Apr 23 12:31:00 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 193880 kb
Host smart-052eb7ae-80fd-4500-bda3-3be0a5d60955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101520132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.101520132
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3896844050
Short name T206
Test name
Test status
Simulation time 14459912 ps
CPU time 0.6 seconds
Started Apr 23 12:30:56 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 193812 kb
Host smart-db8ef9de-3f5a-443b-a949-ee5f28b3acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896844050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3896844050
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4137626007
Short name T480
Test name
Test status
Simulation time 1921623689 ps
CPU time 16.7 seconds
Started Apr 23 12:30:56 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 196896 kb
Host smart-92184a6e-d373-4307-abad-a31a16b455cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137626007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4137626007
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2141026146
Short name T584
Test name
Test status
Simulation time 103929813 ps
CPU time 0.78 seconds
Started Apr 23 12:30:59 PM PDT 24
Finished Apr 23 12:31:01 PM PDT 24
Peak memory 195484 kb
Host smart-24a88036-2fe0-49c9-b21c-88f9e5f08ad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141026146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2141026146
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2913301387
Short name T407
Test name
Test status
Simulation time 22782808 ps
CPU time 0.77 seconds
Started Apr 23 12:30:54 PM PDT 24
Finished Apr 23 12:30:56 PM PDT 24
Peak memory 195428 kb
Host smart-0ea2c315-e684-4b49-8033-e73e3968ff67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913301387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2913301387
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2082135166
Short name T457
Test name
Test status
Simulation time 133258979 ps
CPU time 1.08 seconds
Started Apr 23 12:30:58 PM PDT 24
Finished Apr 23 12:31:01 PM PDT 24
Peak memory 196536 kb
Host smart-446f4035-63a3-4ec2-a1b3-70687a9009af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082135166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2082135166
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3377712219
Short name T559
Test name
Test status
Simulation time 105630073 ps
CPU time 2.27 seconds
Started Apr 23 12:30:59 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 198036 kb
Host smart-f91bc83c-057e-472c-8516-499e6191f297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377712219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3377712219
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.246048267
Short name T623
Test name
Test status
Simulation time 96532404 ps
CPU time 1.12 seconds
Started Apr 23 12:30:53 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 198040 kb
Host smart-6e52f2cb-6b5d-4d36-a4de-0a93b9caaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246048267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.246048267
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.442524207
Short name T568
Test name
Test status
Simulation time 49702043 ps
CPU time 1.17 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 196836 kb
Host smart-cbcc9eea-6d1f-477f-91a6-34c46f434132
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442524207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.442524207
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2682024759
Short name T571
Test name
Test status
Simulation time 1095020621 ps
CPU time 5.16 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:04 PM PDT 24
Peak memory 198072 kb
Host smart-2b943836-7e6b-45a0-a9c7-60f3f6f239ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682024759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2682024759
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1062292200
Short name T661
Test name
Test status
Simulation time 114129358 ps
CPU time 1.06 seconds
Started Apr 23 12:30:55 PM PDT 24
Finished Apr 23 12:30:57 PM PDT 24
Peak memory 195700 kb
Host smart-62017be4-9447-4d33-b2f2-06294b839c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062292200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1062292200
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3668308093
Short name T673
Test name
Test status
Simulation time 131837149 ps
CPU time 1.01 seconds
Started Apr 23 12:30:56 PM PDT 24
Finished Apr 23 12:30:58 PM PDT 24
Peak memory 197196 kb
Host smart-0ceeaa35-eebf-4e0d-9be2-daf45b9da7b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668308093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3668308093
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3529706482
Short name T412
Test name
Test status
Simulation time 10940475647 ps
CPU time 101.1 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:32:39 PM PDT 24
Peak memory 198048 kb
Host smart-674ee5a6-8d7d-45db-b1ca-8c57868b2efa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529706482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3529706482
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3787337565
Short name T306
Test name
Test status
Simulation time 77059211 ps
CPU time 0.61 seconds
Started Apr 23 12:31:00 PM PDT 24
Finished Apr 23 12:31:01 PM PDT 24
Peak memory 194064 kb
Host smart-6e82ce7c-35f6-4991-8c85-65b48813f526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787337565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3787337565
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1038843206
Short name T312
Test name
Test status
Simulation time 19235306 ps
CPU time 0.6 seconds
Started Apr 23 12:30:58 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 193980 kb
Host smart-2bcf4ca9-0a79-464b-bdbb-b1f4090d9400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038843206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1038843206
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1608301588
Short name T72
Test name
Test status
Simulation time 490654785 ps
CPU time 16.98 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:19 PM PDT 24
Peak memory 197104 kb
Host smart-40640d6a-bb0a-47be-a7e6-e8bb0326c9da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608301588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1608301588
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3209473373
Short name T218
Test name
Test status
Simulation time 75941395 ps
CPU time 0.62 seconds
Started Apr 23 12:30:59 PM PDT 24
Finished Apr 23 12:31:01 PM PDT 24
Peak memory 194356 kb
Host smart-085ec36d-be0d-479e-9108-516d9ebf717f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209473373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3209473373
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1650745155
Short name T446
Test name
Test status
Simulation time 50077641 ps
CPU time 0.96 seconds
Started Apr 23 12:30:59 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 197444 kb
Host smart-3c585e39-6a55-47fc-9d64-8dcb27135ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650745155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1650745155
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.12453955
Short name T231
Test name
Test status
Simulation time 149774262 ps
CPU time 1.8 seconds
Started Apr 23 12:31:00 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 196764 kb
Host smart-1cd2e342-74f8-4938-8a26-84fca0af69fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_intr_with_filter_rand_intr_event.12453955
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3908002785
Short name T164
Test name
Test status
Simulation time 277553975 ps
CPU time 3 seconds
Started Apr 23 12:30:59 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 196544 kb
Host smart-7179ecf9-34fd-4092-bc5e-d45865e5163b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908002785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3908002785
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4095995938
Short name T344
Test name
Test status
Simulation time 52449980 ps
CPU time 1.13 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:04 PM PDT 24
Peak memory 196936 kb
Host smart-cff05ae9-3a4d-4729-9cc7-e77858e4432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095995938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4095995938
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.185795967
Short name T632
Test name
Test status
Simulation time 52992763 ps
CPU time 1.16 seconds
Started Apr 23 12:30:57 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 198076 kb
Host smart-10c62240-1032-4d8c-a892-a0cf50695463
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185795967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.185795967
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2707483330
Short name T224
Test name
Test status
Simulation time 895109169 ps
CPU time 5.15 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 197976 kb
Host smart-9c2bd37a-46ad-4444-9298-0e526b1095e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707483330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2707483330
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.967354750
Short name T138
Test name
Test status
Simulation time 118772238 ps
CPU time 1.12 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 196708 kb
Host smart-455e1619-f64e-4182-a0a3-b2a38a5e8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967354750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.967354750
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3416480702
Short name T193
Test name
Test status
Simulation time 45224999 ps
CPU time 1.42 seconds
Started Apr 23 12:31:00 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 196608 kb
Host smart-f83cc244-b2ae-480a-9d9f-4a8261f3fd85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416480702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3416480702
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4232280442
Short name T305
Test name
Test status
Simulation time 12064287481 ps
CPU time 69.13 seconds
Started Apr 23 12:30:58 PM PDT 24
Finished Apr 23 12:32:09 PM PDT 24
Peak memory 198200 kb
Host smart-b9f5f2d7-5322-4240-b73c-3e755bebf711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232280442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4232280442
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3391497812
Short name T44
Test name
Test status
Simulation time 14753951 ps
CPU time 0.58 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 194700 kb
Host smart-d521b086-1e87-4c85-a66e-c0c55913d5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391497812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3391497812
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1176625248
Short name T309
Test name
Test status
Simulation time 42759516 ps
CPU time 0.76 seconds
Started Apr 23 12:31:02 PM PDT 24
Finished Apr 23 12:31:04 PM PDT 24
Peak memory 195212 kb
Host smart-33a61e9f-b535-46a3-a4be-102142ba45c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176625248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1176625248
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3431108324
Short name T501
Test name
Test status
Simulation time 460461850 ps
CPU time 16.42 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:29 PM PDT 24
Peak memory 195640 kb
Host smart-9688db59-b8c0-43b0-8fdc-b835fd57d847
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431108324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3431108324
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2006701435
Short name T505
Test name
Test status
Simulation time 154601168 ps
CPU time 0.88 seconds
Started Apr 23 12:31:04 PM PDT 24
Finished Apr 23 12:31:06 PM PDT 24
Peak memory 195800 kb
Host smart-61589860-cf0f-4f29-8861-86235dbddc6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006701435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2006701435
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3827875224
Short name T144
Test name
Test status
Simulation time 884460710 ps
CPU time 1.38 seconds
Started Apr 23 12:31:06 PM PDT 24
Finished Apr 23 12:31:08 PM PDT 24
Peak memory 198208 kb
Host smart-f4202efe-a6b7-4ad1-81a1-00fff96af5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827875224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3827875224
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2705416113
Short name T608
Test name
Test status
Simulation time 242221498 ps
CPU time 1.62 seconds
Started Apr 23 12:31:02 PM PDT 24
Finished Apr 23 12:31:05 PM PDT 24
Peak memory 196736 kb
Host smart-8a864031-cdb9-4212-9643-68faac4e6f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705416113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2705416113
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2554447026
Short name T535
Test name
Test status
Simulation time 473599320 ps
CPU time 1.13 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 196360 kb
Host smart-13057802-9bb6-44c9-9d6e-851af87a31ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554447026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2554447026
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4108996934
Short name T331
Test name
Test status
Simulation time 28950787 ps
CPU time 0.77 seconds
Started Apr 23 12:31:05 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 195440 kb
Host smart-7b26c7e3-dbf9-4d4e-b5a0-c0dcd91b61a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108996934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4108996934
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2795992679
Short name T316
Test name
Test status
Simulation time 169702639 ps
CPU time 3.68 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 198108 kb
Host smart-aaee9e4b-bc7d-4a57-add7-dad95065dceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795992679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2795992679
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4052451405
Short name T229
Test name
Test status
Simulation time 40808905 ps
CPU time 1.17 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 195884 kb
Host smart-3e4e6ff1-c31d-45bc-8258-969bdb02854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052451405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4052451405
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2741387402
Short name T660
Test name
Test status
Simulation time 119688354 ps
CPU time 1.22 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:03 PM PDT 24
Peak memory 195796 kb
Host smart-bbdf63f2-fdfb-4a31-ad40-8139aac9af8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741387402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2741387402
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1148203454
Short name T598
Test name
Test status
Simulation time 4669354368 ps
CPU time 51.64 seconds
Started Apr 23 12:31:01 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 198144 kb
Host smart-c02b9693-c825-4e75-aeea-ac321b28dd66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148203454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1148203454
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1019688078
Short name T384
Test name
Test status
Simulation time 168366257 ps
CPU time 0.57 seconds
Started Apr 23 12:31:08 PM PDT 24
Finished Apr 23 12:31:10 PM PDT 24
Peak memory 194596 kb
Host smart-963a8f55-ffad-41db-a6e3-e6dacc236632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019688078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1019688078
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2618224646
Short name T461
Test name
Test status
Simulation time 676240665 ps
CPU time 0.86 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 196512 kb
Host smart-364092dc-f69f-4e4c-8ea8-796247f254ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618224646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2618224646
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2038164130
Short name T432
Test name
Test status
Simulation time 1623615759 ps
CPU time 10.85 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 196912 kb
Host smart-bb752f0b-a481-440a-8249-d9bf18e3e9eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038164130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2038164130
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.631053917
Short name T149
Test name
Test status
Simulation time 81285238 ps
CPU time 0.98 seconds
Started Apr 23 12:31:03 PM PDT 24
Finished Apr 23 12:31:05 PM PDT 24
Peak memory 196368 kb
Host smart-8d1d8dbc-25b4-41d3-99f5-ec194fb7c35b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631053917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.631053917
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2462357198
Short name T527
Test name
Test status
Simulation time 202381228 ps
CPU time 1.46 seconds
Started Apr 23 12:31:02 PM PDT 24
Finished Apr 23 12:31:04 PM PDT 24
Peak memory 196980 kb
Host smart-32f9b7d9-c7b7-47a2-9f3f-3a125824988a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462357198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2462357198
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.152124164
Short name T566
Test name
Test status
Simulation time 534593083 ps
CPU time 2.94 seconds
Started Apr 23 12:31:02 PM PDT 24
Finished Apr 23 12:31:06 PM PDT 24
Peak memory 198148 kb
Host smart-3132eb6d-a81e-41b6-9d68-c6b9b9f44354
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152124164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.152124164
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.415304738
Short name T198
Test name
Test status
Simulation time 342274196 ps
CPU time 2 seconds
Started Apr 23 12:31:02 PM PDT 24
Finished Apr 23 12:31:06 PM PDT 24
Peak memory 196532 kb
Host smart-a21c4931-9086-4971-8b0b-cf1e75d1b7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415304738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
415304738
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2748073039
Short name T394
Test name
Test status
Simulation time 97795640 ps
CPU time 1.09 seconds
Started Apr 23 12:31:05 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 195836 kb
Host smart-b34c153c-6ae4-42b1-8428-ae8de8e3eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748073039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2748073039
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.243599748
Short name T509
Test name
Test status
Simulation time 44689735 ps
CPU time 0.95 seconds
Started Apr 23 12:31:05 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 195972 kb
Host smart-0dea2cae-ed46-49d5-9730-e5af4db8f0db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243599748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.243599748
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3283388690
Short name T117
Test name
Test status
Simulation time 709123543 ps
CPU time 3.16 seconds
Started Apr 23 12:31:03 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 198168 kb
Host smart-ae424c80-a82e-4465-9ca4-94b6332d3525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283388690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3283388690
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3723731311
Short name T627
Test name
Test status
Simulation time 132882220 ps
CPU time 0.97 seconds
Started Apr 23 12:31:03 PM PDT 24
Finished Apr 23 12:31:05 PM PDT 24
Peak memory 196340 kb
Host smart-8c99cb76-cfc0-4180-8e21-be61bad946a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723731311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3723731311
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2017084793
Short name T452
Test name
Test status
Simulation time 53316891 ps
CPU time 0.96 seconds
Started Apr 23 12:31:04 PM PDT 24
Finished Apr 23 12:31:06 PM PDT 24
Peak memory 196380 kb
Host smart-2ca8775e-eaa8-4088-a11b-66878f2661cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017084793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2017084793
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3468482186
Short name T519
Test name
Test status
Simulation time 57375856 ps
CPU time 0.6 seconds
Started Apr 23 12:31:08 PM PDT 24
Finished Apr 23 12:31:10 PM PDT 24
Peak memory 194812 kb
Host smart-54f521dd-caee-4cff-bf6c-dca0d0e0b033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468482186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3468482186
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2477487751
Short name T415
Test name
Test status
Simulation time 30440200 ps
CPU time 0.92 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 196316 kb
Host smart-9aa3b04f-7c2e-434a-b8bb-bab071fde31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477487751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2477487751
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2889189779
Short name T339
Test name
Test status
Simulation time 772964864 ps
CPU time 9 seconds
Started Apr 23 12:31:17 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 197016 kb
Host smart-f9a07c82-8341-4be4-9d78-a707fb627981
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889189779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2889189779
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2628112967
Short name T691
Test name
Test status
Simulation time 40019254 ps
CPU time 0.76 seconds
Started Apr 23 12:31:12 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 195516 kb
Host smart-1348388b-4e10-4f9a-8e64-48f8fd5ab674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628112967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2628112967
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.27860800
Short name T506
Test name
Test status
Simulation time 99752185 ps
CPU time 1.39 seconds
Started Apr 23 12:31:12 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 197044 kb
Host smart-6034ffbb-a4a9-45b3-93e7-4f6db19fc406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27860800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.27860800
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.907341678
Short name T626
Test name
Test status
Simulation time 22084887 ps
CPU time 1.02 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 196128 kb
Host smart-d80f5f3d-4f9a-49bc-998e-4c28ccbacee7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907341678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.907341678
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1936017212
Short name T76
Test name
Test status
Simulation time 90134906 ps
CPU time 0.94 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 195596 kb
Host smart-42c64f25-bdb9-4b18-89cf-c1b08884306a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936017212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1936017212
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3724357800
Short name T77
Test name
Test status
Simulation time 316993724 ps
CPU time 0.8 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:31:11 PM PDT 24
Peak memory 195508 kb
Host smart-21056023-493d-40ff-bea2-65836db09880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724357800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3724357800
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1330522821
Short name T641
Test name
Test status
Simulation time 48394269 ps
CPU time 0.95 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 196076 kb
Host smart-38e96f98-bcbf-4ec8-9ca3-e09cb8a64502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330522821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1330522821
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3642483368
Short name T209
Test name
Test status
Simulation time 93305343 ps
CPU time 1.22 seconds
Started Apr 23 12:31:12 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 198008 kb
Host smart-7f98f67b-7558-4ecb-a1cb-7676e4d32c34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642483368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3642483368
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.4165240137
Short name T52
Test name
Test status
Simulation time 39079808 ps
CPU time 0.81 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 196048 kb
Host smart-2feac685-9f0e-4ac5-991d-4fe8d156d237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165240137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.4165240137
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4256738359
Short name T281
Test name
Test status
Simulation time 335965736 ps
CPU time 0.96 seconds
Started Apr 23 12:31:08 PM PDT 24
Finished Apr 23 12:31:11 PM PDT 24
Peak memory 196228 kb
Host smart-d7e28a39-c9ed-4af2-8082-a5c6d5c53101
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256738359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4256738359
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4077154194
Short name T342
Test name
Test status
Simulation time 7313984944 ps
CPU time 209.15 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:34:39 PM PDT 24
Peak memory 198120 kb
Host smart-2913e19f-443c-438f-ba31-876aba899b97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077154194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4077154194
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2891406730
Short name T583
Test name
Test status
Simulation time 20770445 ps
CPU time 0.61 seconds
Started Apr 23 12:31:12 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 193908 kb
Host smart-8cae2853-856a-43fc-845c-494ebea6c2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891406730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2891406730
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3057142690
Short name T458
Test name
Test status
Simulation time 67664158 ps
CPU time 0.67 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 194124 kb
Host smart-37e16853-58ce-4ca1-935b-a6bb0958527a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057142690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3057142690
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1521929242
Short name T180
Test name
Test status
Simulation time 1826733659 ps
CPU time 21.93 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:31:32 PM PDT 24
Peak memory 198004 kb
Host smart-ec0bff10-7903-4b38-a1ea-912df92faf9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521929242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1521929242
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.485037565
Short name T174
Test name
Test status
Simulation time 160393211 ps
CPU time 0.78 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 195868 kb
Host smart-1e47be9b-31af-4977-8845-c76f1c0f197f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485037565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.485037565
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.129093242
Short name T104
Test name
Test status
Simulation time 47168659 ps
CPU time 1.23 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 198004 kb
Host smart-20878dc1-948d-4a1b-9dca-8e5fc0e72116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129093242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.129093242
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2761620746
Short name T468
Test name
Test status
Simulation time 69457327 ps
CPU time 2.52 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 198004 kb
Host smart-6d267fdb-57c5-4ea8-8e29-9993e1ab429e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761620746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2761620746
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3462670352
Short name T695
Test name
Test status
Simulation time 117482627 ps
CPU time 1.17 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 196632 kb
Host smart-c7ea972c-9e2e-4a17-80da-713795d6a7b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462670352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3462670352
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1380966486
Short name T189
Test name
Test status
Simulation time 34816966 ps
CPU time 0.88 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 195804 kb
Host smart-c008efab-92ee-4956-af92-ec98c876c0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380966486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1380966486
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1846737090
Short name T194
Test name
Test status
Simulation time 106649925 ps
CPU time 1.18 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 196664 kb
Host smart-2ef2e36d-7013-461d-8519-8feb1dedc0f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846737090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1846737090
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1408600984
Short name T357
Test name
Test status
Simulation time 197395556 ps
CPU time 4.64 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 198008 kb
Host smart-75d34693-b7e9-4ba5-b725-14b6e239bf2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408600984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1408600984
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2565125089
Short name T276
Test name
Test status
Simulation time 66963002 ps
CPU time 0.84 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 195392 kb
Host smart-070aedbe-c1db-4e22-8d9a-b67824d014d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565125089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2565125089
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.359592458
Short name T251
Test name
Test status
Simulation time 891431523 ps
CPU time 1.22 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 195464 kb
Host smart-c68eff8f-d165-416f-a4da-3be0b255fd2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359592458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.359592458
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3815934309
Short name T543
Test name
Test status
Simulation time 25686112795 ps
CPU time 150 seconds
Started Apr 23 12:31:09 PM PDT 24
Finished Apr 23 12:33:41 PM PDT 24
Peak memory 198116 kb
Host smart-c83f6eb6-3038-43de-b40c-23fc27ebfbf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815934309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3815934309
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.210348704
Short name T487
Test name
Test status
Simulation time 112032725514 ps
CPU time 1662.69 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:58:54 PM PDT 24
Peak memory 198228 kb
Host smart-88f4cf59-4183-4ebc-9d33-18b2dbbf1df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=210348704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.210348704
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3803722894
Short name T207
Test name
Test status
Simulation time 10585194 ps
CPU time 0.6 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 194672 kb
Host smart-f626b9e7-a278-4f45-b2b0-03c99e9ab41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803722894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3803722894
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4107312833
Short name T148
Test name
Test status
Simulation time 184273864 ps
CPU time 0.95 seconds
Started Apr 23 12:31:16 PM PDT 24
Finished Apr 23 12:31:18 PM PDT 24
Peak memory 195712 kb
Host smart-05e8b598-997e-4a65-b161-14b5edd95784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107312833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4107312833
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.438538061
Short name T550
Test name
Test status
Simulation time 4257374552 ps
CPU time 10.99 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 198096 kb
Host smart-b19bee09-44c1-4641-9ae5-7b98497c2e71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438538061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.438538061
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3599760572
Short name T640
Test name
Test status
Simulation time 96458737 ps
CPU time 0.66 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 195040 kb
Host smart-27b0e180-ed9a-4995-a58d-1a25dc976156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599760572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3599760572
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.789150036
Short name T268
Test name
Test status
Simulation time 61305837 ps
CPU time 0.7 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 195452 kb
Host smart-0c1de37c-62e6-469f-bb65-8a295a07b27f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789150036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.789150036
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.723334561
Short name T234
Test name
Test status
Simulation time 70177770 ps
CPU time 1.81 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:18 PM PDT 24
Peak memory 196512 kb
Host smart-cb0c06b6-d1a3-4b22-b08f-b0022d449d37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723334561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.723334561
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3596732497
Short name T455
Test name
Test status
Simulation time 169313004 ps
CPU time 1.5 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 196164 kb
Host smart-71c0fa50-049e-46ac-9c1c-1c80e0947f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596732497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3596732497
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4049170587
Short name T183
Test name
Test status
Simulation time 189425869 ps
CPU time 1.08 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 196008 kb
Host smart-8a508717-8afd-4ddf-b368-6f00dfd7bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049170587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4049170587
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4272651690
Short name T69
Test name
Test status
Simulation time 41480233 ps
CPU time 0.93 seconds
Started Apr 23 12:31:10 PM PDT 24
Finished Apr 23 12:31:13 PM PDT 24
Peak memory 196664 kb
Host smart-b8f5bc2f-f9b0-4140-a46b-954c4ba089e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272651690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4272651690
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.558148402
Short name T520
Test name
Test status
Simulation time 80697390 ps
CPU time 1.69 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 197712 kb
Host smart-c0400e5a-c747-459e-bdb0-b907c75858e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558148402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.558148402
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3183051143
Short name T280
Test name
Test status
Simulation time 93892125 ps
CPU time 1.36 seconds
Started Apr 23 12:31:08 PM PDT 24
Finished Apr 23 12:31:11 PM PDT 24
Peak memory 196728 kb
Host smart-e3a11f33-41df-4e50-b933-36b36a37e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183051143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3183051143
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3716305336
Short name T397
Test name
Test status
Simulation time 223104899 ps
CPU time 1.05 seconds
Started Apr 23 12:31:11 PM PDT 24
Finished Apr 23 12:31:14 PM PDT 24
Peak memory 195812 kb
Host smart-27b0bf32-37c6-43b5-a8bd-077599b71773
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716305336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3716305336
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2024026001
Short name T585
Test name
Test status
Simulation time 6451309596 ps
CPU time 38.24 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 198040 kb
Host smart-0e5e3d38-72f7-448a-ab9c-d18df1ea8f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024026001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2024026001
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1204806825
Short name T544
Test name
Test status
Simulation time 11191310 ps
CPU time 0.56 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 193884 kb
Host smart-e9864abf-b3a5-429a-8b05-eeaf177d17ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204806825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1204806825
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.621106921
Short name T256
Test name
Test status
Simulation time 565804236 ps
CPU time 0.9 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 196800 kb
Host smart-8f0335e6-ddab-4e42-8b8b-7b5a7c7c0882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621106921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.621106921
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.369966955
Short name T512
Test name
Test status
Simulation time 1103618661 ps
CPU time 10.07 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 196424 kb
Host smart-ead1db68-fac2-4343-9fdd-371d49f75cf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369966955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.369966955
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2176495989
Short name T467
Test name
Test status
Simulation time 294204387 ps
CPU time 1.11 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196060 kb
Host smart-b07326ce-09a6-4bb3-8939-56c3bf49ccfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176495989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2176495989
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.577086957
Short name T580
Test name
Test status
Simulation time 77937018 ps
CPU time 0.71 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 194376 kb
Host smart-3553d987-85a7-4b14-9362-24a55c1dd14f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577086957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.577086957
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.431275285
Short name T444
Test name
Test status
Simulation time 59664038 ps
CPU time 0.93 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:30:13 PM PDT 24
Peak memory 196852 kb
Host smart-b3e6e0f1-6fef-441a-a26b-0753731c23a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431275285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.431275285
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1863699075
Short name T260
Test name
Test status
Simulation time 507476430 ps
CPU time 2.4 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 197060 kb
Host smart-efb2934a-3000-4179-bd02-59bb85c2cb20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863699075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1863699075
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.759295126
Short name T479
Test name
Test status
Simulation time 49714357 ps
CPU time 0.92 seconds
Started Apr 23 12:30:12 PM PDT 24
Finished Apr 23 12:30:14 PM PDT 24
Peak memory 195984 kb
Host smart-30491502-41dd-4f9a-8821-cbcc921976ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759295126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.759295126
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2750364497
Short name T325
Test name
Test status
Simulation time 52694773 ps
CPU time 1.06 seconds
Started Apr 23 12:30:12 PM PDT 24
Finished Apr 23 12:30:14 PM PDT 24
Peak memory 196520 kb
Host smart-155a5855-3373-4c1c-a6a0-20205c3c7fc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750364497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2750364497
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3742784303
Short name T491
Test name
Test status
Simulation time 376094336 ps
CPU time 3.08 seconds
Started Apr 23 12:30:10 PM PDT 24
Finished Apr 23 12:30:14 PM PDT 24
Peak memory 198000 kb
Host smart-17090e54-ee73-4ad3-b74b-bf6cdb30ff74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742784303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3742784303
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.305077676
Short name T45
Test name
Test status
Simulation time 42566479 ps
CPU time 0.81 seconds
Started Apr 23 12:30:20 PM PDT 24
Finished Apr 23 12:30:22 PM PDT 24
Peak memory 213548 kb
Host smart-06e97f54-a58b-4af1-9384-7b96a85d174f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305077676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.305077676
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3080236997
Short name T681
Test name
Test status
Simulation time 22312081 ps
CPU time 0.84 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196088 kb
Host smart-598375d0-ca2a-4127-b7b1-95b90bccd817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080236997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3080236997
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3391723892
Short name T435
Test name
Test status
Simulation time 142248273 ps
CPU time 1.26 seconds
Started Apr 23 12:30:13 PM PDT 24
Finished Apr 23 12:30:15 PM PDT 24
Peak memory 197984 kb
Host smart-66688aea-76f6-452b-ae4f-612366cf84af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391723892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3391723892
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2069588208
Short name T524
Test name
Test status
Simulation time 46967112721 ps
CPU time 157.94 seconds
Started Apr 23 12:30:14 PM PDT 24
Finished Apr 23 12:32:54 PM PDT 24
Peak memory 198116 kb
Host smart-b1dd8700-f58e-4e42-979a-356a6da4330b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069588208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2069588208
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2650860696
Short name T367
Test name
Test status
Simulation time 11575521 ps
CPU time 0.59 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 193856 kb
Host smart-b1b5095f-32a3-4595-9336-4c7611e14c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650860696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2650860696
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1631878948
Short name T518
Test name
Test status
Simulation time 32724126 ps
CPU time 0.77 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 195352 kb
Host smart-9b73262a-c0a6-45be-b838-5ec89a61a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631878948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1631878948
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2844635072
Short name T196
Test name
Test status
Simulation time 2033471464 ps
CPU time 11.24 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:28 PM PDT 24
Peak memory 197064 kb
Host smart-d9040a0d-06fc-488a-9071-c516e1f96c44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844635072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2844635072
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1954397450
Short name T7
Test name
Test status
Simulation time 107871677 ps
CPU time 0.86 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 195944 kb
Host smart-c5c7f921-66ab-444f-8d12-7e556f578ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954397450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1954397450
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3176036613
Short name T185
Test name
Test status
Simulation time 61811917 ps
CPU time 0.76 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 196136 kb
Host smart-fe634b5c-7abc-4799-a245-aa161bf9fa9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176036613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3176036613
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4006167990
Short name T23
Test name
Test status
Simulation time 37946535 ps
CPU time 1.54 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 196940 kb
Host smart-b238ab25-a7a6-4f2a-a867-45f87de468df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006167990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4006167990
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2366679945
Short name T392
Test name
Test status
Simulation time 103724347 ps
CPU time 3.1 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 197100 kb
Host smart-b5500aa6-e07a-46f2-8fcc-91d39bf33056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366679945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2366679945
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2117190751
Short name T470
Test name
Test status
Simulation time 15205747 ps
CPU time 0.68 seconds
Started Apr 23 12:31:17 PM PDT 24
Finished Apr 23 12:31:18 PM PDT 24
Peak memory 194200 kb
Host smart-45d682d2-a6d2-4e29-8c3e-7d1c5bc57f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117190751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2117190751
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1052287608
Short name T405
Test name
Test status
Simulation time 52227864 ps
CPU time 0.99 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 196756 kb
Host smart-dd96d683-3d51-408c-b30c-86b2e4696950
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052287608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1052287608
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1666205993
Short name T128
Test name
Test status
Simulation time 241879564 ps
CPU time 5.81 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 197996 kb
Host smart-48d28b4a-a9d0-4f3c-9c19-c37fab3594ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666205993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1666205993
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.661238019
Short name T257
Test name
Test status
Simulation time 34716512 ps
CPU time 1.09 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 195728 kb
Host smart-0b6bf8c1-7669-41f3-b1d1-8b4787d8996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661238019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.661238019
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1345609619
Short name T634
Test name
Test status
Simulation time 50589177 ps
CPU time 0.98 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 195488 kb
Host smart-c9895731-895b-4d2e-9658-c88881f93909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345609619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1345609619
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1206656796
Short name T454
Test name
Test status
Simulation time 65856277253 ps
CPU time 121.19 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:33:16 PM PDT 24
Peak memory 198056 kb
Host smart-cad5dda3-fb21-4796-9d78-a38987095560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206656796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1206656796
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1211106500
Short name T676
Test name
Test status
Simulation time 84150533 ps
CPU time 0.55 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 193976 kb
Host smart-9505ed32-78e5-4575-9270-67bea885f92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211106500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1211106500
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2640779973
Short name T662
Test name
Test status
Simulation time 92542295 ps
CPU time 0.61 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 193960 kb
Host smart-7df56581-5a55-4d72-832d-f895ac2c5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640779973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2640779973
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1892977571
Short name T282
Test name
Test status
Simulation time 706788608 ps
CPU time 9.84 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 196928 kb
Host smart-dcf0c51b-7700-42c5-8b80-4ecb81a5eed4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892977571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1892977571
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.606628626
Short name T12
Test name
Test status
Simulation time 52468086 ps
CPU time 0.72 seconds
Started Apr 23 12:31:16 PM PDT 24
Finished Apr 23 12:31:17 PM PDT 24
Peak memory 194600 kb
Host smart-47094cab-0393-4ef3-a971-b87028144c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606628626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.606628626
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.634048841
Short name T246
Test name
Test status
Simulation time 132074223 ps
CPU time 0.79 seconds
Started Apr 23 12:31:13 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 196312 kb
Host smart-0b1f5237-6b75-46e3-965b-c5e9ef2b1230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634048841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.634048841
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2980221354
Short name T422
Test name
Test status
Simulation time 483811190 ps
CPU time 3.08 seconds
Started Apr 23 12:31:16 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 198116 kb
Host smart-85596d0e-e4de-4e28-bf3d-15988d814415
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980221354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2980221354
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3679791625
Short name T643
Test name
Test status
Simulation time 92443337 ps
CPU time 1.92 seconds
Started Apr 23 12:31:16 PM PDT 24
Finished Apr 23 12:31:19 PM PDT 24
Peak memory 196084 kb
Host smart-93c0711d-d1b5-4f80-a013-27e663aa3f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679791625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3679791625
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1590751178
Short name T554
Test name
Test status
Simulation time 266687700 ps
CPU time 1.29 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 198052 kb
Host smart-d0e0b667-4754-4a91-9992-fe3d94b9b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590751178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1590751178
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2838645598
Short name T154
Test name
Test status
Simulation time 293570714 ps
CPU time 1.32 seconds
Started Apr 23 12:31:15 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 197256 kb
Host smart-6bb5b63f-0223-449f-9e39-a16cbbf5f022
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838645598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2838645598
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3510262222
Short name T54
Test name
Test status
Simulation time 124994408 ps
CPU time 5.88 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 197996 kb
Host smart-2563309a-dcd0-452c-86ce-57ba11ebc4a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510262222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3510262222
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.544959065
Short name T338
Test name
Test status
Simulation time 186643144 ps
CPU time 1.34 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:17 PM PDT 24
Peak memory 196784 kb
Host smart-8cc1ecaa-fee3-41bb-9a02-e5a1777e5f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544959065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.544959065
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2610769431
Short name T391
Test name
Test status
Simulation time 188751589 ps
CPU time 1.01 seconds
Started Apr 23 12:31:14 PM PDT 24
Finished Apr 23 12:31:16 PM PDT 24
Peak memory 195632 kb
Host smart-dd37f65d-daee-4445-86cb-36ecdfc4cae6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610769431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2610769431
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3382131345
Short name T425
Test name
Test status
Simulation time 2276208904 ps
CPU time 32.1 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 198032 kb
Host smart-f942d077-0e3a-430c-a8f5-11ba85a0e894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382131345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3382131345
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.515946476
Short name T546
Test name
Test status
Simulation time 34944763 ps
CPU time 0.56 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 193852 kb
Host smart-b5efca81-1d74-4dea-849e-a7e20a39e151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515946476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.515946476
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.332523521
Short name T469
Test name
Test status
Simulation time 21686021 ps
CPU time 0.79 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:19 PM PDT 24
Peak memory 195940 kb
Host smart-8d000dd8-89c8-4785-9865-f0c407ea15a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332523521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.332523521
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1483220202
Short name T577
Test name
Test status
Simulation time 574954990 ps
CPU time 14.66 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:36 PM PDT 24
Peak memory 197028 kb
Host smart-160c0615-9b7f-4b64-962f-e5320af7219a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483220202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1483220202
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1632861246
Short name T21
Test name
Test status
Simulation time 221288569 ps
CPU time 0.84 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 196048 kb
Host smart-596876a8-af1d-4344-a508-36fe4a500494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632861246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1632861246
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3572517544
Short name T648
Test name
Test status
Simulation time 77632061 ps
CPU time 1.22 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 196324 kb
Host smart-0d8ba404-2444-4a47-a180-a1494b2c7f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572517544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3572517544
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2411157226
Short name T49
Test name
Test status
Simulation time 81960264 ps
CPU time 3.17 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:33 PM PDT 24
Peak memory 198044 kb
Host smart-ecf1ef5e-6de3-4710-bd2b-638771df8f99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411157226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2411157226
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.15575412
Short name T222
Test name
Test status
Simulation time 274134925 ps
CPU time 0.91 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 196284 kb
Host smart-d137002d-0028-462c-abf5-a7630106917f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.15575412
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4179044690
Short name T155
Test name
Test status
Simulation time 68601913 ps
CPU time 1.02 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 196052 kb
Host smart-4cf3b51b-8f53-4e7a-a386-e4e453eba70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179044690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4179044690
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1921405210
Short name T156
Test name
Test status
Simulation time 107476228 ps
CPU time 0.77 seconds
Started Apr 23 12:31:25 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 195496 kb
Host smart-bf81dfac-3fae-4eab-a87c-7725f38deb0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921405210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1921405210
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1947826018
Short name T499
Test name
Test status
Simulation time 390586254 ps
CPU time 5.96 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 197992 kb
Host smart-d0e4d934-be60-4168-b580-4e479d010e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947826018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1947826018
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3236573684
Short name T620
Test name
Test status
Simulation time 746071425 ps
CPU time 0.94 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 195608 kb
Host smart-5ef0cf0a-c4b2-447b-afd3-cdb9abe88367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236573684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3236573684
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2830468474
Short name T532
Test name
Test status
Simulation time 95628145 ps
CPU time 1.39 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 195528 kb
Host smart-47a7ca69-6e43-4cfd-93e5-6ab7a6f04c85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830468474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2830468474
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1768321571
Short name T358
Test name
Test status
Simulation time 15438136634 ps
CPU time 195.25 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:34:44 PM PDT 24
Peak memory 198044 kb
Host smart-6440c0a3-5c2d-4a83-8bce-c057f08da814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768321571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1768321571
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1823933835
Short name T703
Test name
Test status
Simulation time 97111022 ps
CPU time 0.6 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:19 PM PDT 24
Peak memory 194528 kb
Host smart-28016818-f7d9-47f1-a146-310d696f26de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823933835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1823933835
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3764993985
Short name T380
Test name
Test status
Simulation time 40199795 ps
CPU time 0.83 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 196560 kb
Host smart-e200913d-dac3-49d7-b792-a5a633bdb9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764993985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3764993985
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2376747322
Short name T403
Test name
Test status
Simulation time 379364410 ps
CPU time 10.29 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 197168 kb
Host smart-39b9c9d6-3357-4230-9791-0159e294783d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376747322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2376747322
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.373198170
Short name T386
Test name
Test status
Simulation time 275581656 ps
CPU time 0.92 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 197024 kb
Host smart-dcd9e889-13a3-43a1-a1ca-0e63807dd9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373198170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.373198170
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3987258548
Short name T402
Test name
Test status
Simulation time 25966980 ps
CPU time 0.8 seconds
Started Apr 23 12:31:26 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 195684 kb
Host smart-31bcc297-d441-4745-a9b2-f5de86e9bccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987258548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3987258548
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1574106941
Short name T181
Test name
Test status
Simulation time 48530430 ps
CPU time 0.87 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 196780 kb
Host smart-d72f5a77-f7a6-4af8-ac5e-f456d9e51a42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574106941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1574106941
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.816342424
Short name T347
Test name
Test status
Simulation time 47721594 ps
CPU time 1.31 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 197432 kb
Host smart-d5264a1e-27b1-4c8a-ab06-20e8ec23ceb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816342424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
816342424
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2753124343
Short name T79
Test name
Test status
Simulation time 31173654 ps
CPU time 1.14 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 197128 kb
Host smart-dcc49739-b8dc-47eb-9869-b00d25d6468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753124343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2753124343
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3656603258
Short name T517
Test name
Test status
Simulation time 35142652 ps
CPU time 0.69 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 195084 kb
Host smart-63250329-2989-45de-a51c-c8f4c7850c09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656603258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3656603258
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2976280891
Short name T275
Test name
Test status
Simulation time 353199447 ps
CPU time 5.92 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:28 PM PDT 24
Peak memory 197948 kb
Host smart-01f54631-392d-4546-ae22-f32c59322022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976280891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2976280891
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2278919982
Short name T261
Test name
Test status
Simulation time 458520854 ps
CPU time 1.39 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 196600 kb
Host smart-341efb73-44cc-4f24-8441-0e35e8627f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278919982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2278919982
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.892293667
Short name T337
Test name
Test status
Simulation time 23717115 ps
CPU time 0.78 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 195276 kb
Host smart-80d847ac-e93f-47d5-a727-057b584a9c26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892293667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.892293667
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3947041861
Short name T274
Test name
Test status
Simulation time 5516865961 ps
CPU time 144.19 seconds
Started Apr 23 12:31:27 PM PDT 24
Finished Apr 23 12:33:52 PM PDT 24
Peak memory 198208 kb
Host smart-f51e7706-b76a-46cd-b3a3-25bc20f7773c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947041861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3947041861
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2164289561
Short name T57
Test name
Test status
Simulation time 169352443273 ps
CPU time 2197.13 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 01:07:58 PM PDT 24
Peak memory 198216 kb
Host smart-e8ed7ad6-342b-47d9-be97-063499d2f4d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2164289561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2164289561
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3763009181
Short name T372
Test name
Test status
Simulation time 34903667 ps
CPU time 0.57 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 193908 kb
Host smart-b5731ae8-251d-4f58-b8b4-9d01a735fe88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763009181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3763009181
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1087701708
Short name T296
Test name
Test status
Simulation time 187366077 ps
CPU time 0.88 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 196416 kb
Host smart-bb099ebd-fc73-4cc8-86e0-7efdb93d9f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087701708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1087701708
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4009826182
Short name T616
Test name
Test status
Simulation time 515265548 ps
CPU time 17.89 seconds
Started Apr 23 12:31:25 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 196784 kb
Host smart-55467ac1-53a7-43be-a7b5-a641a7a108dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009826182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4009826182
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.390240087
Short name T4
Test name
Test status
Simulation time 282865850 ps
CPU time 0.87 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 195932 kb
Host smart-00277eba-8b60-4521-9f2f-f890a0054720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390240087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.390240087
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.132390900
Short name T582
Test name
Test status
Simulation time 87390876 ps
CPU time 0.82 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:19 PM PDT 24
Peak memory 195388 kb
Host smart-4a87d885-5f79-44f3-8a2f-6098441d16ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132390900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.132390900
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1715397175
Short name T353
Test name
Test status
Simulation time 94235946 ps
CPU time 1.59 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 196584 kb
Host smart-5776c616-91e9-4351-bb18-d9dc0ff5a4d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715397175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1715397175
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2263184076
Short name T453
Test name
Test status
Simulation time 517537009 ps
CPU time 2.72 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 198064 kb
Host smart-ae34f53a-ba2d-45c8-9005-3bb6ca83bda7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263184076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2263184076
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.303893477
Short name T430
Test name
Test status
Simulation time 67110373 ps
CPU time 1.21 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 198036 kb
Host smart-b533e516-596b-44e1-bd74-150f130cc17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303893477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.303893477
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4047082947
Short name T706
Test name
Test status
Simulation time 26863120 ps
CPU time 1.09 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:30 PM PDT 24
Peak memory 195828 kb
Host smart-0f7cec24-33ed-4a8b-acef-172150721afa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047082947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4047082947
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3849006828
Short name T176
Test name
Test status
Simulation time 262662924 ps
CPU time 4.42 seconds
Started Apr 23 12:31:18 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 197980 kb
Host smart-cfa474f0-54ba-40cd-b2bd-56fe989540d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849006828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3849006828
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2858878968
Short name T551
Test name
Test status
Simulation time 122268700 ps
CPU time 0.93 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 195232 kb
Host smart-0ccb1911-448b-479d-8072-43a4a8b4de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858878968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2858878968
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.86515476
Short name T679
Test name
Test status
Simulation time 82056908 ps
CPU time 1.02 seconds
Started Apr 23 12:31:20 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 196552 kb
Host smart-534afec8-9953-43a9-a0cd-1c5eeee0e223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86515476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.86515476
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2632251323
Short name T644
Test name
Test status
Simulation time 14957472439 ps
CPU time 170.21 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:34:15 PM PDT 24
Peak memory 198200 kb
Host smart-5e567b54-a8a2-487c-b579-4f83f717dadb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632251323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2632251323
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3428369136
Short name T393
Test name
Test status
Simulation time 14676613 ps
CPU time 0.58 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 194588 kb
Host smart-2e4e7ce1-f0ef-4619-a54a-d816ff72c2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428369136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3428369136
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.710296778
Short name T663
Test name
Test status
Simulation time 40343352 ps
CPU time 0.9 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 196572 kb
Host smart-18b94445-1693-4f9e-b674-2c46bbb206a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710296778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.710296778
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1761913329
Short name T698
Test name
Test status
Simulation time 162709292 ps
CPU time 5.48 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:28 PM PDT 24
Peak memory 196816 kb
Host smart-583ab569-ac2d-4881-bf9a-6e20cdd7091d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761913329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1761913329
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2098648377
Short name T560
Test name
Test status
Simulation time 61127463 ps
CPU time 0.93 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 197284 kb
Host smart-884adc44-1302-4db6-9b96-b4b15b91f5e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098648377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2098648377
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.831140077
Short name T146
Test name
Test status
Simulation time 181783181 ps
CPU time 1.09 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 196828 kb
Host smart-1bb5f9e3-ba63-47bc-8a18-50c3bdd331a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831140077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.831140077
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2215066068
Short name T578
Test name
Test status
Simulation time 46181295 ps
CPU time 1.85 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 198168 kb
Host smart-0e75978d-bf3d-46d6-b0e7-010d408e2b8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215066068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2215066068
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1320007867
Short name T137
Test name
Test status
Simulation time 703990483 ps
CPU time 1.21 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 196484 kb
Host smart-46cd1276-3cd5-40fd-8e53-bf2c27412256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320007867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1320007867
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2311340227
Short name T417
Test name
Test status
Simulation time 286899105 ps
CPU time 1.4 seconds
Started Apr 23 12:31:25 PM PDT 24
Finished Apr 23 12:31:28 PM PDT 24
Peak memory 196980 kb
Host smart-aab700ca-42b5-4693-aeab-1d3ec5eff53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311340227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2311340227
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2580596684
Short name T658
Test name
Test status
Simulation time 115838355 ps
CPU time 1.2 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:25 PM PDT 24
Peak memory 195936 kb
Host smart-9c854fb9-7c56-40cf-bb0c-47c140a60b47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580596684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2580596684
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1758760218
Short name T22
Test name
Test status
Simulation time 1943820910 ps
CPU time 5.87 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 197960 kb
Host smart-386819aa-e0fa-4362-b174-276491abb634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758760218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1758760218
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2409540517
Short name T343
Test name
Test status
Simulation time 120026460 ps
CPU time 1.24 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 196768 kb
Host smart-69c04c2a-a06f-46fb-a304-b7e09083e9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409540517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2409540517
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3782942617
Short name T369
Test name
Test status
Simulation time 369102305 ps
CPU time 0.92 seconds
Started Apr 23 12:31:19 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 195856 kb
Host smart-0ee2f63c-95e9-4b55-ae17-5f71b2ce8b8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782942617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3782942617
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.214691530
Short name T443
Test name
Test status
Simulation time 41085707913 ps
CPU time 148.21 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:33:57 PM PDT 24
Peak memory 198244 kb
Host smart-464e53f6-69bb-4423-90eb-3dabe0ded2f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214691530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.214691530
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4154033537
Short name T151
Test name
Test status
Simulation time 13777993 ps
CPU time 0.56 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 194060 kb
Host smart-3fe55f7b-143f-400a-9531-56e4ea273df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154033537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4154033537
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.961980381
Short name T592
Test name
Test status
Simulation time 56018345 ps
CPU time 1 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 195724 kb
Host smart-33538632-246c-446a-a708-fc91707608a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961980381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.961980381
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1205062832
Short name T210
Test name
Test status
Simulation time 394601526 ps
CPU time 10.83 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:34 PM PDT 24
Peak memory 195528 kb
Host smart-786aba01-7ffb-49a9-8b43-9a5d8fdcd6a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205062832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1205062832
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3468791573
Short name T482
Test name
Test status
Simulation time 53252040 ps
CPU time 0.93 seconds
Started Apr 23 12:31:21 PM PDT 24
Finished Apr 23 12:31:23 PM PDT 24
Peak memory 196716 kb
Host smart-5bb84747-bd05-444c-a38a-094da0f88633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468791573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3468791573
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2949786695
Short name T475
Test name
Test status
Simulation time 25689904 ps
CPU time 0.88 seconds
Started Apr 23 12:31:24 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 196728 kb
Host smart-c0da512b-857e-41ae-9619-8ac1b48b9602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949786695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2949786695
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1063483794
Short name T682
Test name
Test status
Simulation time 260072135 ps
CPU time 2.56 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:50 PM PDT 24
Peak memory 197996 kb
Host smart-3167530d-794c-4f9e-a8a1-aa8b72b66210
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063483794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1063483794
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1864102329
Short name T136
Test name
Test status
Simulation time 363251451 ps
CPU time 2.04 seconds
Started Apr 23 12:31:35 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 197008 kb
Host smart-8f24c1e7-f57b-4b9b-88b5-b3b64d03d65f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864102329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1864102329
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2490464593
Short name T497
Test name
Test status
Simulation time 38353266 ps
CPU time 1.27 seconds
Started Apr 23 12:31:23 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 195760 kb
Host smart-0407e70d-4460-453d-a3ed-d0663110fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490464593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2490464593
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1148090325
Short name T607
Test name
Test status
Simulation time 62241571 ps
CPU time 1.25 seconds
Started Apr 23 12:31:25 PM PDT 24
Finished Apr 23 12:31:27 PM PDT 24
Peak memory 196976 kb
Host smart-66b852e1-a803-4e45-ae19-b6729e1cd65a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148090325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1148090325
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4024313478
Short name T529
Test name
Test status
Simulation time 149302384 ps
CPU time 3.36 seconds
Started Apr 23 12:31:34 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 197812 kb
Host smart-d78f83c9-ea47-4269-8260-05b1649c31ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024313478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4024313478
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3084496373
Short name T651
Test name
Test status
Simulation time 230045166 ps
CPU time 1.45 seconds
Started Apr 23 12:31:29 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 196848 kb
Host smart-b2d2f803-07a8-40ed-a91e-78767998ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084496373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3084496373
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1904536117
Short name T699
Test name
Test status
Simulation time 165757838 ps
CPU time 1 seconds
Started Apr 23 12:31:22 PM PDT 24
Finished Apr 23 12:31:24 PM PDT 24
Peak memory 195788 kb
Host smart-4f999685-aa1d-4318-b09c-9dd12b6714b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904536117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1904536117
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4264771160
Short name T646
Test name
Test status
Simulation time 4852996308 ps
CPU time 31.08 seconds
Started Apr 23 12:31:29 PM PDT 24
Finished Apr 23 12:32:00 PM PDT 24
Peak memory 198136 kb
Host smart-b9220cf4-69ae-4335-b082-f022d4bea0d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264771160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4264771160
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.24216099
Short name T35
Test name
Test status
Simulation time 12738218 ps
CPU time 0.6 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:30 PM PDT 24
Peak memory 193884 kb
Host smart-8745e2d1-8eff-4267-9d64-eb3738b0e10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.24216099
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.922103891
Short name T267
Test name
Test status
Simulation time 58818753 ps
CPU time 0.77 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 195148 kb
Host smart-eed90948-79ee-475b-a639-c0cd5bbf1689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922103891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.922103891
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3183613530
Short name T247
Test name
Test status
Simulation time 2855252848 ps
CPU time 17.59 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:32:05 PM PDT 24
Peak memory 196592 kb
Host smart-656b3237-1def-4ab5-afe2-3fb0ca079805
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183613530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3183613530
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1677025982
Short name T609
Test name
Test status
Simulation time 28142928 ps
CPU time 0.78 seconds
Started Apr 23 12:31:43 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 196132 kb
Host smart-dd225145-d7c0-4bb5-a66c-882322a636eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677025982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1677025982
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3977245053
Short name T708
Test name
Test status
Simulation time 42256793 ps
CPU time 1.2 seconds
Started Apr 23 12:31:45 PM PDT 24
Finished Apr 23 12:31:47 PM PDT 24
Peak memory 196904 kb
Host smart-034edba3-89f9-4747-a999-faf7863a728f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977245053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3977245053
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4193934050
Short name T672
Test name
Test status
Simulation time 163308604 ps
CPU time 1.65 seconds
Started Apr 23 12:31:29 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 196756 kb
Host smart-6cced80b-ba92-4166-9589-dc70b9022491
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193934050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4193934050
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2958652213
Short name T701
Test name
Test status
Simulation time 65429653 ps
CPU time 1.09 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 195752 kb
Host smart-d59b6022-eacc-44bb-ac3d-fe87d11f1562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958652213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2958652213
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1474528663
Short name T332
Test name
Test status
Simulation time 720893274 ps
CPU time 1.28 seconds
Started Apr 23 12:31:37 PM PDT 24
Finished Apr 23 12:31:39 PM PDT 24
Peak memory 198132 kb
Host smart-c9ad898d-4443-48ee-90cf-0b75be9dabf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474528663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1474528663
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2088198605
Short name T308
Test name
Test status
Simulation time 21787714 ps
CPU time 0.87 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:29 PM PDT 24
Peak memory 196060 kb
Host smart-50324563-dbc8-48ba-b003-2964b6f95292
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088198605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2088198605
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2164837664
Short name T307
Test name
Test status
Simulation time 418199808 ps
CPU time 5.07 seconds
Started Apr 23 12:31:30 PM PDT 24
Finished Apr 23 12:31:36 PM PDT 24
Peak memory 197932 kb
Host smart-ba98bc82-cb4c-4bf5-bb67-1852d262d12c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164837664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2164837664
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1043484165
Short name T656
Test name
Test status
Simulation time 55686196 ps
CPU time 1.12 seconds
Started Apr 23 12:31:29 PM PDT 24
Finished Apr 23 12:31:31 PM PDT 24
Peak memory 195804 kb
Host smart-2a17225d-c432-4ff9-8158-7493409e49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043484165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1043484165
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2370278061
Short name T434
Test name
Test status
Simulation time 474545891 ps
CPU time 1.1 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 195764 kb
Host smart-347638ac-3ff1-4859-bf7d-fbf5fb756bc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370278061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2370278061
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3871076462
Short name T409
Test name
Test status
Simulation time 25911001102 ps
CPU time 177.93 seconds
Started Apr 23 12:31:39 PM PDT 24
Finished Apr 23 12:34:38 PM PDT 24
Peak memory 198248 kb
Host smart-048a642b-0bf0-4931-ad42-1a973bda877e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871076462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3871076462
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.275263790
Short name T81
Test name
Test status
Simulation time 272000905237 ps
CPU time 1240.36 seconds
Started Apr 23 12:31:26 PM PDT 24
Finished Apr 23 12:52:07 PM PDT 24
Peak memory 198176 kb
Host smart-29b46a8e-3c72-45f8-8603-4eb8216d66b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=275263790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.275263790
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3995293348
Short name T575
Test name
Test status
Simulation time 70604140 ps
CPU time 0.62 seconds
Started Apr 23 12:31:31 PM PDT 24
Finished Apr 23 12:31:32 PM PDT 24
Peak memory 194584 kb
Host smart-830e29c3-71a1-473a-b1bd-40d0f2d06060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995293348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3995293348
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4289389878
Short name T654
Test name
Test status
Simulation time 103021381 ps
CPU time 0.91 seconds
Started Apr 23 12:31:39 PM PDT 24
Finished Apr 23 12:31:41 PM PDT 24
Peak memory 195904 kb
Host smart-4d9456c3-dab4-4f9c-984b-f1efafdff890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289389878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4289389878
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1031925901
Short name T451
Test name
Test status
Simulation time 1160463933 ps
CPU time 12.96 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:42 PM PDT 24
Peak memory 197996 kb
Host smart-69373b23-505c-400d-aa4b-29a5dcb15b49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031925901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1031925901
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2310876919
Short name T48
Test name
Test status
Simulation time 26654035 ps
CPU time 0.62 seconds
Started Apr 23 12:31:29 PM PDT 24
Finished Apr 23 12:31:30 PM PDT 24
Peak memory 195160 kb
Host smart-3f3ac53b-2522-46db-aaf2-092a71a3ba6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310876919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2310876919
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3787898819
Short name T289
Test name
Test status
Simulation time 151351311 ps
CPU time 1.13 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:49 PM PDT 24
Peak memory 195864 kb
Host smart-71a50b75-0bf3-4227-b051-313aa723b947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787898819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3787898819
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2508555701
Short name T233
Test name
Test status
Simulation time 65072924 ps
CPU time 1.4 seconds
Started Apr 23 12:31:45 PM PDT 24
Finished Apr 23 12:31:47 PM PDT 24
Peak memory 197912 kb
Host smart-d846eb63-e3a7-4581-9480-604d9ef6dd5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508555701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2508555701
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3465123636
Short name T377
Test name
Test status
Simulation time 93183615 ps
CPU time 2.84 seconds
Started Apr 23 12:31:28 PM PDT 24
Finished Apr 23 12:31:32 PM PDT 24
Peak memory 198064 kb
Host smart-fc3f14bc-c03e-4117-98f4-b491f42e781e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465123636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3465123636
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2129574700
Short name T508
Test name
Test status
Simulation time 82214423 ps
CPU time 0.76 seconds
Started Apr 23 12:31:36 PM PDT 24
Finished Apr 23 12:31:37 PM PDT 24
Peak memory 195344 kb
Host smart-722fb724-ca26-4480-ad5f-110346985843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129574700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2129574700
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.879854652
Short name T382
Test name
Test status
Simulation time 56289688 ps
CPU time 1.24 seconds
Started Apr 23 12:31:36 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 198004 kb
Host smart-97ce3d52-b021-459b-8a70-35fb0dd6324b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879854652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.879854652
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.419981290
Short name T322
Test name
Test status
Simulation time 348970848 ps
CPU time 1.81 seconds
Started Apr 23 12:31:45 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 197964 kb
Host smart-5e09bac3-c091-49f9-84f7-7a0e73392a75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419981290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.419981290
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2289440066
Short name T562
Test name
Test status
Simulation time 30153657 ps
CPU time 1 seconds
Started Apr 23 12:31:36 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 196440 kb
Host smart-ffd4c697-6a8a-444f-9562-c8fa6d77dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289440066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2289440066
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.108024093
Short name T693
Test name
Test status
Simulation time 51697181 ps
CPU time 1.03 seconds
Started Apr 23 12:31:26 PM PDT 24
Finished Apr 23 12:31:28 PM PDT 24
Peak memory 195484 kb
Host smart-f668250a-d42f-4aab-b5ad-94c3e1f4bba8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108024093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.108024093
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2601762334
Short name T6
Test name
Test status
Simulation time 16407862272 ps
CPU time 84.54 seconds
Started Apr 23 12:31:34 PM PDT 24
Finished Apr 23 12:33:00 PM PDT 24
Peak memory 198140 kb
Host smart-3a74ec92-2292-41d3-982f-2951545eb774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601762334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2601762334
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1842548605
Short name T395
Test name
Test status
Simulation time 13464011 ps
CPU time 0.62 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 194032 kb
Host smart-2f04cd32-d09a-41c8-bc9a-71a94060a546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842548605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1842548605
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3873300079
Short name T50
Test name
Test status
Simulation time 35417304 ps
CPU time 0.81 seconds
Started Apr 23 12:31:32 PM PDT 24
Finished Apr 23 12:31:34 PM PDT 24
Peak memory 195232 kb
Host smart-6f8ccf7e-5def-4f4e-9eba-5e7fc09abc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873300079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3873300079
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4213328029
Short name T700
Test name
Test status
Simulation time 3506917401 ps
CPU time 26.25 seconds
Started Apr 23 12:31:38 PM PDT 24
Finished Apr 23 12:32:05 PM PDT 24
Peak memory 198000 kb
Host smart-4426fff5-1e29-4747-88b9-6d3e195426e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213328029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4213328029
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1342812526
Short name T564
Test name
Test status
Simulation time 346343565 ps
CPU time 0.96 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 196516 kb
Host smart-773334e5-4335-4ec1-a141-1e22c4b5ea15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342812526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1342812526
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1448752627
Short name T140
Test name
Test status
Simulation time 106118924 ps
CPU time 1.47 seconds
Started Apr 23 12:31:31 PM PDT 24
Finished Apr 23 12:31:33 PM PDT 24
Peak memory 196572 kb
Host smart-3c22909e-5ee2-43d8-8c7e-27c84844ead9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448752627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1448752627
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.606458826
Short name T477
Test name
Test status
Simulation time 227165687 ps
CPU time 2.48 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 198196 kb
Host smart-254748dd-1fc2-4f26-8ae5-d39cdfab95d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606458826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.606458826
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3872435195
Short name T631
Test name
Test status
Simulation time 50439863 ps
CPU time 0.99 seconds
Started Apr 23 12:31:37 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 196460 kb
Host smart-ce45e16c-44c4-49e6-816d-8579ea47e54a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872435195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3872435195
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4266093407
Short name T636
Test name
Test status
Simulation time 45140572 ps
CPU time 1.08 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 195876 kb
Host smart-c06a2acd-6ef5-4a34-835c-916921b84c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266093407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4266093407
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4114152671
Short name T647
Test name
Test status
Simulation time 86627396 ps
CPU time 0.68 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 194176 kb
Host smart-04ac619e-8e18-4517-a172-2d9cfe826681
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114152671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4114152671
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2086908108
Short name T179
Test name
Test status
Simulation time 112970502 ps
CPU time 5.11 seconds
Started Apr 23 12:31:32 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 197992 kb
Host smart-c8130a59-afcd-4d09-81c1-2e081f83ecd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086908108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2086908108
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.535300192
Short name T388
Test name
Test status
Simulation time 104963613 ps
CPU time 0.95 seconds
Started Apr 23 12:31:34 PM PDT 24
Finished Apr 23 12:31:35 PM PDT 24
Peak memory 196456 kb
Host smart-cb481bfb-1963-415d-a33f-8200aa8062ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535300192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.535300192
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1661981789
Short name T523
Test name
Test status
Simulation time 43213538 ps
CPU time 1.15 seconds
Started Apr 23 12:31:32 PM PDT 24
Finished Apr 23 12:31:34 PM PDT 24
Peak memory 196572 kb
Host smart-a0e023da-a91f-490b-9ba5-a7e587d7e7c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661981789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1661981789
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1330858038
Short name T78
Test name
Test status
Simulation time 7717614031 ps
CPU time 25.86 seconds
Started Apr 23 12:32:47 PM PDT 24
Finished Apr 23 12:33:14 PM PDT 24
Peak memory 197968 kb
Host smart-a170e2bb-4931-4479-8efa-1ba6c63805cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330858038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1330858038
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3050958934
Short name T121
Test name
Test status
Simulation time 90026608 ps
CPU time 0.59 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 194660 kb
Host smart-29b315eb-67de-493f-81db-b447f78e8132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050958934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3050958934
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3755183941
Short name T242
Test name
Test status
Simulation time 21049284 ps
CPU time 0.71 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 194224 kb
Host smart-76096ab0-1504-432c-a4c4-d4c64c6b399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755183941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3755183941
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.322700584
Short name T448
Test name
Test status
Simulation time 505251743 ps
CPU time 8.82 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 198012 kb
Host smart-2a65296d-e213-4304-a302-f46d618bae24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322700584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.322700584
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.718019803
Short name T265
Test name
Test status
Simulation time 313268999 ps
CPU time 1.03 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196680 kb
Host smart-54ed7e8b-f02f-44cb-a83c-cc4402aa86d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718019803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.718019803
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3189057039
Short name T286
Test name
Test status
Simulation time 281220090 ps
CPU time 1.03 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 195852 kb
Host smart-c13958ee-0076-42c3-aab3-39f975d19b54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189057039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3189057039
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1787663942
Short name T278
Test name
Test status
Simulation time 35327473 ps
CPU time 1.44 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 198008 kb
Host smart-418c60c0-e87c-4d0e-8c2c-f8dc783cc81a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787663942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1787663942
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1863433786
Short name T447
Test name
Test status
Simulation time 51666936 ps
CPU time 1.66 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 195908 kb
Host smart-33f857c8-7185-4343-b69a-2fcc8fdbdc0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863433786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1863433786
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2771862190
Short name T675
Test name
Test status
Simulation time 178417186 ps
CPU time 1.17 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 196088 kb
Host smart-8c9e7b43-0c36-4384-a6b6-8243e9759a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771862190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2771862190
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1197152615
Short name T241
Test name
Test status
Simulation time 52460609 ps
CPU time 0.69 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 195584 kb
Host smart-08bb8ecc-65f7-46cd-850f-14c56b46d384
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197152615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1197152615
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.133789013
Short name T230
Test name
Test status
Simulation time 178608107 ps
CPU time 2.44 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:22 PM PDT 24
Peak memory 198072 kb
Host smart-52e297b0-d3d0-44f1-8c53-766a56b98f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133789013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.133789013
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3347987895
Short name T32
Test name
Test status
Simulation time 202617998 ps
CPU time 0.79 seconds
Started Apr 23 12:30:15 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 213484 kb
Host smart-01366f53-c158-4938-af15-133ef32044eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347987895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3347987895
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2888019064
Short name T428
Test name
Test status
Simulation time 38195392 ps
CPU time 1.08 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 196404 kb
Host smart-998e7c2a-3f76-4f53-81bc-e628a69896a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888019064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2888019064
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3918409460
Short name T709
Test name
Test status
Simulation time 344561329 ps
CPU time 1.43 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196836 kb
Host smart-7c8bad21-f48f-42bf-b82d-057c8347bd65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918409460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3918409460
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1269734338
Short name T599
Test name
Test status
Simulation time 13142560623 ps
CPU time 115.76 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:32:15 PM PDT 24
Peak memory 198136 kb
Host smart-f38307c5-05be-4a67-b8cc-fa0ab96f2037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269734338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1269734338
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1251733308
Short name T591
Test name
Test status
Simulation time 304427845089 ps
CPU time 3404.81 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 01:27:02 PM PDT 24
Peak memory 198208 kb
Host smart-c7a2583e-7db7-4eb7-91d9-c2567b59ac6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1251733308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1251733308
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2263798256
Short name T170
Test name
Test status
Simulation time 14747824 ps
CPU time 0.59 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 194608 kb
Host smart-26bf59c3-7c7a-48ea-8293-fa683c43d98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263798256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2263798256
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3911395755
Short name T664
Test name
Test status
Simulation time 18891300 ps
CPU time 0.68 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 194144 kb
Host smart-2389f3ff-d391-49a7-957d-6cdfa3f850b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911395755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3911395755
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2420033617
Short name T471
Test name
Test status
Simulation time 1344671480 ps
CPU time 11.66 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:57 PM PDT 24
Peak memory 195480 kb
Host smart-07adbb37-a794-46a2-9df5-4204edf2d6cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420033617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2420033617
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3125547013
Short name T237
Test name
Test status
Simulation time 79356663 ps
CPU time 0.78 seconds
Started Apr 23 12:31:34 PM PDT 24
Finished Apr 23 12:31:35 PM PDT 24
Peak memory 196532 kb
Host smart-4ae6cf21-0c9e-4d9f-a9f1-4f0b9221cc40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125547013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3125547013
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.699747948
Short name T240
Test name
Test status
Simulation time 191416741 ps
CPU time 1.36 seconds
Started Apr 23 12:31:32 PM PDT 24
Finished Apr 23 12:31:34 PM PDT 24
Peak memory 197372 kb
Host smart-fb2bc14f-d5d2-4556-afbd-5190d5442d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699747948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.699747948
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3850381438
Short name T351
Test name
Test status
Simulation time 139430739 ps
CPU time 1.48 seconds
Started Apr 23 12:31:33 PM PDT 24
Finished Apr 23 12:31:35 PM PDT 24
Peak memory 196464 kb
Host smart-62e6c51a-be19-4d99-885e-a126871acff0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850381438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3850381438
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2568957325
Short name T478
Test name
Test status
Simulation time 107578966 ps
CPU time 1.32 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 196876 kb
Host smart-17b152ef-de0e-483e-aecf-2291e2240ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568957325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2568957325
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1553843806
Short name T406
Test name
Test status
Simulation time 20513491 ps
CPU time 0.8 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 195480 kb
Host smart-0cbd8659-b50f-4b48-b3bf-5e2cc9bbcaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553843806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1553843806
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2545228188
Short name T570
Test name
Test status
Simulation time 55975818 ps
CPU time 1.15 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 197004 kb
Host smart-602df1a4-0c30-4403-9265-c1d5de7c0dab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545228188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2545228188
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1353401370
Short name T9
Test name
Test status
Simulation time 239395218 ps
CPU time 3.16 seconds
Started Apr 23 12:31:33 PM PDT 24
Finished Apr 23 12:31:36 PM PDT 24
Peak memory 197912 kb
Host smart-8bb9b1b7-967e-4ba9-8363-c0c99fe5ecbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353401370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1353401370
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1280749651
Short name T175
Test name
Test status
Simulation time 465784720 ps
CPU time 1.2 seconds
Started Apr 23 12:31:33 PM PDT 24
Finished Apr 23 12:31:35 PM PDT 24
Peak memory 195520 kb
Host smart-e919a36e-f60e-417e-848b-637e2dc3156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280749651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1280749651
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.103392226
Short name T569
Test name
Test status
Simulation time 75400460 ps
CPU time 0.79 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:43 PM PDT 24
Peak memory 195176 kb
Host smart-ca3cce00-7759-443a-8bdd-e85d553bbd2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103392226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.103392226
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1951192407
Short name T498
Test name
Test status
Simulation time 24002649483 ps
CPU time 178.06 seconds
Started Apr 23 12:31:33 PM PDT 24
Finished Apr 23 12:34:32 PM PDT 24
Peak memory 198104 kb
Host smart-739239bc-cb6a-4bc5-9f73-b908ecef00af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951192407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1951192407
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.256536348
Short name T68
Test name
Test status
Simulation time 13275386 ps
CPU time 0.59 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:49 PM PDT 24
Peak memory 193868 kb
Host smart-e9b9c14f-2d42-45bc-9fa8-01fc2fcccf6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256536348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.256536348
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3097228619
Short name T586
Test name
Test status
Simulation time 534368451 ps
CPU time 0.88 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 195404 kb
Host smart-eb3f3165-bf24-49b7-acab-eb7029b5bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097228619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3097228619
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4104354262
Short name T637
Test name
Test status
Simulation time 562744555 ps
CPU time 16.3 seconds
Started Apr 23 12:31:37 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 196808 kb
Host smart-6847175b-1273-42f6-a2c4-ddd47faf46e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104354262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4104354262
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1715664648
Short name T685
Test name
Test status
Simulation time 90184748 ps
CPU time 1.08 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 197860 kb
Host smart-d4b218a0-ddfc-40f6-994c-598b813418b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715664648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1715664648
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1568671092
Short name T53
Test name
Test status
Simulation time 44582451 ps
CPU time 0.76 seconds
Started Apr 23 12:31:37 PM PDT 24
Finished Apr 23 12:31:39 PM PDT 24
Peak memory 195568 kb
Host smart-d32394ba-fd8e-45e4-b4d1-877a1c01396d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568671092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1568671092
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.45051192
Short name T553
Test name
Test status
Simulation time 300431777 ps
CPU time 3.16 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:59 PM PDT 24
Peak memory 198148 kb
Host smart-b3cb11c8-f873-4753-80d9-1b9a5c57d1f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45051192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.gpio_intr_with_filter_rand_intr_event.45051192
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2786704741
Short name T398
Test name
Test status
Simulation time 2403720184 ps
CPU time 3.53 seconds
Started Apr 23 12:31:48 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 197228 kb
Host smart-f40b5b4d-9d22-49a2-83d3-434b58ffcccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786704741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2786704741
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2580437942
Short name T702
Test name
Test status
Simulation time 400992081 ps
CPU time 1.07 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 195980 kb
Host smart-e65dd9a5-56fc-485b-9eeb-dfc856655f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580437942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2580437942
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2494387847
Short name T414
Test name
Test status
Simulation time 43538614 ps
CPU time 1.08 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 196752 kb
Host smart-10248fee-4b2f-4fa3-affd-911439566b63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494387847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2494387847
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3551509261
Short name T3
Test name
Test status
Simulation time 701556018 ps
CPU time 4.29 seconds
Started Apr 23 12:31:45 PM PDT 24
Finished Apr 23 12:31:50 PM PDT 24
Peak memory 197972 kb
Host smart-a47c39b0-55ca-4274-a7a9-8a8cac6608ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551509261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3551509261
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1262831192
Short name T328
Test name
Test status
Simulation time 62232077 ps
CPU time 1.19 seconds
Started Apr 23 12:32:39 PM PDT 24
Finished Apr 23 12:32:43 PM PDT 24
Peak memory 195324 kb
Host smart-471b71a1-f9d4-476c-8f59-517ad38f5f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262831192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1262831192
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1593430497
Short name T531
Test name
Test status
Simulation time 151644004 ps
CPU time 1.15 seconds
Started Apr 23 12:31:36 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 195504 kb
Host smart-05ca4aac-a850-4bbd-970e-8b701238477e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593430497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1593430497
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.46612088
Short name T670
Test name
Test status
Simulation time 10332500492 ps
CPU time 158.06 seconds
Started Apr 23 12:31:40 PM PDT 24
Finished Apr 23 12:34:18 PM PDT 24
Peak memory 198096 kb
Host smart-87c3d5ad-8e5a-4df7-83cf-030271eee274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46612088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gp
io_stress_all.46612088
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3707179040
Short name T62
Test name
Test status
Simulation time 54897291717 ps
CPU time 558.27 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:41:09 PM PDT 24
Peak memory 198152 kb
Host smart-a80dbe62-9743-44cb-a849-86408796c03c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3707179040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3707179040
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2034393773
Short name T324
Test name
Test status
Simulation time 12528127 ps
CPU time 0.59 seconds
Started Apr 23 12:31:45 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 193880 kb
Host smart-eb1c9e51-442e-4014-906f-cfe2327abf8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034393773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2034393773
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.593174138
Short name T41
Test name
Test status
Simulation time 19190987 ps
CPU time 0.63 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 194600 kb
Host smart-489df4be-7080-4558-9250-1316fcf1bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593174138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.593174138
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3958982591
Short name T635
Test name
Test status
Simulation time 285220264 ps
CPU time 9.91 seconds
Started Apr 23 12:31:37 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 197952 kb
Host smart-744ec947-641b-42b4-bff6-5f6dba354c7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958982591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3958982591
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3719151857
Short name T5
Test name
Test status
Simulation time 407404689 ps
CPU time 1.04 seconds
Started Apr 23 12:31:35 PM PDT 24
Finished Apr 23 12:31:37 PM PDT 24
Peak memory 196404 kb
Host smart-59938f4c-b53c-4618-9403-e037d6f9066f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719151857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3719151857
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2675611910
Short name T500
Test name
Test status
Simulation time 86390685 ps
CPU time 1.15 seconds
Started Apr 23 12:31:43 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 196024 kb
Host smart-74aeb0dc-f93d-4c40-b324-65ccec9e0d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675611910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2675611910
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2804162892
Short name T173
Test name
Test status
Simulation time 144337453 ps
CPU time 1.64 seconds
Started Apr 23 12:31:35 PM PDT 24
Finished Apr 23 12:31:37 PM PDT 24
Peak memory 196320 kb
Host smart-c2ea3507-1d75-4bb4-bf55-57ac25c5e225
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804162892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2804162892
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3921908082
Short name T615
Test name
Test status
Simulation time 468310303 ps
CPU time 3.79 seconds
Started Apr 23 12:31:35 PM PDT 24
Finished Apr 23 12:31:40 PM PDT 24
Peak memory 197204 kb
Host smart-b52262c8-d9d8-4b45-954e-1d4796d55fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921908082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3921908082
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3615990203
Short name T665
Test name
Test status
Simulation time 46475253 ps
CPU time 1.06 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 196092 kb
Host smart-350a1318-3d6a-4289-9679-45d23b6e827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615990203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3615990203
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2545914378
Short name T197
Test name
Test status
Simulation time 109105879 ps
CPU time 1.29 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 197064 kb
Host smart-c6c0ca39-5f48-4b34-9fb4-6146a1f8f5e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545914378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2545914378
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.283677183
Short name T236
Test name
Test status
Simulation time 1377320238 ps
CPU time 5.46 seconds
Started Apr 23 12:31:39 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 198052 kb
Host smart-2915f5b7-7255-4778-ad60-25b9bdca9eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283677183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.283677183
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.974373908
Short name T374
Test name
Test status
Simulation time 173766422 ps
CPU time 1.44 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 196992 kb
Host smart-2f96f90c-0cc2-4b5f-89ab-7bcbb3f839a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974373908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.974373908
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2579334908
Short name T354
Test name
Test status
Simulation time 221374776 ps
CPU time 1.17 seconds
Started Apr 23 12:31:34 PM PDT 24
Finished Apr 23 12:31:36 PM PDT 24
Peak memory 195820 kb
Host smart-363cba21-a8ec-48f7-9824-2aaeaa3b7368
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579334908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2579334908
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2304411933
Short name T345
Test name
Test status
Simulation time 30882139562 ps
CPU time 123.5 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:33:51 PM PDT 24
Peak memory 198040 kb
Host smart-f3306d76-23ae-4ca3-bdca-e696b947e731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304411933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2304411933
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1460356867
Short name T530
Test name
Test status
Simulation time 47796057 ps
CPU time 0.57 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 193832 kb
Host smart-cef2ecf1-9371-448d-863b-02a51bc40674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460356867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1460356867
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3473571564
Short name T521
Test name
Test status
Simulation time 56966562 ps
CPU time 0.87 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 197060 kb
Host smart-946dc569-cd0a-4eb9-98ef-cd6163fbe44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473571564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3473571564
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.855059568
Short name T549
Test name
Test status
Simulation time 503994923 ps
CPU time 15.93 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:32:12 PM PDT 24
Peak memory 198192 kb
Host smart-16b7b88b-db25-4aa2-91ea-41c9a34606ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855059568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.855059568
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3421672660
Short name T669
Test name
Test status
Simulation time 200177119 ps
CPU time 0.94 seconds
Started Apr 23 12:31:54 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 197156 kb
Host smart-1b2df015-ec86-41dd-bdd4-37c3fa0470c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421672660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3421672660
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3650295568
Short name T674
Test name
Test status
Simulation time 90528406 ps
CPU time 1.27 seconds
Started Apr 23 12:31:41 PM PDT 24
Finished Apr 23 12:31:42 PM PDT 24
Peak memory 195772 kb
Host smart-1b0cc5bc-2535-4dd3-b6dd-41abfec55351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650295568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3650295568
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1701808064
Short name T533
Test name
Test status
Simulation time 251010906 ps
CPU time 2.25 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 196404 kb
Host smart-4be252fd-5b03-4add-8a3e-83a680ed03d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701808064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1701808064
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2041400361
Short name T465
Test name
Test status
Simulation time 142867276 ps
CPU time 1.32 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 195820 kb
Host smart-c7cb3420-6d48-486b-9614-1956eda48c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041400361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2041400361
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2917973237
Short name T123
Test name
Test status
Simulation time 37185276 ps
CPU time 1.29 seconds
Started Apr 23 12:31:40 PM PDT 24
Finished Apr 23 12:31:42 PM PDT 24
Peak memory 195932 kb
Host smart-cc9e0a75-e47a-4d4e-8f7d-cb82bf8cf8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917973237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2917973237
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1504941683
Short name T579
Test name
Test status
Simulation time 72371055 ps
CPU time 1.31 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 196996 kb
Host smart-db4ab446-9aa8-44c1-b0f4-1818b2ec647c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504941683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1504941683
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3676416722
Short name T612
Test name
Test status
Simulation time 340981489 ps
CPU time 3.93 seconds
Started Apr 23 12:31:56 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 197924 kb
Host smart-e201c69d-bd6a-4eb1-a195-2246302fa58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676416722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3676416722
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.243109551
Short name T285
Test name
Test status
Simulation time 54856266 ps
CPU time 0.92 seconds
Started Apr 23 12:31:41 PM PDT 24
Finished Apr 23 12:31:42 PM PDT 24
Peak memory 196544 kb
Host smart-d2e5f730-fdb4-4480-807f-8409af6b13f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243109551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.243109551
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2519986906
Short name T313
Test name
Test status
Simulation time 83301423 ps
CPU time 1.24 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 196456 kb
Host smart-2bb2f5e0-412d-4c2c-8696-39df0c52b916
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519986906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2519986906
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3651099578
Short name T381
Test name
Test status
Simulation time 14065419009 ps
CPU time 87.6 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:33:20 PM PDT 24
Peak memory 198224 kb
Host smart-3b261508-8adc-4f40-b00a-da52d44a65e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651099578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3651099578
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.347094775
Short name T655
Test name
Test status
Simulation time 146028957 ps
CPU time 0.6 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 194816 kb
Host smart-57cc5501-3c42-457f-9ca5-fd5313a6f07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347094775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.347094775
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2114688411
Short name T317
Test name
Test status
Simulation time 17086301 ps
CPU time 0.62 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 193948 kb
Host smart-b55f73c3-f323-4ac8-a8d5-e76b82c92ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114688411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2114688411
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3315648621
Short name T336
Test name
Test status
Simulation time 874592390 ps
CPU time 28.2 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:32:17 PM PDT 24
Peak memory 196732 kb
Host smart-48ad2212-d2ae-4523-bff0-f07c9b45c391
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315648621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3315648621
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3551622117
Short name T441
Test name
Test status
Simulation time 148139062 ps
CPU time 0.74 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 194688 kb
Host smart-1c37152f-30a3-4d31-96be-9dad9f2e2829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551622117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3551622117
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3488768864
Short name T400
Test name
Test status
Simulation time 53036579 ps
CPU time 0.64 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 194300 kb
Host smart-697b21bb-52b8-4815-b8db-95af0893a700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488768864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3488768864
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1185592181
Short name T51
Test name
Test status
Simulation time 430321175 ps
CPU time 2.59 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 196424 kb
Host smart-e501a80d-f701-4531-b4ad-1cf24cb4622d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185592181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1185592181
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2142272398
Short name T493
Test name
Test status
Simulation time 163139964 ps
CPU time 1.6 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:49 PM PDT 24
Peak memory 196272 kb
Host smart-8dd793f0-38ce-4efa-a427-463eefa0a122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142272398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2142272398
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3514857776
Short name T167
Test name
Test status
Simulation time 169678882 ps
CPU time 0.69 seconds
Started Apr 23 12:31:42 PM PDT 24
Finished Apr 23 12:31:44 PM PDT 24
Peak memory 195332 kb
Host smart-4cd2771d-18e2-445e-90a8-66e7dd527cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514857776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3514857776
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.278778981
Short name T273
Test name
Test status
Simulation time 34819482 ps
CPU time 0.94 seconds
Started Apr 23 12:31:40 PM PDT 24
Finished Apr 23 12:31:42 PM PDT 24
Peak memory 195504 kb
Host smart-c6536557-a9e3-451d-ba83-da56961314ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278778981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.278778981
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2579942119
Short name T159
Test name
Test status
Simulation time 406060453 ps
CPU time 4.87 seconds
Started Apr 23 12:31:40 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 197524 kb
Host smart-8521077b-4801-4ec9-851f-0a87564853b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579942119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2579942119
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2414545333
Short name T481
Test name
Test status
Simulation time 76729011 ps
CPU time 1.24 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 196904 kb
Host smart-eb064623-0448-4c73-9815-178f70e01cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414545333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2414545333
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.102535528
Short name T64
Test name
Test status
Simulation time 201701849 ps
CPU time 1.42 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 197052 kb
Host smart-99d17d5b-3e1a-4181-880d-bdb9820613c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102535528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.102535528
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2537056623
Short name T539
Test name
Test status
Simulation time 10453153944 ps
CPU time 149.05 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:34:19 PM PDT 24
Peak memory 198096 kb
Host smart-69006efd-298d-49b3-a4bc-302aeac83ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537056623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2537056623
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.670901548
Short name T659
Test name
Test status
Simulation time 33470890 ps
CPU time 0.58 seconds
Started Apr 23 12:31:54 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 194592 kb
Host smart-c6fc6d00-dc47-4757-862f-3583465a2422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670901548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.670901548
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3610477091
Short name T476
Test name
Test status
Simulation time 27595366 ps
CPU time 0.82 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 196072 kb
Host smart-ff092be2-0c09-4145-b7f7-cdffd772bec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610477091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3610477091
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3149467516
Short name T238
Test name
Test status
Simulation time 239724874 ps
CPU time 9.7 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:32:06 PM PDT 24
Peak memory 197076 kb
Host smart-a1117643-9481-418f-be74-c60efafe54b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149467516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3149467516
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3372328931
Short name T525
Test name
Test status
Simulation time 24962584 ps
CPU time 0.69 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 195300 kb
Host smart-86831e4f-773a-4286-a69d-3cac8d7748c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372328931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3372328931
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2374094734
Short name T302
Test name
Test status
Simulation time 114221734 ps
CPU time 1.07 seconds
Started Apr 23 12:31:43 PM PDT 24
Finished Apr 23 12:31:45 PM PDT 24
Peak memory 196120 kb
Host smart-f47f712d-60d6-481e-a853-5ab7493a3cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374094734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2374094734
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.126618536
Short name T689
Test name
Test status
Simulation time 49342709 ps
CPU time 1.14 seconds
Started Apr 23 12:31:53 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 198012 kb
Host smart-774f3014-88a3-43fb-b60e-b6f3b990c682
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126618536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.126618536
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1040756581
Short name T277
Test name
Test status
Simulation time 103408238 ps
CPU time 2.27 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 198028 kb
Host smart-39de4f69-b09c-49aa-ac5c-04757622e18f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040756581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1040756581
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3618841538
Short name T355
Test name
Test status
Simulation time 128992083 ps
CPU time 1.27 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:47 PM PDT 24
Peak memory 197040 kb
Host smart-a071aa3a-ebce-4603-b3cf-0819c7faf7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618841538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3618841538
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3302053556
Short name T565
Test name
Test status
Simulation time 94219083 ps
CPU time 1.02 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 195948 kb
Host smart-b5e6da9a-415d-40c8-95b8-fa32614754fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302053556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3302053556
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.599381030
Short name T152
Test name
Test status
Simulation time 162842311 ps
CPU time 3.64 seconds
Started Apr 23 12:31:46 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 198008 kb
Host smart-c5e52a14-2fe2-4ebd-bc88-74fe884b4269
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599381030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.599381030
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1979547936
Short name T226
Test name
Test status
Simulation time 49439511 ps
CPU time 1.28 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 196044 kb
Host smart-9c4e5b3d-2d4f-4957-b071-231949f83852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979547936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1979547936
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2435289330
Short name T55
Test name
Test status
Simulation time 97561619 ps
CPU time 1.44 seconds
Started Apr 23 12:31:44 PM PDT 24
Finished Apr 23 12:31:46 PM PDT 24
Peak memory 196880 kb
Host smart-be8c917c-e64e-444a-94cd-454695bb550f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435289330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2435289330
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1129700532
Short name T686
Test name
Test status
Simulation time 32733175595 ps
CPU time 188.6 seconds
Started Apr 23 12:31:43 PM PDT 24
Finished Apr 23 12:34:52 PM PDT 24
Peak memory 198104 kb
Host smart-b2732f32-c355-4e58-a1ad-66f015b3b4db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129700532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1129700532
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1041931455
Short name T56
Test name
Test status
Simulation time 102079027776 ps
CPU time 1211.41 seconds
Started Apr 23 12:31:43 PM PDT 24
Finished Apr 23 12:51:55 PM PDT 24
Peak memory 198256 kb
Host smart-02cc8cdf-95e3-4a97-ba50-f0f217d64c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1041931455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1041931455
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2953566457
Short name T34
Test name
Test status
Simulation time 17924625 ps
CPU time 0.57 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 193880 kb
Host smart-5cd0e9eb-dbf4-45d2-b7aa-c4153b7f1e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953566457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2953566457
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1027144055
Short name T304
Test name
Test status
Simulation time 21696134 ps
CPU time 0.71 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:49 PM PDT 24
Peak memory 195868 kb
Host smart-30aa9ab3-b9c9-4963-80d7-43175127f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027144055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1027144055
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.66139068
Short name T378
Test name
Test status
Simulation time 715289388 ps
CPU time 9.88 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 196976 kb
Host smart-38b5614f-51ad-4f56-80a4-0a0cf128b8f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66139068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stress
.66139068
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3043318593
Short name T653
Test name
Test status
Simulation time 133010643 ps
CPU time 0.66 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 195352 kb
Host smart-6d724d1b-5bc4-4aa8-8565-cb0ff20c78c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043318593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3043318593
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3760918426
Short name T119
Test name
Test status
Simulation time 53276674 ps
CPU time 1.03 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 196204 kb
Host smart-12ee7604-17dc-4403-bb70-ca182bf8e3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760918426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3760918426
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.127252728
Short name T389
Test name
Test status
Simulation time 162861398 ps
CPU time 3.15 seconds
Started Apr 23 12:33:06 PM PDT 24
Finished Apr 23 12:33:09 PM PDT 24
Peak memory 197964 kb
Host smart-aabcdb98-cfe0-4419-9fed-12fbd5ce2ffd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127252728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.127252728
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4182690131
Short name T163
Test name
Test status
Simulation time 208574186 ps
CPU time 2.39 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 198084 kb
Host smart-4e818dca-4ca4-401e-9581-149185adea9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182690131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4182690131
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3830149338
Short name T208
Test name
Test status
Simulation time 209436477 ps
CPU time 1.26 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 197024 kb
Host smart-4cbf1c57-fea1-43ff-b9d1-2b1378565210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830149338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3830149338
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1432013189
Short name T284
Test name
Test status
Simulation time 85033576 ps
CPU time 0.83 seconds
Started Apr 23 12:31:49 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 196124 kb
Host smart-5d9731df-adb0-4429-8416-ce41cda84775
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432013189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1432013189
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.842645837
Short name T141
Test name
Test status
Simulation time 472929546 ps
CPU time 2.26 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:32:03 PM PDT 24
Peak memory 197988 kb
Host smart-aa9edce9-7263-48d3-a135-7f2e6fcb0b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842645837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.842645837
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1885889555
Short name T298
Test name
Test status
Simulation time 280841546 ps
CPU time 1.11 seconds
Started Apr 23 12:32:02 PM PDT 24
Finished Apr 23 12:32:05 PM PDT 24
Peak memory 195852 kb
Host smart-58cb12b4-b321-42a4-aa42-820a137da65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885889555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1885889555
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.368544678
Short name T341
Test name
Test status
Simulation time 32439141 ps
CPU time 0.86 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 195376 kb
Host smart-f5105303-816e-42de-98fc-2d20537bc342
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368544678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.368544678
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.661556438
Short name T364
Test name
Test status
Simulation time 24683151499 ps
CPU time 144.09 seconds
Started Apr 23 12:33:07 PM PDT 24
Finished Apr 23 12:35:32 PM PDT 24
Peak memory 197976 kb
Host smart-4c832ab6-126c-4515-a98b-3bed2af508a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661556438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.661556438
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3126681700
Short name T27
Test name
Test status
Simulation time 25208689515 ps
CPU time 392.47 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:38:33 PM PDT 24
Peak memory 198196 kb
Host smart-2bad45cb-9c83-41df-a8f9-f7aa1188bc3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3126681700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3126681700
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3760643779
Short name T503
Test name
Test status
Simulation time 39269504 ps
CPU time 0.55 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:57 PM PDT 24
Peak memory 193912 kb
Host smart-4c2e75b8-6f32-4732-b5c0-ab9e9b8cdd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760643779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3760643779
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1521309607
Short name T221
Test name
Test status
Simulation time 31949634 ps
CPU time 0.96 seconds
Started Apr 23 12:31:56 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 197312 kb
Host smart-d53711ad-b53c-4091-98c5-aff356f0f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521309607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1521309607
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1963994655
Short name T294
Test name
Test status
Simulation time 489621218 ps
CPU time 5.4 seconds
Started Apr 23 12:31:48 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 198108 kb
Host smart-a1514fa0-b011-4330-890c-a7b27de20701
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963994655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1963994655
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1225805255
Short name T334
Test name
Test status
Simulation time 84946440 ps
CPU time 0.78 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:57 PM PDT 24
Peak memory 195804 kb
Host smart-453c1bfb-51eb-4474-885f-8f09c95b3a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225805255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1225805255
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.728881866
Short name T295
Test name
Test status
Simulation time 113667029 ps
CPU time 1.47 seconds
Started Apr 23 12:31:47 PM PDT 24
Finished Apr 23 12:31:50 PM PDT 24
Peak memory 197032 kb
Host smart-b6ef9cb1-98e9-478f-b6e3-82474523fac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728881866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.728881866
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.534141243
Short name T303
Test name
Test status
Simulation time 95355656 ps
CPU time 1.93 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 198168 kb
Host smart-9826909b-16b8-436f-99d0-de3f2dfffd88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534141243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.534141243
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3267604116
Short name T596
Test name
Test status
Simulation time 76894717 ps
CPU time 2.31 seconds
Started Apr 23 12:31:48 PM PDT 24
Finished Apr 23 12:31:51 PM PDT 24
Peak memory 197120 kb
Host smart-ef28b899-18ac-4144-8121-4a240091e4ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267604116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3267604116
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1235085139
Short name T346
Test name
Test status
Simulation time 183485203 ps
CPU time 1.03 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 195936 kb
Host smart-4852ab32-ae1a-4330-b769-992d8b8853c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235085139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1235085139
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3339870690
Short name T318
Test name
Test status
Simulation time 38406166 ps
CPU time 0.89 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 195964 kb
Host smart-9b18c8b3-ad7e-4cb9-93c6-ec6b1bcb9b76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339870690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3339870690
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3551405745
Short name T589
Test name
Test status
Simulation time 838319912 ps
CPU time 5.17 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:32:02 PM PDT 24
Peak memory 198020 kb
Host smart-183f8da1-0f39-4e48-85d6-078c32c2225d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551405745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3551405745
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3890286724
Short name T652
Test name
Test status
Simulation time 379012391 ps
CPU time 1.39 seconds
Started Apr 23 12:33:07 PM PDT 24
Finished Apr 23 12:33:09 PM PDT 24
Peak memory 195452 kb
Host smart-12340a08-bf2f-4c5c-b241-3776d785ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890286724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3890286724
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1510418533
Short name T495
Test name
Test status
Simulation time 142378240 ps
CPU time 1 seconds
Started Apr 23 12:33:04 PM PDT 24
Finished Apr 23 12:33:06 PM PDT 24
Peak memory 195392 kb
Host smart-28f6ba77-e7a6-4df0-b3ed-a38d8a89ae9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510418533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1510418533
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3282475363
Short name T624
Test name
Test status
Simulation time 29316958229 ps
CPU time 119.93 seconds
Started Apr 23 12:33:06 PM PDT 24
Finished Apr 23 12:35:06 PM PDT 24
Peak memory 197964 kb
Host smart-90751c1b-1640-4b9a-8320-fb71e15ef66e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282475363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3282475363
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2785589890
Short name T293
Test name
Test status
Simulation time 14699853 ps
CPU time 0.57 seconds
Started Apr 23 12:32:05 PM PDT 24
Finished Apr 23 12:32:07 PM PDT 24
Peak memory 193896 kb
Host smart-c38d266f-eddc-4aa0-a48a-afe9628601dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785589890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2785589890
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1055305281
Short name T413
Test name
Test status
Simulation time 50652632 ps
CPU time 0.86 seconds
Started Apr 23 12:32:00 PM PDT 24
Finished Apr 23 12:32:02 PM PDT 24
Peak memory 196248 kb
Host smart-e1a8f0b2-0e56-4856-8668-0fc323a662fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055305281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1055305281
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1464770885
Short name T235
Test name
Test status
Simulation time 510371234 ps
CPU time 5.17 seconds
Started Apr 23 12:32:01 PM PDT 24
Finished Apr 23 12:32:08 PM PDT 24
Peak memory 197172 kb
Host smart-71f24586-ff78-4b95-93a9-db91fb5737fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464770885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1464770885
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2650795080
Short name T321
Test name
Test status
Simulation time 58690593 ps
CPU time 1.06 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 196152 kb
Host smart-cd98dd3d-7a34-4b8f-8aa0-4883cd5ba814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650795080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2650795080
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2162788736
Short name T511
Test name
Test status
Simulation time 169394130 ps
CPU time 0.75 seconds
Started Apr 23 12:31:56 PM PDT 24
Finished Apr 23 12:31:59 PM PDT 24
Peak memory 195448 kb
Host smart-7275a504-80fd-4b54-87bc-f7ae0a941a29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162788736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2162788736
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3785268335
Short name T621
Test name
Test status
Simulation time 296422022 ps
CPU time 3 seconds
Started Apr 23 12:31:56 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 196292 kb
Host smart-c81ed208-4a80-4202-abc2-64e044859b2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785268335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3785268335
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1649024542
Short name T190
Test name
Test status
Simulation time 373141382 ps
CPU time 2.63 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 197116 kb
Host smart-a2fa5a2c-c2d5-4d45-ad6f-8a4d2cc5e4ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649024542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1649024542
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1270216660
Short name T642
Test name
Test status
Simulation time 31103782 ps
CPU time 0.87 seconds
Started Apr 23 12:31:53 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 197212 kb
Host smart-af922802-b3d7-4638-8c16-a0a1c219522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270216660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1270216660
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.235779698
Short name T376
Test name
Test status
Simulation time 146950543 ps
CPU time 1.18 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 197140 kb
Host smart-7c79590d-c558-4083-b494-bbbf78636e85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235779698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.235779698
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2608874121
Short name T557
Test name
Test status
Simulation time 163979962 ps
CPU time 2.86 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 198004 kb
Host smart-7980857d-550d-4ba9-bc37-b508a4e19acb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608874121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2608874121
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1011974683
Short name T195
Test name
Test status
Simulation time 197876321 ps
CPU time 1.03 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:52 PM PDT 24
Peak memory 196488 kb
Host smart-59b703ad-4554-4fcf-9806-d22bb1f1ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011974683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1011974683
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2563540442
Short name T492
Test name
Test status
Simulation time 426911484 ps
CPU time 1.46 seconds
Started Apr 23 12:31:55 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 196272 kb
Host smart-06cb0925-8862-4760-a1c9-02e0a5efb964
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563540442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2563540442
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1105609408
Short name T485
Test name
Test status
Simulation time 21475152170 ps
CPU time 108.16 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:33:41 PM PDT 24
Peak memory 198212 kb
Host smart-4c37c42f-874f-4418-a57b-5cfb829d664d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105609408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1105609408
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2500504304
Short name T474
Test name
Test status
Simulation time 37586263 ps
CPU time 0.58 seconds
Started Apr 23 12:32:00 PM PDT 24
Finished Apr 23 12:32:03 PM PDT 24
Peak memory 194628 kb
Host smart-44dcdd77-7d4f-41ba-a843-101da35845c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500504304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2500504304
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3022523948
Short name T574
Test name
Test status
Simulation time 56238442 ps
CPU time 0.67 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 194304 kb
Host smart-b6d0f9b2-4b30-4733-a3c3-8f69eb65493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022523948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3022523948
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2840164728
Short name T677
Test name
Test status
Simulation time 500647310 ps
CPU time 6.35 seconds
Started Apr 23 12:31:56 PM PDT 24
Finished Apr 23 12:32:04 PM PDT 24
Peak memory 196760 kb
Host smart-7ad3248e-1a6f-4a11-9aa0-baacc590107f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840164728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2840164728
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2593706203
Short name T232
Test name
Test status
Simulation time 56941226 ps
CPU time 0.95 seconds
Started Apr 23 12:31:58 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 197240 kb
Host smart-0ad4c15e-67dd-4fc2-989e-e43ad49f3a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593706203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2593706203
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1010277988
Short name T401
Test name
Test status
Simulation time 313763312 ps
CPU time 1.34 seconds
Started Apr 23 12:31:50 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 197200 kb
Host smart-23c5d175-91a1-407d-94c7-42fd7676e863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010277988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1010277988
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2129241164
Short name T486
Test name
Test status
Simulation time 118006255 ps
CPU time 1.29 seconds
Started Apr 23 12:31:52 PM PDT 24
Finished Apr 23 12:31:55 PM PDT 24
Peak memory 196484 kb
Host smart-bda23ae6-374d-4e81-9c1f-de1248a9cc96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129241164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2129241164
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1947630775
Short name T297
Test name
Test status
Simulation time 135265400 ps
CPU time 2.99 seconds
Started Apr 23 12:31:54 PM PDT 24
Finished Apr 23 12:31:58 PM PDT 24
Peak memory 197260 kb
Host smart-2396e943-2b5a-45df-a2e2-ad2799719ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947630775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1947630775
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3095018234
Short name T419
Test name
Test status
Simulation time 29122423 ps
CPU time 1.08 seconds
Started Apr 23 12:31:54 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 196700 kb
Host smart-e27d13bf-0925-46d8-aa67-df0f5e4edd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095018234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3095018234
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.465581054
Short name T424
Test name
Test status
Simulation time 54666233 ps
CPU time 1.13 seconds
Started Apr 23 12:32:00 PM PDT 24
Finished Apr 23 12:32:03 PM PDT 24
Peak memory 195932 kb
Host smart-45a8d24b-62d7-4920-9c3b-3d950b6338a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465581054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.465581054
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3712362041
Short name T105
Test name
Test status
Simulation time 76815626 ps
CPU time 3.47 seconds
Started Apr 23 12:31:53 PM PDT 24
Finished Apr 23 12:31:57 PM PDT 24
Peak memory 197940 kb
Host smart-ed920852-ccd1-46a6-aef0-0b07e898ac5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712362041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3712362041
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2159968919
Short name T143
Test name
Test status
Simulation time 262785916 ps
CPU time 1.33 seconds
Started Apr 23 12:31:51 PM PDT 24
Finished Apr 23 12:31:54 PM PDT 24
Peak memory 196736 kb
Host smart-4bb4cf01-25d6-41e0-802e-08a42ce9c3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159968919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2159968919
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1951084697
Short name T466
Test name
Test status
Simulation time 141350536 ps
CPU time 1.09 seconds
Started Apr 23 12:31:54 PM PDT 24
Finished Apr 23 12:31:56 PM PDT 24
Peak memory 195720 kb
Host smart-4364fc58-9469-4c61-bd6c-1e666ae0a8c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951084697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1951084697
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.274657129
Short name T604
Test name
Test status
Simulation time 6119981717 ps
CPU time 159.93 seconds
Started Apr 23 12:31:59 PM PDT 24
Finished Apr 23 12:34:40 PM PDT 24
Peak memory 198140 kb
Host smart-f8ed4879-cead-4cc8-a41d-d4287d421a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274657129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.274657129
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.249560560
Short name T269
Test name
Test status
Simulation time 37972136 ps
CPU time 0.58 seconds
Started Apr 23 12:30:20 PM PDT 24
Finished Apr 23 12:30:21 PM PDT 24
Peak memory 193872 kb
Host smart-6d4c648c-95c4-4313-af1f-ac2dac830d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249560560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.249560560
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3383773514
Short name T200
Test name
Test status
Simulation time 62576660 ps
CPU time 0.87 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 195440 kb
Host smart-c38c2e9e-c3ee-4276-9508-d8beb530b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383773514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3383773514
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4195061943
Short name T134
Test name
Test status
Simulation time 694867165 ps
CPU time 24.79 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 196824 kb
Host smart-b2a506b2-3fc3-419f-8d80-6a562a57c682
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195061943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4195061943
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2460017023
Short name T690
Test name
Test status
Simulation time 34960654 ps
CPU time 0.73 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 194884 kb
Host smart-de9a8fa7-af45-43a5-9db5-43868c4a7508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460017023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2460017023
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.420915347
Short name T131
Test name
Test status
Simulation time 193340717 ps
CPU time 0.86 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 196516 kb
Host smart-292c2c3e-936c-463c-ae9a-533c14a72fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420915347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.420915347
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1302123266
Short name T73
Test name
Test status
Simulation time 50044422 ps
CPU time 1.99 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196464 kb
Host smart-1115a579-d23f-4f19-a6b4-7935287f05a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302123266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1302123266
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3147908904
Short name T387
Test name
Test status
Simulation time 39775841 ps
CPU time 0.99 seconds
Started Apr 23 12:30:14 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 195608 kb
Host smart-49901a14-17e6-4d43-b55d-c4173b63268c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147908904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3147908904
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1048935952
Short name T259
Test name
Test status
Simulation time 54409803 ps
CPU time 0.95 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 196556 kb
Host smart-41b1f4db-ac7e-42e0-b7eb-49679a9a5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048935952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1048935952
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1474427842
Short name T319
Test name
Test status
Simulation time 54865080 ps
CPU time 1.22 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 196012 kb
Host smart-b995c9a3-3c6e-4684-9aad-a16a95af0e07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474427842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1474427842
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3061981538
Short name T266
Test name
Test status
Simulation time 114133389 ps
CPU time 5.16 seconds
Started Apr 23 12:30:16 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 198032 kb
Host smart-a97e25ca-137b-4f99-ad70-209d190f2c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061981538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3061981538
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1330479072
Short name T362
Test name
Test status
Simulation time 38599251 ps
CPU time 1.12 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 195652 kb
Host smart-9bc0c442-1ee0-4726-8476-212b8bc3c9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330479072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1330479072
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2706293600
Short name T172
Test name
Test status
Simulation time 328248101 ps
CPU time 1.46 seconds
Started Apr 23 12:30:17 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 196212 kb
Host smart-70519a45-a2f2-484c-a3aa-6694f560940d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706293600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2706293600
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1696494610
Short name T545
Test name
Test status
Simulation time 7299081028 ps
CPU time 126.04 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:32:26 PM PDT 24
Peak memory 198132 kb
Host smart-79202c7f-7297-4be1-a88c-3f8b59584831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696494610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1696494610
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3965598853
Short name T71
Test name
Test status
Simulation time 66379822839 ps
CPU time 1821.67 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 01:00:45 PM PDT 24
Peak memory 198188 kb
Host smart-b87624b1-9d65-4fb3-b92e-add738d5a424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3965598853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3965598853
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3979346870
Short name T124
Test name
Test status
Simulation time 33917380 ps
CPU time 0.56 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:21 PM PDT 24
Peak memory 193896 kb
Host smart-a10f483f-af99-4971-99df-f4e4b76bdbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979346870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3979346870
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3089744211
Short name T202
Test name
Test status
Simulation time 38047499 ps
CPU time 0.89 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 196560 kb
Host smart-17e94ff8-9601-4a4b-a26d-085929c2c520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089744211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3089744211
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3263860175
Short name T668
Test name
Test status
Simulation time 787729185 ps
CPU time 18.32 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:39 PM PDT 24
Peak memory 195572 kb
Host smart-e60f473e-9e9e-451d-9398-de6fb7f2d229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263860175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3263860175
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.707143958
Short name T411
Test name
Test status
Simulation time 79512390 ps
CPU time 1.03 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 196660 kb
Host smart-729880ef-98bf-4c38-90a5-69b980063d8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707143958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.707143958
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1440977686
Short name T638
Test name
Test status
Simulation time 191616304 ps
CPU time 1.33 seconds
Started Apr 23 12:30:20 PM PDT 24
Finished Apr 23 12:30:22 PM PDT 24
Peak memory 197256 kb
Host smart-2ee66ff7-b9e9-4f87-a9ad-03e718d8aa0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440977686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1440977686
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3145397808
Short name T13
Test name
Test status
Simulation time 42974050 ps
CPU time 1.01 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 196368 kb
Host smart-7558a255-59fa-4507-aaf0-a546d365dbd7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145397808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3145397808
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1316864617
Short name T129
Test name
Test status
Simulation time 256378124 ps
CPU time 2.06 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 197256 kb
Host smart-e6349a13-87c0-4ed2-805a-1404eb470d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316864617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1316864617
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3253193243
Short name T320
Test name
Test status
Simulation time 33732035 ps
CPU time 1.21 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:30:25 PM PDT 24
Peak memory 197024 kb
Host smart-583c9469-afc0-415b-9abf-1ec4c1fc887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253193243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3253193243
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.550013301
Short name T166
Test name
Test status
Simulation time 98392724 ps
CPU time 1.17 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:21 PM PDT 24
Peak memory 196800 kb
Host smart-bc27198c-cd7e-4740-b608-98d811ead380
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550013301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.550013301
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.767270569
Short name T537
Test name
Test status
Simulation time 1174009324 ps
CPU time 6.74 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:27 PM PDT 24
Peak memory 197968 kb
Host smart-117c5240-f6ae-4736-a483-253c0c4ad516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767270569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.767270569
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3130406147
Short name T243
Test name
Test status
Simulation time 47420386 ps
CPU time 1.19 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 195916 kb
Host smart-70164cf3-6c9c-426d-8092-7eb43cacaaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130406147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3130406147
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3388031410
Short name T423
Test name
Test status
Simulation time 139291198 ps
CPU time 0.89 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:21 PM PDT 24
Peak memory 195760 kb
Host smart-56bc0c25-6e5d-4f66-b368-32e25b9f013c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388031410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3388031410
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3681738529
Short name T622
Test name
Test status
Simulation time 60194789496 ps
CPU time 167 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:33:09 PM PDT 24
Peak memory 198200 kb
Host smart-190ccb8d-351a-46fc-a53d-b721de582cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681738529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3681738529
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1919562906
Short name T687
Test name
Test status
Simulation time 43860803741 ps
CPU time 370.04 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:36:34 PM PDT 24
Peak memory 198396 kb
Host smart-a4dbec09-602c-4176-bd3b-966f319c9aa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1919562906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1919562906
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1715212363
Short name T618
Test name
Test status
Simulation time 38772735 ps
CPU time 0.57 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:28 PM PDT 24
Peak memory 193712 kb
Host smart-155ebdc0-b0b5-4d03-819a-7c3618f12136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715212363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1715212363
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.418139253
Short name T426
Test name
Test status
Simulation time 49040948 ps
CPU time 0.88 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:23 PM PDT 24
Peak memory 196660 kb
Host smart-258b8c6f-c7c0-4fc4-822c-bf601be81003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418139253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.418139253
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2237772833
Short name T63
Test name
Test status
Simulation time 3930924553 ps
CPU time 20.89 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:30:45 PM PDT 24
Peak memory 197492 kb
Host smart-2094105e-957e-407f-b1cc-2fd75a35cd3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237772833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2237772833
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.366758787
Short name T270
Test name
Test status
Simulation time 741355505 ps
CPU time 0.98 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:27 PM PDT 24
Peak memory 196960 kb
Host smart-c7ad12ba-5cdf-4756-b80a-146b3b925f13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366758787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.366758787
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1213853120
Short name T352
Test name
Test status
Simulation time 41551055 ps
CPU time 0.75 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 196252 kb
Host smart-45abc83e-5c9b-40a5-8fec-7d2f3310d4bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213853120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1213853120
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.840403673
Short name T326
Test name
Test status
Simulation time 56852259 ps
CPU time 2.26 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:25 PM PDT 24
Peak memory 198028 kb
Host smart-0ea7a2c8-1f61-491f-9ecc-676436e2b22f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840403673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.840403673
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1065608314
Short name T228
Test name
Test status
Simulation time 168967814 ps
CPU time 2.48 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 196988 kb
Host smart-8c0d3889-fbcf-4f0d-a2a5-3de2abbf6579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065608314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1065608314
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1841407196
Short name T252
Test name
Test status
Simulation time 165545812 ps
CPU time 0.89 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 196592 kb
Host smart-5970614c-4f68-4826-9a0a-5b336cab1b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841407196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1841407196
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2903388790
Short name T215
Test name
Test status
Simulation time 458409402 ps
CPU time 1.31 seconds
Started Apr 23 12:30:18 PM PDT 24
Finished Apr 23 12:30:20 PM PDT 24
Peak memory 198084 kb
Host smart-35292cca-9c9e-4954-a287-250de109d2ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903388790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2903388790
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2262519615
Short name T555
Test name
Test status
Simulation time 630811405 ps
CPU time 4.59 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:32 PM PDT 24
Peak memory 197976 kb
Host smart-48d4910f-9261-4574-86ab-856bc7289336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262519615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2262519615
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3156461562
Short name T290
Test name
Test status
Simulation time 256185437 ps
CPU time 1.22 seconds
Started Apr 23 12:30:19 PM PDT 24
Finished Apr 23 12:30:21 PM PDT 24
Peak memory 196240 kb
Host smart-56085ede-58bd-439a-be7a-7a1567003029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156461562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3156461562
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.29992880
Short name T262
Test name
Test status
Simulation time 120828913 ps
CPU time 0.94 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:30:25 PM PDT 24
Peak memory 196636 kb
Host smart-3fea3dcc-a7c7-463f-bf1f-08c048974328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29992880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.29992880
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.4187736708
Short name T254
Test name
Test status
Simulation time 8793714203 ps
CPU time 128.61 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:32:32 PM PDT 24
Peak memory 198156 kb
Host smart-32594e43-6e9c-4550-9294-fa22c103dc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187736708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.4187736708
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1822629342
Short name T300
Test name
Test status
Simulation time 61271693 ps
CPU time 0.57 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:27 PM PDT 24
Peak memory 194860 kb
Host smart-b4e28ec2-4980-4be4-8f3f-19346f8fe94d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822629342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1822629342
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2718177337
Short name T220
Test name
Test status
Simulation time 44097987 ps
CPU time 0.83 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:27 PM PDT 24
Peak memory 195228 kb
Host smart-3d6039bb-1ad7-4d14-9d68-d165b263fd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718177337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2718177337
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.350201104
Short name T429
Test name
Test status
Simulation time 4176397423 ps
CPU time 14.46 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:30:38 PM PDT 24
Peak memory 196656 kb
Host smart-3ebe302c-3c96-495c-aa93-e88a0df58122
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350201104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.350201104
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3222126219
Short name T127
Test name
Test status
Simulation time 73385014 ps
CPU time 1.03 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:29 PM PDT 24
Peak memory 197768 kb
Host smart-2b019294-191c-4304-b54e-c474eb409c84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222126219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3222126219
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3629037524
Short name T204
Test name
Test status
Simulation time 87607854 ps
CPU time 1.37 seconds
Started Apr 23 12:30:21 PM PDT 24
Finished Apr 23 12:30:24 PM PDT 24
Peak memory 197400 kb
Host smart-3959231c-b1b0-4f50-8514-00eb5f88ecb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629037524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3629037524
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.911004349
Short name T496
Test name
Test status
Simulation time 82315214 ps
CPU time 2.68 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 198148 kb
Host smart-0a0ad68b-be1f-4596-a1c9-306735b4cd0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911004349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.911004349
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2079783716
Short name T516
Test name
Test status
Simulation time 190920564 ps
CPU time 2.02 seconds
Started Apr 23 12:30:22 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 196276 kb
Host smart-effdb1c3-d96f-4f50-b987-a71bff16b54a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079783716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2079783716
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3113041367
Short name T366
Test name
Test status
Simulation time 212958110 ps
CPU time 1.08 seconds
Started Apr 23 12:30:24 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 196004 kb
Host smart-ce520db1-7088-46cc-bf40-012f44f07ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113041367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3113041367
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.659175346
Short name T24
Test name
Test status
Simulation time 131721710 ps
CPU time 0.81 seconds
Started Apr 23 12:30:24 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 196300 kb
Host smart-e8deed53-0427-41a2-82cd-69bd739a5ee1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659175346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.659175346
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1826143350
Short name T75
Test name
Test status
Simulation time 855497639 ps
CPU time 5.66 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 197932 kb
Host smart-aa910cf1-a490-4c03-a962-9733d796583d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826143350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1826143350
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1161642921
Short name T335
Test name
Test status
Simulation time 108194842 ps
CPU time 1.06 seconds
Started Apr 23 12:30:24 PM PDT 24
Finished Apr 23 12:30:26 PM PDT 24
Peak memory 195852 kb
Host smart-3b4a1b59-3f3f-4710-acab-66a859a267e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161642921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1161642921
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3435933765
Short name T323
Test name
Test status
Simulation time 23063349 ps
CPU time 0.71 seconds
Started Apr 23 12:30:23 PM PDT 24
Finished Apr 23 12:30:25 PM PDT 24
Peak memory 194188 kb
Host smart-cff978fe-c856-464b-b72c-27860d0c0d4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435933765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3435933765
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.510375228
Short name T177
Test name
Test status
Simulation time 17408130822 ps
CPU time 105.34 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:32:13 PM PDT 24
Peak memory 198116 kb
Host smart-b898109f-f4cc-43ff-bbff-16679b4cc7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510375228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.510375228
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1106011647
Short name T390
Test name
Test status
Simulation time 54053387 ps
CPU time 0.56 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 193836 kb
Host smart-49cf7bfa-4db7-4d73-97de-aaee6e0f1ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106011647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1106011647
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1485797142
Short name T614
Test name
Test status
Simulation time 29964448 ps
CPU time 0.86 seconds
Started Apr 23 12:30:29 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 197028 kb
Host smart-84a04a34-fda9-462b-a87a-54da49643e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485797142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1485797142
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2261369339
Short name T66
Test name
Test status
Simulation time 355992635 ps
CPU time 9.23 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 197960 kb
Host smart-8b135ae5-4d78-4c45-98bc-64a80a296541
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261369339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2261369339
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3321680883
Short name T436
Test name
Test status
Simulation time 398806902 ps
CPU time 0.62 seconds
Started Apr 23 12:30:29 PM PDT 24
Finished Apr 23 12:30:31 PM PDT 24
Peak memory 194504 kb
Host smart-bff53659-05c4-4af6-8e55-bf7eeeb124cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321680883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3321680883
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1982315562
Short name T135
Test name
Test status
Simulation time 179398194 ps
CPU time 0.83 seconds
Started Apr 23 12:30:30 PM PDT 24
Finished Apr 23 12:30:32 PM PDT 24
Peak memory 196588 kb
Host smart-36fe95cb-b7f9-422e-b05f-f49c35f92603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982315562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1982315562
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3861131863
Short name T440
Test name
Test status
Simulation time 100643488 ps
CPU time 3.48 seconds
Started Apr 23 12:30:28 PM PDT 24
Finished Apr 23 12:30:33 PM PDT 24
Peak memory 198124 kb
Host smart-eae37ffd-0010-41e8-ada6-354aee691881
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861131863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3861131863
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1368866092
Short name T538
Test name
Test status
Simulation time 81141133 ps
CPU time 1.57 seconds
Started Apr 23 12:30:27 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 196256 kb
Host smart-7d744698-81c5-4eb2-b7f8-11c71431d591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368866092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1368866092
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3877599007
Short name T692
Test name
Test status
Simulation time 50867619 ps
CPU time 1.1 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:28 PM PDT 24
Peak memory 196784 kb
Host smart-4d65c1e6-f096-4af4-ab1c-650a9ec32242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877599007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3877599007
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3077537057
Short name T333
Test name
Test status
Simulation time 49945665 ps
CPU time 0.7 seconds
Started Apr 23 12:30:34 PM PDT 24
Finished Apr 23 12:30:35 PM PDT 24
Peak memory 196200 kb
Host smart-5c54abc4-e3be-4eee-9794-08e33371d807
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077537057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3077537057
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.906006626
Short name T373
Test name
Test status
Simulation time 416630432 ps
CPU time 5.25 seconds
Started Apr 23 12:30:31 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 197776 kb
Host smart-288ed313-d21f-48ee-9ea6-de8dcd1f080e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906006626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.906006626
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1670079371
Short name T299
Test name
Test status
Simulation time 28022885 ps
CPU time 0.88 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:28 PM PDT 24
Peak memory 195340 kb
Host smart-26507cc2-3a9a-42a1-bbf7-ecf7b93a71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670079371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1670079371
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2409308679
Short name T15
Test name
Test status
Simulation time 120083869 ps
CPU time 1.07 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:30:29 PM PDT 24
Peak memory 195540 kb
Host smart-963f13ca-8ffa-45b9-9851-0501893a462e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409308679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2409308679
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1116524945
Short name T157
Test name
Test status
Simulation time 7829368226 ps
CPU time 54.39 seconds
Started Apr 23 12:30:26 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 198088 kb
Host smart-2b1156f1-1382-4d5a-9dfb-581d2130b8a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116524945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1116524945
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3306098236
Short name T918
Test name
Test status
Simulation time 57842308 ps
CPU time 1.14 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:00 PM PDT 24
Peak memory 196948 kb
Host smart-436af941-897b-4093-bd82-2e65b216d58b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3306098236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3306098236
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3100065787
Short name T900
Test name
Test status
Simulation time 66062584 ps
CPU time 0.78 seconds
Started Apr 23 12:23:26 PM PDT 24
Finished Apr 23 12:23:28 PM PDT 24
Peak memory 190300 kb
Host smart-42428bd2-174b-441e-8945-93f260443683
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100065787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3100065787
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.965220559
Short name T929
Test name
Test status
Simulation time 42889127 ps
CPU time 1.15 seconds
Started Apr 23 12:18:47 PM PDT 24
Finished Apr 23 12:18:49 PM PDT 24
Peak memory 191376 kb
Host smart-b799bf4f-fade-467a-b5c3-5e3054496cf3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=965220559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.965220559
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1977921296
Short name T913
Test name
Test status
Simulation time 175249103 ps
CPU time 1.21 seconds
Started Apr 23 12:22:34 PM PDT 24
Finished Apr 23 12:22:36 PM PDT 24
Peak memory 191128 kb
Host smart-2c642d06-3224-4910-b4dd-6e23f23858a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977921296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1977921296
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3372353934
Short name T849
Test name
Test status
Simulation time 179901476 ps
CPU time 0.97 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:34 PM PDT 24
Peak memory 196264 kb
Host smart-ca3ae344-8c53-4886-8ede-a687a16c9a91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3372353934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3372353934
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1689280565
Short name T908
Test name
Test status
Simulation time 270614567 ps
CPU time 1.29 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 189544 kb
Host smart-969cc9b2-684b-4269-9583-0856c60abb41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689280565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1689280565
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2276385926
Short name T867
Test name
Test status
Simulation time 215212713 ps
CPU time 1.06 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 191436 kb
Host smart-fae43e72-8574-417e-a5a7-6739002cf139
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2276385926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2276385926
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602834307
Short name T886
Test name
Test status
Simulation time 199122112 ps
CPU time 0.97 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 190048 kb
Host smart-8c7da7ef-4dc7-4469-8c74-ec8362e65f36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602834307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2602834307
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3795521566
Short name T854
Test name
Test status
Simulation time 433069607 ps
CPU time 1.33 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:26 PM PDT 24
Peak memory 190400 kb
Host smart-b6e92c7d-1754-4fff-9ea6-51a0874469fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3795521566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3795521566
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2396954459
Short name T850
Test name
Test status
Simulation time 123102299 ps
CPU time 1.21 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191412 kb
Host smart-c1121965-c20b-49f3-8ca9-f2be8085f6ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396954459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2396954459
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1358359839
Short name T921
Test name
Test status
Simulation time 74721813 ps
CPU time 0.73 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191320 kb
Host smart-0f8b3ee1-695a-4412-942a-6259c265a605
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1358359839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1358359839
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2111293300
Short name T928
Test name
Test status
Simulation time 97420466 ps
CPU time 1.23 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191444 kb
Host smart-8f3b4b48-1e5a-4bbf-9d46-9e2107fcc169
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111293300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2111293300
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1567264050
Short name T844
Test name
Test status
Simulation time 104547708 ps
CPU time 0.91 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 190396 kb
Host smart-9f90a012-c2b9-49f5-af87-35901e807952
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1567264050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1567264050
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747746543
Short name T925
Test name
Test status
Simulation time 110529441 ps
CPU time 0.92 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191404 kb
Host smart-58bf833f-94ff-41ad-a3e7-bd9e59437523
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747746543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2747746543
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2666631309
Short name T920
Test name
Test status
Simulation time 372881891 ps
CPU time 1.49 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:15 PM PDT 24
Peak memory 196740 kb
Host smart-e98e47c7-6552-4bd4-b9bf-f8f80ed2972c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2666631309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2666631309
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479621384
Short name T911
Test name
Test status
Simulation time 150617659 ps
CPU time 0.86 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 190292 kb
Host smart-d6583e3a-8dcf-4eba-8cfd-ef025f22fdcb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479621384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.479621384
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2818877754
Short name T874
Test name
Test status
Simulation time 65859884 ps
CPU time 1.07 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:34 PM PDT 24
Peak memory 189540 kb
Host smart-c68e3819-13b0-4f57-9ed2-09eeeca9c90e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2818877754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2818877754
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3251266539
Short name T909
Test name
Test status
Simulation time 57400756 ps
CPU time 1.45 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:35 PM PDT 24
Peak memory 191088 kb
Host smart-b419a004-6d4c-4a78-a408-181fa53b1aff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251266539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3251266539
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1438391951
Short name T856
Test name
Test status
Simulation time 38703527 ps
CPU time 1.27 seconds
Started Apr 23 12:22:02 PM PDT 24
Finished Apr 23 12:22:03 PM PDT 24
Peak memory 191448 kb
Host smart-f7964766-0d7a-4677-8df7-d12bb282a22c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1438391951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1438391951
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1578798950
Short name T905
Test name
Test status
Simulation time 35286582 ps
CPU time 0.8 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 195940 kb
Host smart-f6ee9491-0b50-4b37-8ca5-0371a6ae1a26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578798950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1578798950
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2366356915
Short name T907
Test name
Test status
Simulation time 74265831 ps
CPU time 1.45 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 190220 kb
Host smart-4c9c2853-5793-4f89-bbb3-3e628e41c8bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2366356915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2366356915
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908037678
Short name T846
Test name
Test status
Simulation time 34884596 ps
CPU time 0.96 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:00 PM PDT 24
Peak memory 191116 kb
Host smart-c8caa72f-45ef-40c1-b85d-bf6ffec4ee04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908037678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3908037678
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.255630129
Short name T842
Test name
Test status
Simulation time 65267184 ps
CPU time 1.09 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 191008 kb
Host smart-920f4119-d000-4990-85e4-19945b5ec79b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=255630129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.255630129
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2625001470
Short name T881
Test name
Test status
Simulation time 100934281 ps
CPU time 1.28 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191404 kb
Host smart-fdbb6856-fc09-4168-9d3c-8f80ed672d3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625001470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2625001470
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2924140450
Short name T897
Test name
Test status
Simulation time 166246000 ps
CPU time 1.4 seconds
Started Apr 23 12:22:58 PM PDT 24
Finished Apr 23 12:23:01 PM PDT 24
Peak memory 189788 kb
Host smart-778a80f2-f5bf-47f5-9a16-8234f11a5b3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2924140450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2924140450
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998047494
Short name T847
Test name
Test status
Simulation time 36747340 ps
CPU time 0.98 seconds
Started Apr 23 12:21:38 PM PDT 24
Finished Apr 23 12:21:40 PM PDT 24
Peak memory 191332 kb
Host smart-8a4f14bd-a4f5-4eb1-8a27-c569824bd992
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998047494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3998047494
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.399153851
Short name T912
Test name
Test status
Simulation time 97742943 ps
CPU time 0.86 seconds
Started Apr 23 12:21:29 PM PDT 24
Finished Apr 23 12:21:30 PM PDT 24
Peak memory 191524 kb
Host smart-c90b4d9b-0d0a-4857-b3d7-92b743a322f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=399153851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.399153851
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.456445702
Short name T839
Test name
Test status
Simulation time 62301758 ps
CPU time 1.18 seconds
Started Apr 23 12:21:32 PM PDT 24
Finished Apr 23 12:21:34 PM PDT 24
Peak memory 191456 kb
Host smart-15009de8-580f-45f0-b7ad-bf9d6c78abf2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456445702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.456445702
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4214495349
Short name T894
Test name
Test status
Simulation time 674128974 ps
CPU time 1.31 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 190048 kb
Host smart-cbbab582-e804-444a-bce3-8a05d8722b5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4214495349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4214495349
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1198274756
Short name T870
Test name
Test status
Simulation time 52071906 ps
CPU time 1.15 seconds
Started Apr 23 12:19:44 PM PDT 24
Finished Apr 23 12:19:46 PM PDT 24
Peak memory 191480 kb
Host smart-83440a19-41bf-443b-8c1b-29af01235c53
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198274756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1198274756
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4229862338
Short name T841
Test name
Test status
Simulation time 137707568 ps
CPU time 0.9 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:42 PM PDT 24
Peak memory 191100 kb
Host smart-130f6394-98ea-41a7-bf13-6479d47826e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4229862338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4229862338
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908721404
Short name T895
Test name
Test status
Simulation time 60448053 ps
CPU time 1.18 seconds
Started Apr 23 12:21:19 PM PDT 24
Finished Apr 23 12:21:21 PM PDT 24
Peak memory 191400 kb
Host smart-ed9c3e4c-c2b5-4ecc-9c59-357e2f9b07f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908721404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3908721404
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4197704573
Short name T853
Test name
Test status
Simulation time 231453211 ps
CPU time 0.91 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191424 kb
Host smart-7281570c-515c-438b-a77f-ec93f78a88d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4197704573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4197704573
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1349009095
Short name T932
Test name
Test status
Simulation time 89333747 ps
CPU time 1.39 seconds
Started Apr 23 12:21:32 PM PDT 24
Finished Apr 23 12:21:34 PM PDT 24
Peak memory 191404 kb
Host smart-4435ddcd-5e58-46a5-b04e-4be2f33e3db4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349009095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1349009095
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3723608785
Short name T919
Test name
Test status
Simulation time 132999251 ps
CPU time 1.52 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:25 PM PDT 24
Peak memory 197456 kb
Host smart-dc15accf-0c32-45ba-992d-88ff7ae3bab1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3723608785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3723608785
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2260535143
Short name T871
Test name
Test status
Simulation time 37517265 ps
CPU time 0.71 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 190104 kb
Host smart-335f6a00-967e-43b1-973f-223f56b6e276
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260535143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2260535143
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.983271046
Short name T914
Test name
Test status
Simulation time 22478480 ps
CPU time 0.73 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 191352 kb
Host smart-ec80cb73-3fec-4fd4-8194-0d795e7f81ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=983271046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.983271046
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604012513
Short name T859
Test name
Test status
Simulation time 335774115 ps
CPU time 1.52 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 195972 kb
Host smart-2f7b2fbc-6727-4922-82a9-fc584f4d116a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604012513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3604012513
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.873475635
Short name T857
Test name
Test status
Simulation time 48243076 ps
CPU time 1.21 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:15 PM PDT 24
Peak memory 191140 kb
Host smart-95aca741-e354-490f-bcc4-36571b6dc576
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=873475635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.873475635
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1661239244
Short name T926
Test name
Test status
Simulation time 182219999 ps
CPU time 1.14 seconds
Started Apr 23 12:19:52 PM PDT 24
Finished Apr 23 12:19:54 PM PDT 24
Peak memory 197544 kb
Host smart-22f78dd5-fc05-4bd4-88ef-5dfe5f8ba153
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661239244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1661239244
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1001798251
Short name T892
Test name
Test status
Simulation time 171496773 ps
CPU time 1 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 191076 kb
Host smart-532f732b-1eaa-49ad-95f3-e15a3e6c9efc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1001798251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1001798251
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2899968131
Short name T868
Test name
Test status
Simulation time 175979531 ps
CPU time 0.92 seconds
Started Apr 23 12:23:26 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 191148 kb
Host smart-d4c7761b-dcda-406d-9780-693bba53d1ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899968131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2899968131
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4198285212
Short name T848
Test name
Test status
Simulation time 52884924 ps
CPU time 1.08 seconds
Started Apr 23 12:18:49 PM PDT 24
Finished Apr 23 12:18:50 PM PDT 24
Peak memory 197232 kb
Host smart-b8bde67b-de80-4962-a629-d48064c46363
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4198285212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4198285212
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616442211
Short name T869
Test name
Test status
Simulation time 58312764 ps
CPU time 1.27 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:15 PM PDT 24
Peak memory 197504 kb
Host smart-b9da1c6b-0d35-444e-ad21-569dd6a02beb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616442211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2616442211
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1498473557
Short name T922
Test name
Test status
Simulation time 205965395 ps
CPU time 1.11 seconds
Started Apr 23 12:22:12 PM PDT 24
Finished Apr 23 12:22:14 PM PDT 24
Peak memory 196096 kb
Host smart-db93873f-18c7-4804-8633-7aaf9d1b27bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1498473557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1498473557
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854357440
Short name T865
Test name
Test status
Simulation time 40617355 ps
CPU time 1.17 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 190540 kb
Host smart-be645645-5d7f-489d-92e8-a1d68ff695e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854357440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.854357440
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2591055222
Short name T889
Test name
Test status
Simulation time 318005796 ps
CPU time 1.19 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 191324 kb
Host smart-b3d03888-09e7-4f66-934f-54008eec5611
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2591055222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2591055222
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768170677
Short name T934
Test name
Test status
Simulation time 162835032 ps
CPU time 1.44 seconds
Started Apr 23 12:21:44 PM PDT 24
Finished Apr 23 12:21:45 PM PDT 24
Peak memory 191352 kb
Host smart-c74bc652-4ff3-41cc-9b0c-e6c4da869339
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768170677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.768170677
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1518027934
Short name T866
Test name
Test status
Simulation time 56190383 ps
CPU time 1.04 seconds
Started Apr 23 12:18:44 PM PDT 24
Finished Apr 23 12:18:45 PM PDT 24
Peak memory 191404 kb
Host smart-288150e4-bab9-4db5-b3be-b9ff24f54581
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1518027934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1518027934
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154672542
Short name T891
Test name
Test status
Simulation time 222998640 ps
CPU time 1.19 seconds
Started Apr 23 12:21:57 PM PDT 24
Finished Apr 23 12:21:59 PM PDT 24
Peak memory 191424 kb
Host smart-538ec5f2-1504-4d3d-9261-f3a2c37af5b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154672542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.154672542
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2884144079
Short name T879
Test name
Test status
Simulation time 54282854 ps
CPU time 1.45 seconds
Started Apr 23 12:29:56 PM PDT 24
Finished Apr 23 12:29:59 PM PDT 24
Peak memory 191432 kb
Host smart-11bb86cd-3a79-41b8-b95f-7a37a31771b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2884144079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2884144079
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013175175
Short name T838
Test name
Test status
Simulation time 56173848 ps
CPU time 1.24 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 191344 kb
Host smart-aedb42ce-29be-4606-a3f4-3bb00d3b3e9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013175175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1013175175
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.87930539
Short name T936
Test name
Test status
Simulation time 30451960 ps
CPU time 0.97 seconds
Started Apr 23 12:29:58 PM PDT 24
Finished Apr 23 12:29:59 PM PDT 24
Peak memory 191480 kb
Host smart-20df8b9d-503e-43b0-bc10-a7775c750d81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=87930539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.87930539
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749581598
Short name T902
Test name
Test status
Simulation time 153802758 ps
CPU time 1.39 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:02 PM PDT 24
Peak memory 191328 kb
Host smart-a25e99fa-e5c6-4c79-94b0-c342793ef798
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749581598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749581598
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3537753242
Short name T878
Test name
Test status
Simulation time 79206955 ps
CPU time 1.25 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:04 PM PDT 24
Peak memory 191444 kb
Host smart-1aff3db5-56b8-4e36-bff9-ac6b6c842e4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3537753242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3537753242
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2385577356
Short name T861
Test name
Test status
Simulation time 146783892 ps
CPU time 1.25 seconds
Started Apr 23 12:30:00 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 191348 kb
Host smart-09131151-8289-4a3b-a7f7-e12e43bd2067
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385577356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2385577356
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.274397602
Short name T901
Test name
Test status
Simulation time 302859432 ps
CPU time 1.33 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:01 PM PDT 24
Peak memory 191428 kb
Host smart-b69f3390-7cb3-4e1a-a60e-e9f105ec7d70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=274397602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.274397602
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737593459
Short name T915
Test name
Test status
Simulation time 176214501 ps
CPU time 1.47 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:02 PM PDT 24
Peak memory 197764 kb
Host smart-8c74ac57-bf8f-4b39-9572-52f7e9b8ab4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737593459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1737593459
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1818856456
Short name T872
Test name
Test status
Simulation time 431074175 ps
CPU time 1.28 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:01 PM PDT 24
Peak memory 191428 kb
Host smart-2d3f895b-1eac-4dc5-911d-9552d8d5cd3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1818856456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1818856456
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3568553226
Short name T840
Test name
Test status
Simulation time 304740883 ps
CPU time 1.48 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:04 PM PDT 24
Peak memory 191412 kb
Host smart-a2a181e1-8aa9-4ee9-8e23-b8183c440253
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568553226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3568553226
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3440323384
Short name T903
Test name
Test status
Simulation time 64569275 ps
CPU time 1.37 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:02 PM PDT 24
Peak memory 191356 kb
Host smart-9fd4be3a-7311-4d71-adbc-4c1b0d848e4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3440323384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3440323384
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549899543
Short name T924
Test name
Test status
Simulation time 37194997 ps
CPU time 0.85 seconds
Started Apr 23 12:30:00 PM PDT 24
Finished Apr 23 12:30:02 PM PDT 24
Peak memory 191368 kb
Host smart-9637d1d9-7164-49b5-96d5-ffe0e530720e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549899543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3549899543
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3893256895
Short name T937
Test name
Test status
Simulation time 114775058 ps
CPU time 1.1 seconds
Started Apr 23 12:30:00 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 191460 kb
Host smart-0fbe9b72-49f0-4433-b23b-0ba593ddc583
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3893256895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3893256895
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284440904
Short name T890
Test name
Test status
Simulation time 40438435 ps
CPU time 0.95 seconds
Started Apr 23 12:30:01 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 191356 kb
Host smart-6d35f784-cd94-4efe-a632-e6ec584f4dec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284440904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.284440904
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2194850322
Short name T876
Test name
Test status
Simulation time 29833539 ps
CPU time 0.84 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:01 PM PDT 24
Peak memory 191332 kb
Host smart-7d933e1a-4a72-4b43-a1a4-1c3ee8b08c9e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2194850322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2194850322
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217493939
Short name T873
Test name
Test status
Simulation time 117581758 ps
CPU time 0.82 seconds
Started Apr 23 12:29:58 PM PDT 24
Finished Apr 23 12:30:00 PM PDT 24
Peak memory 191340 kb
Host smart-9ca0384f-b8ef-441f-9261-ed092dc14b46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217493939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3217493939
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2352239546
Short name T884
Test name
Test status
Simulation time 60495767 ps
CPU time 1 seconds
Started Apr 23 12:29:59 PM PDT 24
Finished Apr 23 12:30:01 PM PDT 24
Peak memory 197696 kb
Host smart-ed7d3a8d-641f-42fe-b4b9-34ce0203dc0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2352239546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2352239546
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2489684242
Short name T855
Test name
Test status
Simulation time 100354841 ps
CPU time 1 seconds
Started Apr 23 12:30:00 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 191452 kb
Host smart-2ca816a6-8d47-415e-bb79-0d56ad11aba6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489684242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2489684242
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3125732186
Short name T916
Test name
Test status
Simulation time 51420989 ps
CPU time 1.37 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:19:40 PM PDT 24
Peak memory 197072 kb
Host smart-985ed37d-05f6-4312-81f3-b60daed06504
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3125732186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3125732186
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773357190
Short name T862
Test name
Test status
Simulation time 360599617 ps
CPU time 1.34 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 196948 kb
Host smart-5dd88aca-5902-4d3c-bf72-1975df9a87df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773357190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2773357190
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2757850064
Short name T882
Test name
Test status
Simulation time 60589825 ps
CPU time 1.15 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 191400 kb
Host smart-4881e133-faf7-4dfb-8924-e9597b1a38f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2757850064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2757850064
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.501251548
Short name T885
Test name
Test status
Simulation time 116073112 ps
CPU time 1.19 seconds
Started Apr 23 12:30:05 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 191396 kb
Host smart-b1208e20-eeb2-4d9e-924f-0732731bc0a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501251548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.501251548
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2236695081
Short name T888
Test name
Test status
Simulation time 193609982 ps
CPU time 1.36 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 191388 kb
Host smart-0f1178a1-6e9c-4efa-bd2b-0eed2f6e1b2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2236695081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2236695081
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193750400
Short name T875
Test name
Test status
Simulation time 1485608749 ps
CPU time 1.45 seconds
Started Apr 23 12:30:02 PM PDT 24
Finished Apr 23 12:30:05 PM PDT 24
Peak memory 197088 kb
Host smart-564dd2f2-bdf6-4b16-9263-9a764b02f3e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193750400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.193750400
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4283626945
Short name T898
Test name
Test status
Simulation time 442515559 ps
CPU time 1.26 seconds
Started Apr 23 12:30:02 PM PDT 24
Finished Apr 23 12:30:05 PM PDT 24
Peak memory 191412 kb
Host smart-5b7bd064-4b1f-4e07-968a-593f3f7d2726
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4283626945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4283626945
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539020858
Short name T880
Test name
Test status
Simulation time 23047359 ps
CPU time 0.8 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:05 PM PDT 24
Peak memory 191336 kb
Host smart-296dd059-9d7b-4900-96d0-a683a33a68fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539020858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2539020858
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4284370284
Short name T851
Test name
Test status
Simulation time 31507317 ps
CPU time 0.9 seconds
Started Apr 23 12:30:05 PM PDT 24
Finished Apr 23 12:30:07 PM PDT 24
Peak memory 191288 kb
Host smart-fabd9e73-e12b-48e3-bd14-4bd3b2868567
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4284370284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4284370284
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2704255889
Short name T917
Test name
Test status
Simulation time 35114159 ps
CPU time 0.82 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 196016 kb
Host smart-8e5de9ac-29f6-42e8-9542-46667e3a353f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704255889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2704255889
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1274395216
Short name T887
Test name
Test status
Simulation time 231991520 ps
CPU time 1.13 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 196112 kb
Host smart-4794b98e-1239-4121-a952-ebde0f75766a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1274395216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1274395216
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3831189613
Short name T852
Test name
Test status
Simulation time 94246124 ps
CPU time 0.79 seconds
Started Apr 23 12:30:02 PM PDT 24
Finished Apr 23 12:30:04 PM PDT 24
Peak memory 191348 kb
Host smart-1ee34ca1-c334-4354-8fbd-cb2b68c6afca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831189613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3831189613
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1955716183
Short name T904
Test name
Test status
Simulation time 46933572 ps
CPU time 1.26 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:05 PM PDT 24
Peak memory 191380 kb
Host smart-4ef9eee4-f1b7-4b50-b013-6ab1f3b76f67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1955716183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1955716183
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.212447904
Short name T933
Test name
Test status
Simulation time 330658499 ps
CPU time 1.52 seconds
Started Apr 23 12:30:04 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 197644 kb
Host smart-fd1f9b66-67bb-4c6d-8b63-cd680620677d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212447904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.212447904
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1479325127
Short name T843
Test name
Test status
Simulation time 38651332 ps
CPU time 1.22 seconds
Started Apr 23 12:30:04 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 197432 kb
Host smart-2bb036c1-d4e7-47d2-b193-1d94b6856e48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1479325127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1479325127
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2393177222
Short name T906
Test name
Test status
Simulation time 43718894 ps
CPU time 1 seconds
Started Apr 23 12:30:04 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 197712 kb
Host smart-147d321c-cf4d-4cf5-b148-3cc07339025f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393177222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2393177222
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4254527776
Short name T930
Test name
Test status
Simulation time 204546786 ps
CPU time 1.44 seconds
Started Apr 23 12:30:03 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 191464 kb
Host smart-9cd67c71-da5d-4e70-868f-28751e4ec90e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4254527776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4254527776
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466841306
Short name T860
Test name
Test status
Simulation time 64782455 ps
CPU time 1.26 seconds
Started Apr 23 12:30:06 PM PDT 24
Finished Apr 23 12:30:08 PM PDT 24
Peak memory 191360 kb
Host smart-efa5e2aa-5203-481b-8dfb-a5ec761817ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466841306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2466841306
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2944447700
Short name T877
Test name
Test status
Simulation time 209706046 ps
CPU time 1.14 seconds
Started Apr 23 12:30:09 PM PDT 24
Finished Apr 23 12:30:11 PM PDT 24
Peak memory 197796 kb
Host smart-aefaca99-92b8-4c96-8d74-6e8dae7b4f54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2944447700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2944447700
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1468258676
Short name T863
Test name
Test status
Simulation time 95571010 ps
CPU time 1.37 seconds
Started Apr 23 12:30:10 PM PDT 24
Finished Apr 23 12:30:12 PM PDT 24
Peak memory 191412 kb
Host smart-33ffbc6b-0b57-4316-a94f-d2400f2d0091
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468258676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1468258676
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1358700010
Short name T910
Test name
Test status
Simulation time 465160022 ps
CPU time 0.84 seconds
Started Apr 23 12:30:07 PM PDT 24
Finished Apr 23 12:30:09 PM PDT 24
Peak memory 197620 kb
Host smart-f73bd850-e7cf-4b77-bd10-04e7629b9413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1358700010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1358700010
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557987277
Short name T931
Test name
Test status
Simulation time 104568539 ps
CPU time 0.83 seconds
Started Apr 23 12:30:11 PM PDT 24
Finished Apr 23 12:30:13 PM PDT 24
Peak memory 195836 kb
Host smart-a48416e3-76de-43ec-a09c-4046b04b6a12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557987277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3557987277
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.472587316
Short name T883
Test name
Test status
Simulation time 125500954 ps
CPU time 0.92 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 190228 kb
Host smart-9e0edf1c-0fb8-450e-b16c-6da9f2d95c8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=472587316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.472587316
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2295324763
Short name T858
Test name
Test status
Simulation time 200545785 ps
CPU time 1.54 seconds
Started Apr 23 12:20:17 PM PDT 24
Finished Apr 23 12:20:20 PM PDT 24
Peak memory 197736 kb
Host smart-09146ce7-18fb-47a4-b9d1-332c9b6b9d4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295324763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2295324763
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4041779378
Short name T899
Test name
Test status
Simulation time 76013320 ps
CPU time 1.43 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 190188 kb
Host smart-0515f9dd-7e75-4417-83a4-6721503621b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4041779378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.4041779378
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3260584285
Short name T927
Test name
Test status
Simulation time 77227637 ps
CPU time 1.43 seconds
Started Apr 23 12:23:48 PM PDT 24
Finished Apr 23 12:23:51 PM PDT 24
Peak memory 190524 kb
Host smart-794fdfe2-6217-4e01-a356-ee78101d1083
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260584285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3260584285
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3888244086
Short name T896
Test name
Test status
Simulation time 57218908 ps
CPU time 1.39 seconds
Started Apr 23 12:21:27 PM PDT 24
Finished Apr 23 12:21:29 PM PDT 24
Peak memory 197680 kb
Host smart-456d4306-f840-4988-bebb-82e7e26a26e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3888244086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3888244086
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.34561478
Short name T923
Test name
Test status
Simulation time 292572845 ps
CPU time 1.23 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 191164 kb
Host smart-3c8e72a6-bbdc-4093-b65d-1d8e9bec4acd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34561478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.34561478
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1876806574
Short name T893
Test name
Test status
Simulation time 170309338 ps
CPU time 1.21 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 190332 kb
Host smart-c6168941-91f1-41b4-9869-19d75df6e995
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1876806574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1876806574
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156740998
Short name T935
Test name
Test status
Simulation time 208290437 ps
CPU time 0.98 seconds
Started Apr 23 12:23:54 PM PDT 24
Finished Apr 23 12:23:56 PM PDT 24
Peak memory 190616 kb
Host smart-711b3f6c-e3e9-40b0-85f2-939653bc7ab5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156740998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3156740998
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1203114612
Short name T845
Test name
Test status
Simulation time 295561692 ps
CPU time 1.3 seconds
Started Apr 23 12:23:51 PM PDT 24
Finished Apr 23 12:23:54 PM PDT 24
Peak memory 196964 kb
Host smart-8fdf55c0-66ad-4d81-9924-6b07b5608253
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1203114612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1203114612
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2923568853
Short name T864
Test name
Test status
Simulation time 170298744 ps
CPU time 0.95 seconds
Started Apr 23 12:18:48 PM PDT 24
Finished Apr 23 12:18:49 PM PDT 24
Peak memory 191460 kb
Host smart-6f79efcf-2ae3-4280-9ac4-554a1d211b1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923568853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2923568853
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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