HMAC Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	5.170s	484.207us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.720s	92.658us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.780s	87.282us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.390s	790.872us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.280s	53.028us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.612m	359.130ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.780s	87.282us	20	20	100.00
		hmac_csr_aliasing	2.280s	53.028us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.891m	4.202ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	52.380s	18.602ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.276m	55.190ms	49	50	98.00
		hmac_test_hmac_vectors	1.230s	69.138us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.143m	6.134ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.385m	5.146ms	50	50	100.00
V2	error	hmac_error	3.496m	67.351ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.436m	60.700ms	50	50	100.00
V2	stress_all	hmac_stress_all	51.965m	190.300ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	16.514us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	11.225us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.410s	65.934us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.410s	65.934us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.720s	92.658us	5	5	100.00
		hmac_csr_rw	0.780s	87.282us	20	20	100.00
		hmac_csr_aliasing	2.280s	53.028us	5	5	100.00
		hmac_same_csr_outstanding	1.370s	133.703us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.720s	92.658us	5	5	100.00
		hmac_csr_rw	0.780s	87.282us	20	20	100.00
		hmac_csr_aliasing	2.280s	53.028us	5	5	100.00
		hmac_same_csr_outstanding	1.370s	133.703us	20	20	100.00
V2		TOTAL			589	590	99.83
V2S	tl_intg_err	hmac_sec_cm	0.850s	74.141us	5	5	100.00
		hmac_tl_intg_err	2.500s	163.935us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.500s	163.935us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	5.170s	484.207us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.066h	583.740ms	196	200	98.00
V3		TOTAL			196	200	98.00
		TOTAL			915	920	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.54	98.80	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 3 failures:

Test hmac_stress_all_with_rand_reset has 3 failures.

46.hmac_stress_all_with_rand_reset.4110402312
Line 857, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/46.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42582395785 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42582395785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.hmac_stress_all_with_rand_reset.405300045
Line 796, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/51.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21796116057 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 21796116057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha_vectors has 1 failures.
  - 33.hmac_test_sha_vectors.580131499
    Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 97.hmac_stress_all_with_rand_reset.2171464428
    Line 940, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/97.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51586336667 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 51586336667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```