Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 70562525 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 84687515 1 T13 4273 T14 69 T15 17



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 59967675 1 T13 3065 T14 53 T15 20
values[0x0] 44164420 1 T13 1503 T14 24 T15 6
values[0x1] 51117945 1 T13 1556 T14 20 T15 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 51849945 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 103400095 1 T13 4624 T14 70 T15 20



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 621785 1 T13 36 T14 6 T17 581
valid_sources[0x01] 617245 1 T13 31 T17 569 T20 31
valid_sources[0x02] 613635 1 T13 22 T17 544 T18 1
valid_sources[0x03] 575715 1 T13 39 T17 522 T18 1
valid_sources[0x04] 602090 1 T13 18 T17 566 T18 3
valid_sources[0x05] 612355 1 T13 11 T17 568 T18 2
valid_sources[0x06] 602975 1 T13 32 T17 577 T18 2
valid_sources[0x07] 595550 1 T13 31 T17 582 T20 31
valid_sources[0x08] 613355 1 T13 21 T15 4 T16 4
valid_sources[0x09] 576295 1 T13 29 T17 536 T20 29
valid_sources[0x0a] 590545 1 T13 25 T17 462 T18 2
valid_sources[0x0b] 579105 1 T13 21 T14 2 T17 560
valid_sources[0x0c] 653020 1 T13 18 T17 533 T20 18
valid_sources[0x0d] 577295 1 T13 36 T17 579 T20 36
valid_sources[0x0e] 608025 1 T13 23 T17 473 T18 1
valid_sources[0x0f] 593165 1 T13 22 T14 2 T17 530
valid_sources[0x10] 596960 1 T13 20 T14 1 T17 584
valid_sources[0x11] 582285 1 T13 31 T17 584 T18 1
valid_sources[0x12] 610190 1 T13 10 T17 631 T20 10
valid_sources[0x13] 656235 1 T13 7 T17 624 T18 3
valid_sources[0x14] 616100 1 T13 44 T17 496 T20 44
valid_sources[0x15] 595940 1 T13 17 T17 515 T20 17
valid_sources[0x16] 633115 1 T13 15 T17 467 T18 2
valid_sources[0x17] 587895 1 T13 24 T17 521 T18 1
valid_sources[0x18] 630215 1 T13 11 T17 466 T18 1
valid_sources[0x19] 583545 1 T13 47 T17 622 T18 2
valid_sources[0x1a] 623315 1 T13 32 T17 576 T20 32
valid_sources[0x1b] 599330 1 T13 3 T17 539 T20 3
valid_sources[0x1c] 602080 1 T13 10 T17 529 T20 10
valid_sources[0x1d] 621910 1 T13 17 T17 588 T18 1
valid_sources[0x1e] 607175 1 T13 9 T17 498 T20 9
valid_sources[0x1f] 638365 1 T13 15 T17 578 T18 6
valid_sources[0x20] 567605 1 T13 56 T17 588 T18 2
valid_sources[0x21] 583595 1 T13 33 T14 1 T17 616
valid_sources[0x22] 589365 1 T13 26 T14 3 T17 525
valid_sources[0x23] 627100 1 T13 36 T17 588 T20 36
valid_sources[0x24] 606195 1 T13 17 T17 529 T18 1
valid_sources[0x25] 613525 1 T13 32 T17 498 T20 32
valid_sources[0x26] 601310 1 T13 9 T17 594 T20 9
valid_sources[0x27] 607610 1 T13 39 T17 499 T20 39
valid_sources[0x28] 588530 1 T13 28 T17 504 T18 2
valid_sources[0x29] 599040 1 T13 17 T17 526 T20 17
valid_sources[0x2a] 621505 1 T13 19 T17 553 T20 19
valid_sources[0x2b] 639510 1 T13 30 T17 601 T20 30
valid_sources[0x2c] 604285 1 T13 15 T17 416 T20 15
valid_sources[0x2d] 587420 1 T13 8 T17 554 T18 3
valid_sources[0x2e] 592990 1 T13 22 T17 583 T20 22
valid_sources[0x2f] 606870 1 T13 32 T15 5 T16 5
valid_sources[0x30] 602125 1 T13 21 T17 536 T18 4
valid_sources[0x31] 616530 1 T13 10 T14 6 T17 541
valid_sources[0x32] 630225 1 T13 13 T17 556 T18 1
valid_sources[0x33] 601600 1 T13 32 T17 523 T18 4
valid_sources[0x34] 623680 1 T13 5 T17 545 T20 5
valid_sources[0x35] 593330 1 T13 5 T14 4 T17 638
valid_sources[0x36] 562165 1 T13 49 T17 505 T20 49
valid_sources[0x37] 591385 1 T13 14 T17 493 T20 14
valid_sources[0x38] 624060 1 T13 29 T17 531 T18 1
valid_sources[0x39] 595515 1 T13 25 T17 525 T18 2
valid_sources[0x3a] 593510 1 T13 14 T17 619 T20 14
valid_sources[0x3b] 574320 1 T13 8 T17 702 T18 1
valid_sources[0x3c] 656895 1 T13 33 T17 570 T18 4
valid_sources[0x3d] 635410 1 T13 9 T17 514 T20 9
valid_sources[0x3e] 581925 1 T13 26 T17 529 T20 26
valid_sources[0x3f] 565005 1 T13 31 T17 504 T18 2
valid_sources[0x40] 613300 1 T13 20 T17 535 T20 20
valid_sources[0x41] 584825 1 T13 57 T17 610 T20 57
valid_sources[0x42] 624975 1 T13 11 T17 614 T18 4
valid_sources[0x43] 597825 1 T13 8 T17 560 T20 8
valid_sources[0x44] 614295 1 T13 9 T17 574 T20 9
valid_sources[0x45] 632830 1 T13 4 T17 577 T18 3
valid_sources[0x46] 635680 1 T13 39 T17 520 T20 39
valid_sources[0x47] 607285 1 T13 25 T17 684 T18 1
valid_sources[0x48] 617340 1 T13 33 T17 478 T18 2
valid_sources[0x49] 612995 1 T13 43 T17 632 T18 1
valid_sources[0x4a] 614140 1 T13 20 T17 553 T20 20
valid_sources[0x4b] 621625 1 T13 33 T17 622 T18 4
valid_sources[0x4c] 617870 1 T13 32 T14 2 T17 607
valid_sources[0x4d] 591820 1 T13 24 T14 2 T17 493
valid_sources[0x4e] 570710 1 T13 26 T17 483 T18 1
valid_sources[0x4f] 642145 1 T13 41 T14 7 T17 614
valid_sources[0x50] 614570 1 T13 19 T17 518 T20 19
valid_sources[0x51] 579950 1 T13 25 T14 1 T17 524
valid_sources[0x52] 575495 1 T13 39 T17 655 T20 39
valid_sources[0x53] 604415 1 T13 7 T17 541 T18 1
valid_sources[0x54] 608580 1 T13 27 T17 509 T18 2
valid_sources[0x55] 646100 1 T13 11 T17 618 T18 4
valid_sources[0x56] 592920 1 T13 32 T17 635 T18 1
valid_sources[0x57] 597600 1 T13 17 T17 502 T20 17
valid_sources[0x58] 608700 1 T13 45 T17 645 T18 1
valid_sources[0x59] 604325 1 T13 33 T17 629 T18 1
valid_sources[0x5a] 602960 1 T13 20 T17 615 T18 1
valid_sources[0x5b] 589270 1 T13 6 T17 570 T18 1
valid_sources[0x5c] 615015 1 T13 39 T17 501 T20 39
valid_sources[0x5d] 603395 1 T13 27 T14 3 T17 565
valid_sources[0x5e] 582970 1 T13 28 T15 2 T16 2
valid_sources[0x5f] 555175 1 T13 42 T17 537 T18 12
valid_sources[0x60] 590020 1 T13 19 T17 601 T18 1
valid_sources[0x61] 599530 1 T13 53 T17 537 T18 1
valid_sources[0x62] 632550 1 T13 35 T14 1 T17 638
valid_sources[0x63] 586180 1 T13 11 T17 600 T20 11
valid_sources[0x64] 596660 1 T13 12 T17 509 T20 12
valid_sources[0x65] 590385 1 T13 14 T15 3 T16 3
valid_sources[0x66] 610215 1 T13 21 T17 551 T20 21
valid_sources[0x67] 592285 1 T13 20 T17 573 T18 3
valid_sources[0x68] 629475 1 T13 15 T14 5 T17 647
valid_sources[0x69] 578930 1 T13 58 T17 570 T20 58
valid_sources[0x6a] 619950 1 T13 20 T17 505 T18 3
valid_sources[0x6b] 585725 1 T13 21 T17 605 T20 21
valid_sources[0x6c] 591740 1 T13 16 T14 4 T17 500
valid_sources[0x6d] 598795 1 T13 16 T14 1 T17 531
valid_sources[0x6e] 591170 1 T13 16 T17 490 T20 16
valid_sources[0x6f] 612745 1 T13 30 T17 536 T18 2
valid_sources[0x70] 603975 1 T13 34 T17 639 T18 1
valid_sources[0x71] 635840 1 T13 20 T17 560 T18 6
valid_sources[0x72] 631670 1 T13 28 T17 561 T20 28
valid_sources[0x73] 586215 1 T13 21 T17 645 T20 21
valid_sources[0x74] 574625 1 T13 15 T17 513 T18 2
valid_sources[0x75] 588630 1 T13 40 T17 559 T20 40
valid_sources[0x76] 581280 1 T13 27 T17 529 T20 27
valid_sources[0x77] 646470 1 T13 4 T17 497 T20 4
valid_sources[0x78] 625990 1 T13 24 T14 2 T17 539
valid_sources[0x79] 582125 1 T13 26 T17 596 T18 2
valid_sources[0x7a] 630075 1 T13 39 T17 632 T20 39
valid_sources[0x7b] 624185 1 T13 4 T17 632 T20 4
valid_sources[0x7c] 656635 1 T13 19 T17 600 T18 3
valid_sources[0x7d] 580325 1 T13 9 T17 700 T18 1
valid_sources[0x7e] 601900 1 T13 13 T17 514 T20 13
valid_sources[0x7f] 600240 1 T13 20 T14 2 T17 624
valid_sources[0x80] 598960 1 T13 38 T17 494 T18 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 30258760 1 T13 1558 T14 30 T15 11
values[0x0] all_enables biggest_size 28275395 1 T13 1353 T14 21 T15 5
values[0x1] all_enables biggest_size 26153360 1 T13 1362 T14 18 T15 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%