Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1811311060	30868540	0	0
intr_enable_rd_A	1811311060	23785	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1811311060	30868540	0	0
T17	726080	214451	0	0
T18	11153	382	0	0
T19	1287	0	0	0
T20	56665	0	0	0
T21	1287	0	0	0
T22	1287	0	0	0
T23	11153	382	0	0
T24	1287	0	0	0
T25	0	382	0	0
T32	4985	0	0	0
T33	10084	4	0	0
T73	0	4	0	0
T74	0	4	0	0
T75	0	4	0	0
T76	0	4	0	0
T77	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1811311060	23785	0	0
T13	56665	256	0	0
T14	1752	8	0	0
T15	1287	6	0	0
T16	1287	6	0	0
T17	726080	118	0	0
T18	11153	0	0	0
T19	1287	6	0	0
T20	56665	256	0	0
T21	1287	6	0	0
T22	1287	6	0	0
T24	0	6	0	0