Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.10	100.00	93.75			86.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_packer	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	156	4	4	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	9	9	100.00
ALWAYS	213	8	8	100.00
ALWAYS	234	3	3	100.00
ALWAYS	242	14	14	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	290	0	0
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	298	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
164	1	1
165	1	1
169	1	1
170	1	1
173	1	1
174	1	1
177	1	1
179	1	1
184	1	1
186	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
234	1	1
235	1	1
237	1	1
242	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
257	1	1
258	1	1
260	1	1
261	1	1
263	1	1
265	1	1
266	1	1
278	1	1
282	1	1
290		unreachable
293	1	1
294	1	1
295	1	1
298		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T7,T34,T35
1	Not Covered

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T2,T3,T7
1	1	Covered	T2,T3,T4

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T4

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T2,T3,T4

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	26	86.67
TERNARY	169	2	2	100.00
TERNARY	170	2	2	100.00
TERNARY	282	1	1	100.00
IF	158	2	2	100.00
CASE	184	5	4	80.00
IF	213	3	3	100.00
IF	234	2	2	100.00
CASE	247	5	4	80.00
CASE	80	5	3	60.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T2,T3,T4
2'b10	Covered	T2,T3,T4
2'b11	Covered	T7,T34,T35
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T2,T3,T4
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T2,T3,T4
FlushSend	-	0	Covered	T2,T3,T4
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T2,T3,T4
2'b01	0	-	Unreachable	T2,T3,T4
2'b10	-	-	Covered	T2,T3,T4
2'b11	-	1	Not Covered
2'b11	-	0	Unreachable	T7,T34,T35
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	1665129060	3702100	0	755
DataOStableWhenPending_A	1665129060	3743050	0	755
ExFlushValid_M	1665129060	124600	0	0
ExcessiveDataStored_A	1665129060	18550	0	0
ExcessiveMaskStored_A	1665129060	18550	0	0
FlushFollowedByDone_A	1665129060	124600	0	755
ValidIDeassertedOnFlush_M	1665129060	215400	0	0
ValidOAssertedForStoredDataGTEOutW_A	1665129060	33715700	0	0
ValidOPairedWidthReadyI_A	1665129060	3743050	0	0
gen_mask_assert.ContiguousOnesMask_M	1665129060	42458850	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3702100	0	755
T2	272352	9	0	1
T3	272352	9	0	1
T4	450583	0	0	1
T5	450583	0	0	1
T6	450583	0	0	1
T7	0	74033	0	0
T8	837725	0	0	1
T9	252231	0	0	1
T10	252231	0	0	1
T11	357921	0	0	1
T12	252231	0	0	1
T34	0	74033	0	0
T35	0	74033	0	0
T36	0	9	0	0
T37	0	9	0	0
T38	0	9	0	0
T39	0	9	0	0
T40	0	74033	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3743050	0	755
T2	272352	10	0	1
T3	272352	10	0	1
T4	450583	0	0	1
T5	450583	0	0	1
T6	450583	0	0	1
T7	0	74851	0	0
T8	837725	0	0	1
T9	252231	0	0	1
T10	252231	0	0	1
T11	357921	0	0	1
T12	252231	0	0	1
T34	0	74851	0	0
T35	0	74851	0	0
T36	0	10	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	74851	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	124600	0	0
T2	272352	46	0	0
T3	272352	46	0	0
T4	450583	340	0	0
T5	450583	340	0	0
T6	450583	340	0	0
T8	837725	46	0	0
T9	252231	46	0	0
T10	252231	46	0	0
T11	357921	194	0	0
T12	252231	46	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	18550	0	0
T7	145162	371	0	0
T34	145162	371	0	0
T35	0	371	0	0
T36	272352	0	0	0
T37	272352	0	0	0
T40	0	371	0	0
T41	0	371	0	0
T42	0	371	0	0
T43	0	371	0	0
T44	0	371	0	0
T45	0	371	0	0
T46	0	371	0	0
T47	252231	0	0	0
T48	450583	0	0	0
T49	450583	0	0	0
T50	4273	0	0	0
T51	821217	0	0	0
T52	450583	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	18550	0	0
T7	145162	371	0	0
T34	145162	371	0	0
T35	0	371	0	0
T36	272352	0	0	0
T37	272352	0	0	0
T40	0	371	0	0
T41	0	371	0	0
T42	0	371	0	0
T43	0	371	0	0
T44	0	371	0	0
T45	0	371	0	0
T46	0	371	0	0
T47	252231	0	0	0
T48	450583	0	0	0
T49	450583	0	0	0
T50	4273	0	0	0
T51	821217	0	0	0
T52	450583	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	124600	0	755
T2	272352	46	0	1
T3	272352	46	0	1
T4	450583	340	0	1
T5	450583	340	0	1
T6	450583	340	0	1
T8	837725	46	0	1
T9	252231	46	0	1
T10	252231	46	0	1
T11	357921	194	0	1
T12	252231	46	0	1

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	215400	0	0
T2	272352	92	0	0
T3	272352	92	0	0
T4	450583	587	0	0
T5	450583	587	0	0
T6	450583	587	0	0
T8	837725	77	0	0
T9	252231	77	0	0
T10	252231	77	0	0
T11	357921	338	0	0
T12	252231	77	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	33715700	0	0
T2	272352	36794	0	0
T3	272352	36794	0	0
T4	450583	45447	0	0
T5	450583	45447	0	0
T6	450583	45447	0	0
T8	837725	26149	0	0
T9	252231	18458	0	0
T10	252231	18458	0	0
T11	357921	53472	0	0
T12	252231	18458	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3743050	0	0
T2	272352	10	0	0
T3	272352	10	0	0
T4	450583	0	0	0
T5	450583	0	0	0
T6	450583	0	0	0
T7	0	74851	0	0
T8	837725	0	0	0
T9	252231	0	0	0
T10	252231	0	0	0
T11	357921	0	0	0
T12	252231	0	0	0
T34	0	74851	0	0
T35	0	74851	0	0
T36	0	10	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	74851	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	42458850	0	0
T2	272352	50921	0	0
T3	272352	50921	0	0
T4	450583	59125	0	0
T5	450583	59125	0	0
T6	450583	59125	0	0
T8	837725	36183	0	0
T9	252231	18570	0	0
T10	252231	18570	0	0
T11	357921	74091	0	0
T12	252231	18570	0	0

Line Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	156	4	4	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	9	9	100.00
ALWAYS	213	8	8	100.00
ALWAYS	234	3	3	100.00
ALWAYS	242	14	14	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	290	0	0
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	298	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
			Exclude Annotation: VC_COV_UNR
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
164	1	1
165	1	1
169	1	1
170	1	1
173	1	1
174	1	1
177	1	1
179	1	1
184	1	1
186	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
234	1	1
235	1	1
237	1	1
242	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
257	1	1
258	1	1
260	1	1
261	1	1
263	1	1
265	1	1
266	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
278	1	1
282	1	1
290		unreachable
293	1	1
294	1	1
295	1	1
298		unreachable

---

Cond Coverage for Instance : tb.dut.u_packer

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------
 Exclude Annotation: [UNR] cannot have (ack_in & ack_out) = 1

-1-	Status	Tests
0	Unreachable	T7,T34,T35
1	Excluded

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T2,T3,T7
1	1	Covered	T2,T3,T4

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T4

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	169	2	2	100.00
TERNARY	170	2	2	100.00
TERNARY	282	1	1	100.00
IF	158	2	2	100.00
CASE	184	4	4	100.00
IF	213	3	3	100.00
IF	234	2	2	100.00
CASE	247	4	4	100.00
CASE	80	3	3	100.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests	Exclude Annotation
2'b00	Covered	T1,T2,T3
2'b01	Covered	T2,T3,T4
2'b10	Covered	T2,T3,T4
2'b11	Covered	T7,T34,T35
default	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
FlushIdle	1	-	Covered	T2,T3,T4
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T2,T3,T4
FlushSend	-	0	Covered	T2,T3,T4
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T2,T3,T4
2'b01	0	-	Unreachable	T2,T3,T4
2'b10	-	-	Covered	T2,T3,T4
2'b11	-	1	Excluded		[UNR] cannot have (ack_in & ack_out) = 1
2'b11	-	0	Unreachable	T7,T34,T35
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	1665129060	3702100	0	755
DataOStableWhenPending_A	1665129060	3743050	0	755
ExFlushValid_M	1665129060	124600	0	0
ExcessiveDataStored_A	1665129060	18550	0	0
ExcessiveMaskStored_A	1665129060	18550	0	0
FlushFollowedByDone_A	1665129060	124600	0	755
ValidIDeassertedOnFlush_M	1665129060	215400	0	0
ValidOAssertedForStoredDataGTEOutW_A	1665129060	33715700	0	0
ValidOPairedWidthReadyI_A	1665129060	3743050	0	0
gen_mask_assert.ContiguousOnesMask_M	1665129060	42458850	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3702100	0	755
T2	272352	9	0	1
T3	272352	9	0	1
T4	450583	0	0	1
T5	450583	0	0	1
T6	450583	0	0	1
T7	0	74033	0	0
T8	837725	0	0	1
T9	252231	0	0	1
T10	252231	0	0	1
T11	357921	0	0	1
T12	252231	0	0	1
T34	0	74033	0	0
T35	0	74033	0	0
T36	0	9	0	0
T37	0	9	0	0
T38	0	9	0	0
T39	0	9	0	0
T40	0	74033	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3743050	0	755
T2	272352	10	0	1
T3	272352	10	0	1
T4	450583	0	0	1
T5	450583	0	0	1
T6	450583	0	0	1
T7	0	74851	0	0
T8	837725	0	0	1
T9	252231	0	0	1
T10	252231	0	0	1
T11	357921	0	0	1
T12	252231	0	0	1
T34	0	74851	0	0
T35	0	74851	0	0
T36	0	10	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	74851	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	124600	0	0
T2	272352	46	0	0
T3	272352	46	0	0
T4	450583	340	0	0
T5	450583	340	0	0
T6	450583	340	0	0
T8	837725	46	0	0
T9	252231	46	0	0
T10	252231	46	0	0
T11	357921	194	0	0
T12	252231	46	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	18550	0	0
T7	145162	371	0	0
T34	145162	371	0	0
T35	0	371	0	0
T36	272352	0	0	0
T37	272352	0	0	0
T40	0	371	0	0
T41	0	371	0	0
T42	0	371	0	0
T43	0	371	0	0
T44	0	371	0	0
T45	0	371	0	0
T46	0	371	0	0
T47	252231	0	0	0
T48	450583	0	0	0
T49	450583	0	0	0
T50	4273	0	0	0
T51	821217	0	0	0
T52	450583	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	18550	0	0
T7	145162	371	0	0
T34	145162	371	0	0
T35	0	371	0	0
T36	272352	0	0	0
T37	272352	0	0	0
T40	0	371	0	0
T41	0	371	0	0
T42	0	371	0	0
T43	0	371	0	0
T44	0	371	0	0
T45	0	371	0	0
T46	0	371	0	0
T47	252231	0	0	0
T48	450583	0	0	0
T49	450583	0	0	0
T50	4273	0	0	0
T51	821217	0	0	0
T52	450583	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	124600	0	755
T2	272352	46	0	1
T3	272352	46	0	1
T4	450583	340	0	1
T5	450583	340	0	1
T6	450583	340	0	1
T8	837725	46	0	1
T9	252231	46	0	1
T10	252231	46	0	1
T11	357921	194	0	1
T12	252231	46	0	1

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	215400	0	0
T2	272352	92	0	0
T3	272352	92	0	0
T4	450583	587	0	0
T5	450583	587	0	0
T6	450583	587	0	0
T8	837725	77	0	0
T9	252231	77	0	0
T10	252231	77	0	0
T11	357921	338	0	0
T12	252231	77	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	33715700	0	0
T2	272352	36794	0	0
T3	272352	36794	0	0
T4	450583	45447	0	0
T5	450583	45447	0	0
T6	450583	45447	0	0
T8	837725	26149	0	0
T9	252231	18458	0	0
T10	252231	18458	0	0
T11	357921	53472	0	0
T12	252231	18458	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	3743050	0	0
T2	272352	10	0	0
T3	272352	10	0	0
T4	450583	0	0	0
T5	450583	0	0	0
T6	450583	0	0	0
T7	0	74851	0	0
T8	837725	0	0	0
T9	252231	0	0	0
T10	252231	0	0	0
T11	357921	0	0	0
T12	252231	0	0	0
T34	0	74851	0	0
T35	0	74851	0	0
T36	0	10	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	74851	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665129060	42458850	0	0
T2	272352	50921	0	0
T3	272352	50921	0	0
T4	450583	59125	0	0
T5	450583	59125	0	0
T6	450583	59125	0	0
T8	837725	36183	0	0
T9	252231	18570	0	0
T10	252231	18570	0	0
T11	357921	74091	0	0
T12	252231	18570	0	0