Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	100.00	91.01		100.00	92.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	100.00	100.00	100.00		100.00	100.00

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		98	98	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	141	6	6	100.00
ALWAYS	152	6	6	100.00
ALWAYS	162	4	4	100.00
ALWAYS	170	6	6	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	182	3	3	100.00
ALWAYS	187	59	59	100.00
CONT_ASSIGN	314	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
106	1	1
107	1	1
108	1	1
110	1	1
112	1	1
113	1	1
116	1	1
118	1	1
119	1	1
126	1	1
131	1	1
133	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
			MISSING_ELSE
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
			==> MISSING_ELSE
179	1	1
182	2	2
183	1	1
187	1	1
188	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
200	1	1
202	1	1
203	1	1
205	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
215	1	1
220	1	1
222	1	1
223	1	1
225	1	1
227	1	1
229	1	1
234	1	1
235	1	1
237	1	1
239	1	1
241	1	1
242	1	1
244	1	1
246	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
266	1	1
267	1	1
268	1	1
270	1	1
271	1	1
273	1	1
274	1	1
275	1	1
276	1	1
278	1	1
284	1	1
285	1	1
287	1	1
288	1	1
290	1	1
292	1	1
294	1	1
300	1	1
302	1	1
314	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	89	81	91.01
Logical	89	81	91.01
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       108
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       116
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       116
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       116
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : ((sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       119
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? message_length : ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       126
 SUB-EXPRESSION ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0))
                 -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION (sel_msglen == SelIPadMsg)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)
                 -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION (sel_msglen == SelOPadMsg)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (txcount[BlockSizeBits:0] == BlockSizeBSB)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       133
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       156
 EXPRESSION (hmac_hash_done || reg_hash_start)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       174
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       179
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       254
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       270
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
             -----1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       270
 SUB-EXPRESSION (fifo_wdata_sel == 3'h7)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       314
 EXPRESSION ((st_q == StIdle) && ((!reg_hash_start)))
             --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       314
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	255	Covered	T13
StIPad	208	Covered	T13
StIdle	215	Covered	T13
StMsg	223	Covered	T13
StOPad	271	Covered	T13
StPushToMsgFifo	257	Covered	T13
StWaitResp	239	Covered	T13

transitions	Line No.	Covered	Tests
StDone->StIdle	300	Covered	T13
StIPad->StMsg	223	Covered	T13
StIdle->StIPad	208	Covered	T13
StMsg->StWaitResp	239	Covered	T13
StOPad->StMsg	288	Covered	T13
StPushToMsgFifo->StOPad	271	Covered	T13
StWaitResp->StDone	255	Covered	T13
StWaitResp->StPushToMsgFifo	257	Covered	T13

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		53	49	92.45
TERNARY	106	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	108	2	2	100.00
TERNARY	116	2	2	100.00
TERNARY	118	2	2	100.00
TERNARY	119	5	4	80.00
TERNARY	126	4	3	75.00
TERNARY	179	2	2	100.00
IF	141	4	4	100.00
IF	152	4	4	100.00
IF	162	3	3	100.00
IF	170	4	3	75.00
IF	182	2	2	100.00
CASE	205	15	14	93.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	107	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	108	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	118	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	119	((!hmac_en)) ? 
-2-:	119	((sel_rdata == SelIPad)) ? 
-3-:	119	((sel_rdata == SelOPad)) ? 
-4-:	119	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T4
0	0	1	-	Covered	T2,T3,T4
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	126	((!hmac_en)) ? 
-2-:	126	((sel_msglen == SelIPadMsg)) ? 
-3-:	126	((sel_msglen == SelOPadMsg)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	179	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	143	if (clr_txcount)
-3-:	145	if (inc_txcount)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (reg_hash_process)
-3-:	156	if ((hmac_hash_done || reg_hash_start))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	if ((!rst_ni))
-2-:	164	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (clr_fifo_wdata_sel)
-3-:	174	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	182	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	case (st_q)
-2-:	207	if ((hmac_en && reg_hash_start))
-3-:	222	if (txcnt_eq_blksz)
-4-:	237	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-5-:	253	if (sha_hash_done)
-6-:	254	if ((round_q == Outer))
-7-:	270	if ((fifo_wready && (fifo_wdata_sel == 3'h7)))
-8-:	287	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	Covered	T2,T3,T4
StIPad	-	0	-	-	-	-	-	Covered	T2,T3,T4
StMsg	-	-	1	-	-	-	-	Covered	T2,T3,T4
StMsg	-	-	0	-	-	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	1	1	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	1	0	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	0	-	-	-	Covered	T2,T3,T4
StPushToMsgFifo	-	-	-	-	-	1	-	Covered	T2,T3,T4
StPushToMsgFifo	-	-	-	-	-	0	-	Covered	T2,T3,T4
StOPad	-	-	-	-	-	-	1	Covered	T2,T3,T4
StOPad	-	-	-	-	-	-	0	Covered	T2,T3,T4
StDone	-	-	-	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
TOTAL		98	98	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	141	6	6	100.00
ALWAYS	152	6	6	100.00
ALWAYS	162	4	4	100.00
ALWAYS	170	6	6	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	182	3	3	100.00
ALWAYS	187	59	59	100.00
CONT_ASSIGN	314	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
106	1	1
107	1	1
108	1	1
110	1	1
112	1	1
113	1	1
116	1	1
118	1	1
119	1	1
126	1	1
131	1	1
133	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
			MISSING_ELSE
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
			==> MISSING_ELSE
179	1	1
182	2	2
183	1	1
187	1	1
188	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
200	1	1
202	1	1
203	1	1
205	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
215	1	1
220	1	1
222	1	1
223	1	1
225	1	1
227	1	1
229	1	1
234	1	1
235	1	1
237	1	1
239	1	1
241	1	1
242	1	1
244	1	1
246	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
266	1	1
267	1	1
268	1	1
270	1	1
271	1	1
273	1	1
274	1	1
275	1	1
276	1	1
278	1	1
284	1	1
285	1	1
287	1	1
288	1	1
290	1	1
292	1	1
294	1	1
300	1	1
302	1	1
			Exclude Annotation: VC_COV_UNR
314	1	1

---

Cond Coverage for Instance : tb.dut.u_hmac

	Total	Covered	Percent
Conditions	75	75	100.00
Logical	75	75	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       107
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       108
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       116
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       116
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       116
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : ((sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       119
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelIPad) ? ('{data:i_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION 
 Number  Term
      1  (sel_rdata == SelOPad) ? ('{data:o_pad[((BlockSize - 1) - (32 * pad_index))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       119
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? message_length : ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       126
 SUB-EXPRESSION ((sel_msglen == SelIPadMsg) ? ((message_length + BlockSize64)) : ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0))
                 -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION (sel_msglen == SelIPadMsg)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION ((sel_msglen == SelOPadMsg) ? ((BlockSize64 + 64'h0000000000000100)) : '0)
                 -------------1------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       126
 SUB-EXPRESSION (sel_msglen == SelOPadMsg)
                -------------1------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (txcount[BlockSizeBits:0] == BlockSizeBSB)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       133
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----
 Exclude Annotation: [UNR] sha_rready=1 requires sha_rvalid=1.

-1-	-2-	Status	Tests
0	1	Excluded	T2,T3,T4
1	0	Excluded
1	1	Excluded	T2,T3,T4

 LINE       156
 EXPRESSION (hmac_hash_done || reg_hash_start)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       174
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       179
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       237
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       254
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       270
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
             -----1-----    ------------2-----------
 Exclude Annotation: [UNR] tl_adapter with outstanding=1 drains fifo faster than it pushes. So it cannot have fifo full condition

 LINE       270
 EXPRESSION (fifo_wready && (fifo_wdata_sel == 3'h7))
 Exclude Annotation: [UNR] tl_adapter with outstanding=1 drains fifo faster than it pushes. So it cannot have fifo full condition

-1-	-2-	Status	Tests
0	1	Excluded
1	0	Excluded	T2,T3,T4
1	1	Excluded	T2,T3,T4

 LINE       270
 SUB-EXPRESSION (fifo_wdata_sel == 3'h7)
                ------------1-----------

-1-	Status	Tests
0	Excluded	T2,T3,T4
1	Excluded	T2,T3,T4

 LINE       314
 EXPRESSION ((st_q == StIdle) && ((!reg_hash_start)))
             --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       314
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_hmac

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	255	Covered	T13
StIPad	208	Covered	T13
StIdle	215	Covered	T13
StMsg	223	Covered	T13
StOPad	271	Covered	T13
StPushToMsgFifo	257	Covered	T13
StWaitResp	239	Covered	T13

transitions	Line No.	Covered	Tests
StDone->StIdle	300	Covered	T13
StIPad->StMsg	223	Covered	T13
StIdle->StIPad	208	Covered	T13
StMsg->StWaitResp	239	Covered	T13
StOPad->StMsg	288	Covered	T13
StPushToMsgFifo->StOPad	271	Covered	T13
StWaitResp->StDone	255	Covered	T13
StWaitResp->StPushToMsgFifo	257	Covered	T13

---

Branch Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
Branches		49	49	100.00
TERNARY	106	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	108	2	2	100.00
TERNARY	116	2	2	100.00
TERNARY	118	2	2	100.00
TERNARY	119	4	4	100.00
TERNARY	126	3	3	100.00
TERNARY	179	2	2	100.00
IF	141	4	4	100.00
IF	152	4	4	100.00
IF	162	3	3	100.00
IF	170	3	3	100.00
IF	182	2	2	100.00
CASE	205	14	14	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	107	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	108	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	118	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	119	((!hmac_en)) ? 
-2-:	119	((sel_rdata == SelIPad)) ? 
-3-:	119	((sel_rdata == SelOPad)) ? 
-4-:	119	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T4
0	0	1	-	Covered	T2,T3,T4
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	126	((!hmac_en)) ? 
-2-:	126	((sel_msglen == SelIPadMsg)) ? 
-3-:	126	((sel_msglen == SelOPadMsg)) ? 

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	179	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	143	if (clr_txcount)
-3-:	145	if (inc_txcount)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (reg_hash_process)
-3-:	156	if ((hmac_hash_done || reg_hash_start))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	if ((!rst_ni))
-2-:	164	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (clr_fifo_wdata_sel)
-3-:	174	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	182	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	case (st_q)
-2-:	207	if ((hmac_en && reg_hash_start))
-3-:	222	if (txcnt_eq_blksz)
-4-:	237	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-5-:	253	if (sha_hash_done)
-6-:	254	if ((round_q == Outer))
-7-:	270	if ((fifo_wready && (fifo_wdata_sel == 3'h7)))
-8-:	287	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
StIdle	1	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	Covered	T2,T3,T4
StIPad	-	0	-	-	-	-	-	Covered	T2,T3,T4
StMsg	-	-	1	-	-	-	-	Covered	T2,T3,T4
StMsg	-	-	0	-	-	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	1	1	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	1	0	-	-	Covered	T2,T3,T4
StWaitResp	-	-	-	0	-	-	-	Covered	T2,T3,T4
StPushToMsgFifo	-	-	-	-	-	1	-	Covered	T2,T3,T4
StPushToMsgFifo	-	-	-	-	-	0	-	Covered	T2,T3,T4
StOPad	-	-	-	-	-	-	1	Covered	T2,T3,T4
StOPad	-	-	-	-	-	-	0	Covered	T2,T3,T4
StDone	-	-	-	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR