Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116655922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

131307756

1

T12

9

T13

329

T14

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	98008387	1			T12	11		T13	117		T14	27
values[0x0]	69629561	1			T12	4		T13	125		T14	32
values[0x1]	80325730	1			T12	7		T13	149		T14	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	85227373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162736305

1

T12

10

T13

364

T14

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	911378	1			T18	4		T64	3		T71	1
valid_sources[0x01]	958682	1			T15	13		T18	5		T64	2
valid_sources[0x02]	925130	1			T18	4		T20	4		T48	1
valid_sources[0x03]	945505	1			T18	5		T19	1		T20	12
valid_sources[0x04]	922783	1			T13	2		T18	5		T20	26
valid_sources[0x05]	909137	1			T18	10		T20	26		T71	5
valid_sources[0x06]	945796	1			T13	6		T18	7		T19	1
valid_sources[0x07]	917557	1			T18	4		T20	8		T48	1
valid_sources[0x08]	1344162	1			T18	9		T19	1		T20	2
valid_sources[0x09]	910072	1			T18	12		T20	2		T71	2
valid_sources[0x0a]	938743	1			T17	3		T18	14		T20	79
valid_sources[0x0b]	895307	1			T13	2		T18	4		T20	4
valid_sources[0x0c]	996218	1			T18	11		T23	1		T71	4
valid_sources[0x0d]	895817	1			T18	5		T20	1		T64	3
valid_sources[0x0e]	917369	1			T13	5		T17	2		T18	7
valid_sources[0x0f]	923372	1			T18	8		T20	20		T21	11
valid_sources[0x10]	920906	1			T18	4		T19	1		T20	92
valid_sources[0x11]	994444	1			T13	1		T18	14		T20	11
valid_sources[0x12]	913316	1			T17	3		T18	2		T20	32
valid_sources[0x13]	928177	1			T14	3		T18	3		T93	2
valid_sources[0x14]	933162	1			T17	1		T18	4		T20	17
valid_sources[0x15]	929200	1			T13	2		T19	1		T72	2
valid_sources[0x16]	1026244	1			T13	8		T18	3		T20	24
valid_sources[0x17]	947862	1			T18	4		T20	8		T22	2
valid_sources[0x18]	965545	1			T18	6		T20	11		T71	1
valid_sources[0x19]	978679	1			T13	1		T17	1		T18	5
valid_sources[0x1a]	932185	1			T18	11		T20	20		T23	1
valid_sources[0x1b]	1228825	1			T13	3		T17	2		T18	8
valid_sources[0x1c]	1263727	1			T13	1		T18	11		T20	19
valid_sources[0x1d]	932382	1			T18	6		T19	1		T71	1
valid_sources[0x1e]	1344078	1			T13	2		T18	7		T20	2
valid_sources[0x1f]	936558	1			T18	10		T20	49		T64	10
valid_sources[0x20]	929519	1			T13	1		T14	14		T16	52
valid_sources[0x21]	897041	1			T13	1		T16	23		T18	5
valid_sources[0x22]	949829	1			T18	11		T20	5		T64	2
valid_sources[0x23]	958795	1			T13	2		T14	12		T18	4
valid_sources[0x24]	949213	1			T18	7		T19	2		T20	60
valid_sources[0x25]	910909	1			T18	11		T47	1		T74	1
valid_sources[0x26]	895415	1			T13	5		T18	12		T48	1
valid_sources[0x27]	907100	1			T18	6		T23	2		T64	11
valid_sources[0x28]	938712	1			T13	1		T17	2		T18	13
valid_sources[0x29]	928919	1			T18	5		T20	4		T23	1
valid_sources[0x2a]	939953	1			T13	3		T18	9		T20	5
valid_sources[0x2b]	899128	1			T18	9		T23	1		T64	2
valid_sources[0x2c]	916249	1			T18	4		T20	13		T23	1
valid_sources[0x2d]	917295	1			T18	6		T20	47		T71	4
valid_sources[0x2e]	1182209	1			T13	3		T17	1		T18	2
valid_sources[0x2f]	907650	1			T13	3		T18	6		T20	12
valid_sources[0x30]	926493	1			T18	6		T23	2		T71	1
valid_sources[0x31]	1273181	1			T17	2		T18	8		T21	3
valid_sources[0x32]	982393	1			T17	1		T18	1		T71	5
valid_sources[0x33]	906250	1			T18	7		T20	15		T23	2
valid_sources[0x34]	912865	1			T17	1		T18	7		T23	1
valid_sources[0x35]	925852	1			T16	15		T18	9		T20	9
valid_sources[0x36]	934944	1			T13	3		T18	5		T19	1
valid_sources[0x37]	896981	1			T18	12		T19	1		T20	58
valid_sources[0x38]	910615	1			T13	1		T18	4		T20	3
valid_sources[0x39]	921043	1			T13	1		T18	4		T20	12
valid_sources[0x3a]	872569	1			T13	3		T18	3		T20	6
valid_sources[0x3b]	921918	1			T18	11		T64	4		T71	8
valid_sources[0x3c]	956414	1			T13	4		T18	8		T20	27
valid_sources[0x3d]	913302	1			T18	4		T23	1		T71	7
valid_sources[0x3e]	899684	1			T13	1		T14	13		T17	1
valid_sources[0x3f]	899361	1			T17	1		T18	3		T19	1
valid_sources[0x40]	914001	1			T18	4		T20	6		T72	1
valid_sources[0x41]	885460	1			T13	2		T17	2		T18	8
valid_sources[0x42]	899531	1			T18	15		T19	1		T20	17
valid_sources[0x43]	964272	1			T13	5		T17	2		T18	7
valid_sources[0x44]	899242	1			T13	5		T18	8		T20	24
valid_sources[0x45]	937746	1			T13	4		T18	8		T20	17
valid_sources[0x46]	1109096	1			T17	3		T18	2		T19	2
valid_sources[0x47]	1145043	1			T13	5		T17	1		T18	6
valid_sources[0x48]	901191	1			T13	9		T18	12		T20	1
valid_sources[0x49]	939233	1			T14	10		T18	3		T19	1
valid_sources[0x4a]	965540	1			T13	7		T18	11		T19	2
valid_sources[0x4b]	883960	1			T13	3		T17	1		T18	4
valid_sources[0x4c]	901605	1			T13	4		T16	28		T18	11
valid_sources[0x4d]	906763	1			T13	1		T17	1		T18	5
valid_sources[0x4e]	1357365	1			T13	5		T18	13		T19	1
valid_sources[0x4f]	926109	1			T18	5		T20	23		T71	13
valid_sources[0x50]	1315472	1			T17	1		T18	9		T20	4
valid_sources[0x51]	913093	1			T18	5		T64	10		T48	1
valid_sources[0x52]	1070329	1			T17	1		T18	9		T20	7
valid_sources[0x53]	907182	1			T17	1		T18	9		T20	52
valid_sources[0x54]	855301	1			T13	3		T18	15		T19	1
valid_sources[0x55]	897215	1			T13	1		T18	11		T19	1
valid_sources[0x56]	961307	1			T18	9		T20	6		T23	2
valid_sources[0x57]	2114792	1			T18	4		T21	116		T23	1
valid_sources[0x58]	906774	1			T13	4		T17	1		T18	5
valid_sources[0x59]	908874	1			T17	1		T18	5		T20	49
valid_sources[0x5a]	920939	1			T17	1		T18	10		T22	30
valid_sources[0x5b]	1301526	1			T13	2		T18	6		T20	22
valid_sources[0x5c]	902344	1			T17	1		T18	7		T19	1
valid_sources[0x5d]	1249474	1			T17	1		T18	3		T64	17
valid_sources[0x5e]	925866	1			T13	3		T17	1		T18	10
valid_sources[0x5f]	914299	1			T13	1		T17	1		T18	3
valid_sources[0x60]	967797	1			T18	9		T72	1		T25	1
valid_sources[0x61]	914725	1			T13	8		T18	8		T23	1
valid_sources[0x62]	961007	1			T13	1		T18	8		T21	28
valid_sources[0x63]	1209606	1			T18	5		T19	1		T20	8
valid_sources[0x64]	894184	1			T13	1		T17	1		T18	15
valid_sources[0x65]	920451	1			T13	3		T17	1		T18	11
valid_sources[0x66]	1015468	1			T17	1		T18	5		T20	7
valid_sources[0x67]	912943	1			T13	4		T14	16		T18	9
valid_sources[0x68]	893346	1			T13	1		T17	1		T18	2
valid_sources[0x69]	916072	1			T17	2		T18	4		T20	14
valid_sources[0x6a]	928536	1			T18	11		T20	42		T71	7
valid_sources[0x6b]	906354	1			T18	6		T19	1		T20	16
valid_sources[0x6c]	940653	1			T17	1		T18	6		T19	1
valid_sources[0x6d]	929553	1			T17	1		T18	8		T20	5
valid_sources[0x6e]	959605	1			T17	2		T18	2		T64	14
valid_sources[0x6f]	908130	1			T14	15		T18	2		T23	1
valid_sources[0x70]	982905	1			T18	2		T20	5		T64	25
valid_sources[0x71]	919014	1			T13	1		T18	4		T64	1
valid_sources[0x72]	917329	1			T13	5		T18	4		T20	14
valid_sources[0x73]	924117	1			T18	3		T20	4		T23	1
valid_sources[0x74]	908741	1			T17	1		T18	15		T25	3
valid_sources[0x75]	972746	1			T13	5		T18	2		T19	1
valid_sources[0x76]	924405	1			T13	16		T18	1		T20	35
valid_sources[0x77]	945378	1			T13	1		T18	5		T23	3
valid_sources[0x78]	941895	1			T13	2		T18	4		T20	3
valid_sources[0x79]	1311130	1			T13	2		T18	3		T19	2
valid_sources[0x7a]	935156	1			T13	5		T17	1		T18	8
valid_sources[0x7b]	1679018	1			T18	3		T20	6		T23	2
valid_sources[0x7c]	1195801	1			T18	4		T19	2		T71	5
valid_sources[0x7d]	862690	1			T17	2		T18	2		T20	31
valid_sources[0x7e]	919181	1			T13	3		T18	3		T71	2
valid_sources[0x7f]	955016	1			T17	1		T18	5		T71	3
valid_sources[0x80]	915510	1			T13	5		T18	2		T71	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47253057

1

T12

6

T13

83

T14

16

values[0x0]

all_enables

biggest_size

43768468

1

T12

1

T13

120

T14

19

values[0x1]

all_enables

biggest_size

40286231

1

T12

2

T13

126

T14

13