Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

174080489

1

T12

13

T13

623

T14

61

full_word

135645516

1

T12

9

T13

372

T14

48

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	309725595	1			T12	22		T13	995		T14	109
auto[TlIntgErrCmd]	125	1			T18	10		T21	3		T63	4
auto[TlIntgErrData]	133	1			T18	9		T63	4		T70	11
auto[TlIntgErrBoth]	152	1			T18	11		T21	7		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120721052

1

T12

11

T13

362

T14

27

auto[1]

189004953

1

T12

11

T13

633

T14

82

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	71739859	1			T12	5		T13	257		T14	11
auto[TlIntgErrNone]	partial	auto[1]	102340251	1			T12	8		T13	366		T14	50
auto[TlIntgErrNone]	full_word	auto[0]	48981008	1			T12	6		T13	105		T14	16
auto[TlIntgErrNone]	full_word	auto[1]	86664477	1			T12	3		T13	267		T14	32
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T18	5		T21	3		T70	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T18	2		T63	4		T70	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T70	1		T102	2		T105	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T18	3		T102	2		T67	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T18	7		T63	2		T70	5
auto[TlIntgErrData]	partial	auto[1]	64	1			T18	1		T63	1		T70	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T18	1		T78	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T63	1		T70	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T18	2		T21	3		T70	6
auto[TlIntgErrBoth]	partial	auto[1]	84	1			T18	9		T21	4		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T107	2		T108	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T70	1		T67	1		T109	1