9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 4.610s | 1.738ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.690s | 35.829us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.760s | 26.310us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 6.800s | 7.219ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 2.360s | 189.871us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.089m | 59.853ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.760s | 26.310us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 2.360s | 189.871us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | long_msg | hmac_long_msg | 1.883m | 20.175ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 58.080s | 13.987ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 8.296m | 48.496ms | 44 | 50 | 88.00 |
| hmac_test_hmac_vectors | 1.240s | 62.829us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.027m | 1.326ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.264m | 2.735ms | 49 | 50 | 98.00 |
| V2 | error | hmac_error | 3.991m | 21.915ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.276m | 12.554ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 30.743m | 119.422ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.620s | 23.896us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.630s | 13.102us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.030s | 242.005us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.030s | 242.005us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.690s | 35.829us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.760s | 26.310us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 2.360s | 189.871us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 1.430s | 80.868us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.690s | 35.829us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.760s | 26.310us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 2.360s | 189.871us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 1.430s | 80.868us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 583 | 590 | 98.81 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.980s | 838.553us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 2.540s | 181.114us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 2.540s | 181.114us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 4.610s | 1.738ms | 49 | 50 | 98.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 2.103h | 1.010s | 191 | 200 | 95.50 |
| V3 | TOTAL | 191 | 200 | 95.50 | |||
| TOTAL | 903 | 920 | 98.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 13 | 13 | 11 | 84.62 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.53 | 98.58 | 100.00 | 100.00 | 99.76 | 99.49 | 100.00 |
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:
0.hmac_stress_all_with_rand_reset.63077269820838362389909428796715309347130164308757506135881797725797836967514
Line 343, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10737906076 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10737906076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
63.hmac_stress_all_with_rand_reset.28831368722992140276390127857018810349531822727728133892941408046637641025724
Line 1352, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/63.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1704893888303 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1704893888303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
Test hmac_test_sha_vectors has 2 failures.
15.hmac_test_sha_vectors.61997815021460722363207896772284443621423371002566453565554264314843288712393
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_test_sha_vectors/latest/run.log
[make]: simulate
cd /workspace/15.hmac_test_sha_vectors/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27145417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.27145417
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
49.hmac_test_sha_vectors.97365630883846398196259342590962985606793470498037041818978052499567923441394
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_test_sha_vectors/latest/run.log
[make]: simulate
cd /workspace/49.hmac_test_sha_vectors/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644337906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.3644337906
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test hmac_datapath_stress has 1 failures.
16.hmac_datapath_stress.89947784970306345571928247424408930687393252439489991165121208819611158771525
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_datapath_stress/latest/run.log
[make]: simulate
cd /workspace/16.hmac_datapath_stress/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000666949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1000666949
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test hmac_smoke has 1 failures.
20.hmac_smoke.112142197045188767990504610054430572930430155235787495078573004403323876825784
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_smoke/latest/run.log
[make]: simulate
cd /workspace/20.hmac_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182503096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2182503096
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test hmac_stress_all_with_rand_reset has 1 failures.
195.hmac_stress_all_with_rand_reset.37958124400986442738524850320668535636793985597747457146131370650660719876351
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/195.hmac_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/195.hmac_stress_all_with_rand_reset/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677697791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.677697791
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
6.hmac_test_sha_vectors.5557348565544518997609707775478513469851401554113581351070956333330734045695
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.hmac_test_sha_vectors.111906413137949470407557930203264273097170429803652823782803801001426392557645
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
27.hmac_stress_all_with_rand_reset.62828897863630937266357132778464617368749488375047471969803634316599888693194
Line 879, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 121688086151 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 121688086151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
107.hmac_stress_all_with_rand_reset.91129158271702554926480576056160772585689156968558913888645007212264683735206
Line 391, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/107.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96774508205 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 96774508205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
146.hmac_stress_all_with_rand_reset.67126181426102540755381618298106314696688493100672715537765601042468015515836
Line 832, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/146.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 140577355645 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 140577355645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---