Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	42693217	1			T16	8		T19	4		T20	1
all_values[1]	42693217	1			T16	8		T19	4		T20	1
all_values[2]	42693217	1			T16	8		T19	4		T20	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132875

1

T16

12

T19

6

T20

3

auto[1]

127946776

1

T16

12

T19

6

T21

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92991937

1

T16

14

T19

9

T20

3

auto[1]

35087714

1

T16

10

T19

3

T21

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	51907	1			T16	3		T20	1		T22	2
all_values[0]	auto[0]	auto[1]	1313	1			T19	1		T126	3		T127	2
all_values[0]	auto[1]	auto[0]	42462439	1			T16	5		T19	2		T21	2
all_values[0]	auto[1]	auto[1]	177558	1			T19	1		T21	3		T22	2
all_values[1]	auto[0]	auto[0]	21189	1			T16	3		T19	2		T20	1
all_values[1]	auto[0]	auto[1]	18188	1			T16	1		T19	1		T21	2
all_values[1]	auto[1]	auto[0]	24326590	1			T16	1		T19	1		T21	1
all_values[1]	auto[1]	auto[1]	18327250	1			T16	3		T22	2		T24	1
all_values[2]	auto[0]	auto[0]	28768	1			T16	2		T19	2		T20	1
all_values[2]	auto[0]	auto[1]	11510	1			T16	3		T21	1		T22	1
all_values[2]	auto[1]	auto[0]	26101044	1			T19	2		T21	1		T24	2
all_values[2]	auto[1]	auto[1]	16551895	1			T16	3		T21	3		T22	3