Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.53 98.47 100.00 100.00 99.76 99.49 99.86


Total tests in report: 913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
48.77 48.77 39.53 39.53 32.90 32.90 56.78 56.78 100.00 100.00 25.41 25.41 80.05 80.05 6.74 6.74 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.400827580
83.85 35.07 97.67 58.13 78.91 46.01 61.31 4.52 100.00 0.00 94.35 68.94 94.44 14.39 60.25 53.51 /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.313339890
94.42 10.57 99.38 1.71 96.07 17.16 90.20 28.89 100.00 0.00 99.06 4.71 96.46 2.02 79.78 19.53 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1200437638
96.49 2.07 99.38 0.00 97.38 1.31 96.23 6.03 100.00 0.00 99.06 0.00 96.46 0.00 86.93 7.15 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3794274483
97.28 0.79 99.53 0.16 97.81 0.44 98.24 2.01 100.00 0.00 99.53 0.47 96.46 0.00 89.41 2.48 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.548579224
97.85 0.56 99.53 0.00 98.03 0.22 98.24 0.00 100.00 0.00 99.53 0.00 96.46 0.00 93.12 3.71 /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1240035848
98.28 0.43 99.53 0.00 98.03 0.00 99.50 1.26 100.00 0.00 99.53 0.00 98.23 1.77 93.12 0.00 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1539082256
98.51 0.24 99.53 0.00 98.03 0.00 99.50 0.00 100.00 0.00 99.53 0.00 98.23 0.00 94.77 1.65 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4191274167
98.69 0.18 99.53 0.00 98.25 0.22 100.00 0.50 100.00 0.00 99.53 0.00 98.48 0.25 95.05 0.28 /workspace/coverage/default/1.hmac_sec_cm.472566452
98.87 0.18 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 96.29 1.24 /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3189543021
99.01 0.14 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 97.25 0.96 /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1209403865
99.09 0.08 99.53 0.00 98.25 0.00 100.00 0.00 100.00 0.00 99.53 0.00 98.48 0.00 97.80 0.55 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3415581434
99.15 0.06 99.53 0.00 98.47 0.22 100.00 0.00 100.00 0.00 99.76 0.24 98.48 0.00 97.80 0.00 /workspace/coverage/default/29.hmac_alert_test.1068219198
99.21 0.06 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 98.21 0.41 /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.3054126541
99.27 0.06 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 98.62 0.41 /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.4119254121
99.33 0.06 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.04 0.41 /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.527770241
99.35 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.17 0.14 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1036494367
99.37 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3769825305
99.39 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2904325983
99.41 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.492766242
99.43 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.110605849
99.45 0.02 99.53 0.00 98.47 0.00 100.00 0.00 100.00 0.00 99.76 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.3075977029

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1658181585
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4186468662
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3807990994
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1335560986
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.3687530
/workspace/coverage/cover_reg_top/0.hmac_intr_test.1399741181
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2290331776
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.673910728
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3209409245
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.481536597
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.21451432
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1249495960
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.4018783975
/workspace/coverage/cover_reg_top/1.hmac_intr_test.1360299994
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.543124341
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.331978999
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.302111453
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.308081342
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.2557173080
/workspace/coverage/cover_reg_top/10.hmac_intr_test.833972042
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2761135997
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.1752150413
/workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1735241795
/workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.508566439
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.3428777566
/workspace/coverage/cover_reg_top/11.hmac_intr_test.600182930
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.306321506
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4185683898
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1403247275
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.3593518812
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.785872133
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.4165228385
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.443972724
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.244672357
/workspace/coverage/cover_reg_top/13.hmac_intr_test.2309177540
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2022228439
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.976024879
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.544439197
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.20681736
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.2298498763
/workspace/coverage/cover_reg_top/14.hmac_intr_test.3093997012
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1588186630
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.1133507483
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.784407460
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2218324485
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.2748863244
/workspace/coverage/cover_reg_top/15.hmac_intr_test.258394212
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.168597989
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.1292950727
/workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3920166285
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3346248302
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.2204362453
/workspace/coverage/cover_reg_top/16.hmac_intr_test.2482466457
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4043243729
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.2378472665
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1264985339
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.155821468
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.917659351
/workspace/coverage/cover_reg_top/17.hmac_intr_test.2331716655
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.671114618
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.2593410149
/workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3700607192
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.334190418
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.2812201455
/workspace/coverage/cover_reg_top/18.hmac_intr_test.762715048
/workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1014363927
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.2985344617
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2591316245
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2358956907
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.4260444067
/workspace/coverage/cover_reg_top/19.hmac_intr_test.4098366631
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1189327117
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.382354782
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1023460813
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3318160028
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1331305001
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.122941521
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.2187924379
/workspace/coverage/cover_reg_top/2.hmac_intr_test.3976989752
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3691766194
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.1190827586
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3986608497
/workspace/coverage/cover_reg_top/20.hmac_intr_test.2346201865
/workspace/coverage/cover_reg_top/21.hmac_intr_test.2443702374
/workspace/coverage/cover_reg_top/22.hmac_intr_test.917195038
/workspace/coverage/cover_reg_top/23.hmac_intr_test.4063640474
/workspace/coverage/cover_reg_top/24.hmac_intr_test.752564089
/workspace/coverage/cover_reg_top/25.hmac_intr_test.3167624401
/workspace/coverage/cover_reg_top/26.hmac_intr_test.1193674848
/workspace/coverage/cover_reg_top/27.hmac_intr_test.860524187
/workspace/coverage/cover_reg_top/28.hmac_intr_test.3872532405
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2608694374
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3459650836
/workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1371773174
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3786440890
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.673011092
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.773262905
/workspace/coverage/cover_reg_top/3.hmac_intr_test.1173112939
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3670489194
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.347253850
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2543990277
/workspace/coverage/cover_reg_top/30.hmac_intr_test.1644471181
/workspace/coverage/cover_reg_top/31.hmac_intr_test.3287240988
/workspace/coverage/cover_reg_top/33.hmac_intr_test.1224245692
/workspace/coverage/cover_reg_top/34.hmac_intr_test.3354706037
/workspace/coverage/cover_reg_top/35.hmac_intr_test.4101150768
/workspace/coverage/cover_reg_top/36.hmac_intr_test.816095260
/workspace/coverage/cover_reg_top/37.hmac_intr_test.3100191842
/workspace/coverage/cover_reg_top/38.hmac_intr_test.3646363977
/workspace/coverage/cover_reg_top/39.hmac_intr_test.3330848785
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3418415710
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3724753761
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2485939217
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.3690061826
/workspace/coverage/cover_reg_top/4.hmac_intr_test.4281773840
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.321933916
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.4090966777
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1401720876
/workspace/coverage/cover_reg_top/40.hmac_intr_test.3448381386
/workspace/coverage/cover_reg_top/41.hmac_intr_test.2970853600
/workspace/coverage/cover_reg_top/42.hmac_intr_test.3514551099
/workspace/coverage/cover_reg_top/43.hmac_intr_test.681861561
/workspace/coverage/cover_reg_top/44.hmac_intr_test.53088516
/workspace/coverage/cover_reg_top/45.hmac_intr_test.1152584861
/workspace/coverage/cover_reg_top/46.hmac_intr_test.533447461
/workspace/coverage/cover_reg_top/47.hmac_intr_test.2037303594
/workspace/coverage/cover_reg_top/48.hmac_intr_test.528706838
/workspace/coverage/cover_reg_top/49.hmac_intr_test.1536267813
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1875566551
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.1511677775
/workspace/coverage/cover_reg_top/5.hmac_intr_test.1689754536
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4085465430
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.2368477174
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.707305272
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3117688757
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.2918651947
/workspace/coverage/cover_reg_top/6.hmac_intr_test.173985169
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1506410175
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.1409978271
/workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1114616428
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.865625581
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2999504205
/workspace/coverage/cover_reg_top/7.hmac_intr_test.1212282249
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3267050708
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.3159675609
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3181938646
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2280254101
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.292079917
/workspace/coverage/cover_reg_top/8.hmac_intr_test.4243854871
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4095562731
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.24981290
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4111699817
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.1833873764
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3593711675
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.3098575502
/workspace/coverage/default/0.hmac_alert_test.1941648537
/workspace/coverage/default/0.hmac_back_pressure.4183806725
/workspace/coverage/default/0.hmac_burst_wr.4182128073
/workspace/coverage/default/0.hmac_datapath_stress.3602909860
/workspace/coverage/default/0.hmac_error.388598244
/workspace/coverage/default/0.hmac_long_msg.3275653966
/workspace/coverage/default/0.hmac_sec_cm.424768816
/workspace/coverage/default/0.hmac_smoke.3756822864
/workspace/coverage/default/0.hmac_stress_all.1384355771
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3245957245
/workspace/coverage/default/0.hmac_test_hmac_vectors.1659077036
/workspace/coverage/default/0.hmac_test_sha_vectors.1876643709
/workspace/coverage/default/0.hmac_wipe_secret.1808106265
/workspace/coverage/default/1.hmac_alert_test.1089578560
/workspace/coverage/default/1.hmac_back_pressure.4226255848
/workspace/coverage/default/1.hmac_burst_wr.4290253172
/workspace/coverage/default/1.hmac_datapath_stress.879497870
/workspace/coverage/default/1.hmac_error.2181962278
/workspace/coverage/default/1.hmac_long_msg.3521465598
/workspace/coverage/default/1.hmac_smoke.1212585365
/workspace/coverage/default/1.hmac_stress_all.4002912773
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1030889255
/workspace/coverage/default/1.hmac_test_hmac_vectors.369318921
/workspace/coverage/default/1.hmac_test_sha_vectors.1979123972
/workspace/coverage/default/1.hmac_wipe_secret.334079436
/workspace/coverage/default/10.hmac_alert_test.1663523804
/workspace/coverage/default/10.hmac_back_pressure.2006866336
/workspace/coverage/default/10.hmac_burst_wr.2677176613
/workspace/coverage/default/10.hmac_datapath_stress.1039206712
/workspace/coverage/default/10.hmac_error.1061171808
/workspace/coverage/default/10.hmac_long_msg.1565860046
/workspace/coverage/default/10.hmac_smoke.2309867486
/workspace/coverage/default/10.hmac_stress_all.998661698
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2766745592
/workspace/coverage/default/10.hmac_test_hmac_vectors.3160326118
/workspace/coverage/default/10.hmac_test_sha_vectors.3612978085
/workspace/coverage/default/10.hmac_wipe_secret.301922834
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.288230134
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.2069120015
/workspace/coverage/default/102.hmac_stress_all_with_rand_reset.2562128881
/workspace/coverage/default/103.hmac_stress_all_with_rand_reset.3960437130
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.576180974
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.395472878
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.877638620
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3722771840
/workspace/coverage/default/11.hmac_alert_test.1012058131
/workspace/coverage/default/11.hmac_back_pressure.950961427
/workspace/coverage/default/11.hmac_burst_wr.2631317084
/workspace/coverage/default/11.hmac_datapath_stress.3017273268
/workspace/coverage/default/11.hmac_error.3117823069
/workspace/coverage/default/11.hmac_long_msg.3234148764
/workspace/coverage/default/11.hmac_smoke.305971099
/workspace/coverage/default/11.hmac_stress_all.3748072042
/workspace/coverage/default/11.hmac_test_hmac_vectors.1245132029
/workspace/coverage/default/11.hmac_test_sha_vectors.2898521130
/workspace/coverage/default/11.hmac_wipe_secret.1135642740
/workspace/coverage/default/110.hmac_stress_all_with_rand_reset.3423186853
/workspace/coverage/default/111.hmac_stress_all_with_rand_reset.3092447987
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/workspace/coverage/default/74.hmac_stress_all_with_rand_reset.2187602099
/workspace/coverage/default/75.hmac_stress_all_with_rand_reset.4097893726
/workspace/coverage/default/76.hmac_stress_all_with_rand_reset.35812871
/workspace/coverage/default/77.hmac_stress_all_with_rand_reset.1970293831
/workspace/coverage/default/78.hmac_stress_all_with_rand_reset.3604109192
/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.4180637954
/workspace/coverage/default/8.hmac_alert_test.1824282393
/workspace/coverage/default/8.hmac_back_pressure.3978415131
/workspace/coverage/default/8.hmac_burst_wr.766557191
/workspace/coverage/default/8.hmac_datapath_stress.4176433095
/workspace/coverage/default/8.hmac_long_msg.3282082120
/workspace/coverage/default/8.hmac_smoke.1405458922
/workspace/coverage/default/8.hmac_stress_all.2636634900
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3827529693
/workspace/coverage/default/8.hmac_test_hmac_vectors.2860756739
/workspace/coverage/default/8.hmac_test_sha_vectors.2830325629
/workspace/coverage/default/8.hmac_wipe_secret.2477478824
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1647832349
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.1642817232
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.3348056017
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2153316502
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.383738110
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3807509921
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.186020534
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.169483997
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.555178039
/workspace/coverage/default/9.hmac_alert_test.1575662161
/workspace/coverage/default/9.hmac_back_pressure.3269138113
/workspace/coverage/default/9.hmac_burst_wr.2710518177
/workspace/coverage/default/9.hmac_datapath_stress.3193332482
/workspace/coverage/default/9.hmac_error.1031841412
/workspace/coverage/default/9.hmac_long_msg.3408973481
/workspace/coverage/default/9.hmac_smoke.3079556687
/workspace/coverage/default/9.hmac_stress_all.565754879
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.483017740
/workspace/coverage/default/9.hmac_test_hmac_vectors.300936765
/workspace/coverage/default/9.hmac_test_sha_vectors.2418310665
/workspace/coverage/default/9.hmac_wipe_secret.3595039051
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2978704600
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3276161800
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.967295190
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.2207420142
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.970865303
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3790976587
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2571288415
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1429608396
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.1770130706
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1187748253



Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T13 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.400827580 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:13 PM PST 23 25173564 ps
T14 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.244672357 Dec 27 12:33:15 PM PST 23 Dec 27 12:33:44 PM PST 23 79933372 ps
T15 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3267050708 Dec 27 12:33:27 PM PST 23 Dec 27 12:33:49 PM PST 23 115882867 ps
T16 /workspace/coverage/cover_reg_top/11.hmac_intr_test.600182930 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:06 PM PST 23 50603951 ps
T17 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1200437638 Dec 27 12:34:04 PM PST 23 Dec 27 12:35:46 PM PST 23 27889816556 ps
T18 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3670489194 Dec 27 12:33:38 PM PST 23 Dec 27 12:33:55 PM PST 23 51567462 ps
T19 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1036494367 Dec 27 12:33:30 PM PST 23 Dec 27 12:33:50 PM PST 23 45256732 ps
T20 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2368477174 Dec 27 12:33:30 PM PST 23 Dec 27 12:33:51 PM PST 23 169846716 ps
T21 /workspace/coverage/cover_reg_top/27.hmac_intr_test.860524187 Dec 27 12:35:32 PM PST 23 Dec 27 12:35:46 PM PST 23 15045802 ps
T22 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4191274167 Dec 27 12:33:27 PM PST 23 Dec 27 12:33:49 PM PST 23 16955410 ps
T24 /workspace/coverage/cover_reg_top/48.hmac_intr_test.528706838 Dec 27 12:33:41 PM PST 23 Dec 27 12:33:56 PM PST 23 16568678 ps
T32 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1539082256 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:23 PM PST 23 435363403 ps
T33 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1506410175 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:53 PM PST 23 59974981 ps
T23 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.382354782 Dec 27 12:34:21 PM PST 23 Dec 27 12:34:39 PM PST 23 104430419 ps
T25 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1409978271 Dec 27 12:33:22 PM PST 23 Dec 27 12:33:47 PM PST 23 112112863 ps
T46 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1331305001 Dec 27 12:33:38 PM PST 23 Dec 27 12:33:54 PM PST 23 22951123 ps
T26 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.508566439 Dec 27 12:33:32 PM PST 23 Dec 27 12:33:52 PM PST 23 91309087 ps
T126 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3794274483 Dec 27 12:33:32 PM PST 23 Dec 27 12:33:50 PM PST 23 62228065 ps
T127 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2443702374 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:12 PM PST 23 16787273 ps
T83 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1833873764 Dec 27 12:33:24 PM PST 23 Dec 27 12:33:48 PM PST 23 22844966 ps
T128 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3330848785 Dec 27 12:34:19 PM PST 23 Dec 27 12:34:36 PM PST 23 15899387 ps
T138 /workspace/coverage/cover_reg_top/24.hmac_intr_test.752564089 Dec 27 12:33:59 PM PST 23 Dec 27 12:34:15 PM PST 23 35184310 ps
T27 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.865625581 Dec 27 12:33:28 PM PST 23 Dec 27 12:33:50 PM PST 23 16673670 ps
T28 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.122941521 Dec 27 12:33:44 PM PST 23 Dec 27 12:56:35 PM PST 23 431752002766 ps
T61 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3700607192 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:23 PM PST 23 554495382 ps
T84 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3691766194 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:28 PM PST 23 107213211 ps
T85 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2022228439 Dec 27 12:33:57 PM PST 23 Dec 27 12:34:13 PM PST 23 161916714 ps
T69 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2557173080 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:04 PM PST 23 74818669 ps
T139 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3167624401 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:05 PM PST 23 13479592 ps
T64 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3318160028 Dec 27 12:33:36 PM PST 23 Dec 27 12:34:01 PM PST 23 5283746691 ps
T29 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2378472665 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:08 PM PST 23 208182146 ps
T62 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.707305272 Dec 27 12:36:27 PM PST 23 Dec 27 12:37:07 PM PST 23 47058158 ps
T63 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1401720876 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:54 PM PST 23 81024870 ps
T70 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4095562731 Dec 27 12:33:22 PM PST 23 Dec 27 12:33:48 PM PST 23 43478090 ps
T65 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3100191842 Dec 27 12:35:19 PM PST 23 Dec 27 12:35:36 PM PST 23 62239837 ps
T71 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.292079917 Dec 27 12:34:02 PM PST 23 Dec 27 12:34:17 PM PST 23 58238701 ps
T140 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2309177540 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:54 PM PST 23 12706108 ps
T30 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1292950727 Dec 27 12:34:11 PM PST 23 Dec 27 12:34:29 PM PST 23 237567872 ps
T141 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4281773840 Dec 27 12:33:14 PM PST 23 Dec 27 12:33:43 PM PST 23 40157752 ps
T31 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2593410149 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:05 PM PST 23 198886897 ps
T72 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.481536597 Dec 27 12:33:14 PM PST 23 Dec 27 12:33:48 PM PST 23 138519425 ps
T73 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3593711675 Dec 27 12:33:18 PM PST 23 Dec 27 12:33:46 PM PST 23 115098620 ps
T142 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1689754536 Dec 27 12:33:41 PM PST 23 Dec 27 12:33:57 PM PST 23 83503384 ps
T68 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.673910728 Dec 27 12:33:30 PM PST 23 Dec 27 12:33:51 PM PST 23 382009819 ps
T66 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3287240988 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:22 PM PST 23 19034044 ps
T143 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3724753761 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:56 PM PST 23 72915756 ps
T74 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1023460813 Dec 27 12:34:08 PM PST 23 Dec 27 12:34:27 PM PST 23 62866973 ps
T144 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2290331776 Dec 27 12:33:26 PM PST 23 Dec 27 12:33:49 PM PST 23 80754937 ps
T145 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.308081342 Dec 27 12:33:40 PM PST 23 Dec 27 12:33:57 PM PST 23 31362170 ps
T146 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3354706037 Dec 27 12:34:38 PM PST 23 Dec 27 12:34:56 PM PST 23 32393368 ps
T147 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4243854871 Dec 27 12:33:50 PM PST 23 Dec 27 12:34:07 PM PST 23 28298321 ps
T148 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3159675609 Dec 27 12:34:20 PM PST 23 Dec 27 12:34:39 PM PST 23 161352990 ps
T149 /workspace/coverage/cover_reg_top/36.hmac_intr_test.816095260 Dec 27 12:33:53 PM PST 23 Dec 27 12:34:09 PM PST 23 30248623 ps
T129 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.548579224 Dec 27 12:33:44 PM PST 23 Dec 27 12:34:02 PM PST 23 215342122 ps
T150 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4063640474 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 48713784 ps
T151 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.673011092 Dec 27 12:33:34 PM PST 23 Dec 27 12:33:52 PM PST 23 37236383 ps
T152 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4186468662 Dec 27 12:33:23 PM PST 23 Dec 27 12:33:50 PM PST 23 77374779 ps
T153 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4090966777 Dec 27 12:33:57 PM PST 23 Dec 27 12:34:14 PM PST 23 152092037 ps
T154 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1875566551 Dec 27 12:33:41 PM PST 23 Dec 27 12:48:28 PM PST 23 277417948041 ps
T155 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.24981290 Dec 27 12:36:30 PM PST 23 Dec 27 12:36:57 PM PST 23 41334087 ps
T156 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2485939217 Dec 27 12:33:28 PM PST 23 Dec 27 12:33:49 PM PST 23 52720818 ps
T75 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.917659351 Dec 27 12:34:02 PM PST 23 Dec 27 12:34:17 PM PST 23 220718723 ps
T130 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3415581434 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:07 PM PST 23 204302389 ps
T157 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1224245692 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:28 PM PST 23 21711469 ps
T76 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3418415710 Dec 27 12:33:34 PM PST 23 Dec 27 12:33:53 PM PST 23 113327157 ps
T135 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3769825305 Dec 27 12:33:43 PM PST 23 Dec 27 12:34:00 PM PST 23 1614901367 ps
T158 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3093997012 Dec 27 12:33:57 PM PST 23 Dec 27 12:34:13 PM PST 23 48383831 ps
T159 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1644471181 Dec 27 12:35:32 PM PST 23 Dec 27 12:35:46 PM PST 23 112903591 ps
T136 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3986608497 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:35 PM PST 23 482226273 ps
T160 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4085465430 Dec 27 12:33:21 PM PST 23 Dec 27 12:33:47 PM PST 23 30102791 ps
T161 /workspace/coverage/cover_reg_top/10.hmac_intr_test.833972042 Dec 27 12:33:45 PM PST 23 Dec 27 12:34:02 PM PST 23 36152612 ps
T162 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.785872133 Dec 27 12:33:20 PM PST 23 Dec 27 12:33:47 PM PST 23 42729969 ps
T163 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1193674848 Dec 27 12:34:01 PM PST 23 Dec 27 12:34:16 PM PST 23 10743686 ps
T164 /workspace/coverage/cover_reg_top/15.hmac_intr_test.258394212 Dec 27 12:34:17 PM PST 23 Dec 27 12:34:34 PM PST 23 48885241 ps
T165 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.302111453 Dec 27 12:33:28 PM PST 23 Dec 27 12:33:50 PM PST 23 138369710 ps
T166 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2482466457 Dec 27 12:34:39 PM PST 23 Dec 27 12:34:56 PM PST 23 27158703 ps
T167 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1752150413 Dec 27 12:36:31 PM PST 23 Dec 27 12:36:57 PM PST 23 27634213 ps
T168 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1588186630 Dec 27 12:33:44 PM PST 23 Dec 27 12:34:00 PM PST 23 161597908 ps
T169 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.20681736 Dec 27 12:34:00 PM PST 23 Dec 27 12:43:06 PM PST 23 373106151360 ps
T170 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.334190418 Dec 27 12:35:39 PM PST 23 Dec 27 12:35:54 PM PST 23 18405961 ps
T171 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2346201865 Dec 27 12:33:59 PM PST 23 Dec 27 12:34:15 PM PST 23 18448513 ps
T172 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3098575502 Dec 27 12:33:22 PM PST 23 Dec 27 12:33:52 PM PST 23 138518474 ps
T173 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2331716655 Dec 27 12:33:39 PM PST 23 Dec 27 12:33:55 PM PST 23 41923302 ps
T174 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4111699817 Dec 27 12:36:27 PM PST 23 Dec 27 12:36:50 PM PST 23 34297254 ps
T175 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3346248302 Dec 27 12:33:51 PM PST 23 Dec 27 12:34:09 PM PST 23 37051954 ps
T176 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1014363927 Dec 27 12:34:26 PM PST 23 Dec 27 12:34:44 PM PST 23 325087097 ps
T177 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3459650836 Dec 27 12:35:02 PM PST 23 Dec 27 12:35:22 PM PST 23 59018547 ps
T178 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1536267813 Dec 27 12:35:38 PM PST 23 Dec 27 12:35:51 PM PST 23 63926023 ps
T179 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2608694374 Dec 27 12:35:32 PM PST 23 Dec 27 12:35:46 PM PST 23 16817097 ps
T180 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.671114618 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:04 PM PST 23 101593087 ps
T181 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.331978999 Dec 27 12:33:26 PM PST 23 Dec 27 12:33:49 PM PST 23 254386511 ps
T182 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2985344617 Dec 27 12:33:59 PM PST 23 Dec 27 12:34:15 PM PST 23 215458998 ps
T183 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4165228385 Dec 27 12:33:43 PM PST 23 Dec 27 12:34:00 PM PST 23 72776817 ps
T184 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2218324485 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:05 PM PST 23 99120496 ps
T185 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.976024879 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:55 PM PST 23 48735935 ps
T186 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1212282249 Dec 27 12:33:40 PM PST 23 Dec 27 12:33:55 PM PST 23 35142084 ps
T187 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.321933916 Dec 27 12:36:27 PM PST 23 Dec 27 12:36:50 PM PST 23 24636924 ps
T188 /workspace/coverage/cover_reg_top/44.hmac_intr_test.53088516 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 13330389 ps
T189 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.543124341 Dec 27 12:33:19 PM PST 23 Dec 27 12:33:46 PM PST 23 187399591 ps
T190 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2280254101 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:14 PM PST 23 22913784 ps
T77 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4018783975 Dec 27 12:33:40 PM PST 23 Dec 27 12:33:56 PM PST 23 81938561 ps
T191 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4260444067 Dec 27 12:35:29 PM PST 23 Dec 27 12:35:43 PM PST 23 18527375 ps
T192 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.155821468 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:14 PM PST 23 27881808 ps
T193 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1658181585 Dec 27 12:33:18 PM PST 23 Dec 27 12:33:46 PM PST 23 98998016 ps
T78 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3687530 Dec 27 12:33:50 PM PST 23 Dec 27 12:34:07 PM PST 23 12277244 ps
T79 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.21451432 Dec 27 12:34:04 PM PST 23 Dec 27 12:34:19 PM PST 23 26366653 ps
T194 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1735241795 Dec 27 12:33:38 PM PST 23 Dec 27 12:33:55 PM PST 23 56727528 ps
T195 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3646363977 Dec 27 12:33:33 PM PST 23 Dec 27 12:33:51 PM PST 23 13924925 ps
T196 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2761135997 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:35 PM PST 23 323197099 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3690061826 Dec 27 12:33:14 PM PST 23 Dec 27 12:33:44 PM PST 23 16250533 ps
T131 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4185683898 Dec 27 12:36:21 PM PST 23 Dec 27 12:36:45 PM PST 23 504727042 ps
T197 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4098366631 Dec 27 12:33:30 PM PST 23 Dec 27 12:33:50 PM PST 23 33614255 ps
T198 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1152584861 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:12 PM PST 23 12385823 ps
T1 /workspace/coverage/default/40.hmac_error.3185074980 Dec 27 12:21:23 PM PST 23 Dec 27 12:21:28 PM PST 23 362168092 ps
T2 /workspace/coverage/default/11.hmac_stress_all.3748072042 Dec 27 12:26:28 PM PST 23 Dec 27 12:34:52 PM PST 23 11607844547 ps
T3 /workspace/coverage/default/26.hmac_back_pressure.484281220 Dec 27 12:25:02 PM PST 23 Dec 27 12:25:40 PM PST 23 1157940099 ps
T7 /workspace/coverage/default/26.hmac_wipe_secret.1193077834 Dec 27 12:26:52 PM PST 23 Dec 27 12:27:17 PM PST 23 1141995300 ps
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