Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21417746

1

T1

202

T2

51714

T3

15

auto[1]

10075798

1

T1

116

T2

50414

T3

17

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10229671

1

T1

194

T2

45722

T3

18

auto[1]

21263873

1

T1

124

T2

56406

T3

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18815435

1

T1

10

T2

38074

T3

14

auto[1]

12678109

1

T1

308

T2

64054

T3

18

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	17175444	1			T1	239		T2	28290		T7	476
fifo_depth[1]	1594762	1			T1	5		T2	5655		T7	29
fifo_depth[2]	1464706	1			T1	10		T2	6061		T7	6
fifo_depth[3]	1263018	1			T1	8		T2	6085		T3	1
fifo_depth[4]	1228572	1			T1	10		T2	6475		T3	1
fifo_depth[5]	1058738	1			T1	7		T2	6231		T4	6486
fifo_depth[6]	1091920	1			T1	8		T2	6153		T3	4
fifo_depth[7]	931440	1			T1	11		T2	5620		T3	3
fifo_depth[8]	1106313	1			T1	3		T2	6850		T3	6
fifo_depth[9]	646574	1			T1	2		T2	3795		T3	2
fifo_depth[10]	660199	1			T1	3		T2	3136		T3	3
fifo_depth[11]	396545	1			T1	3		T2	1976		T3	2
fifo_depth[12]	663159	1			T1	4		T2	4153		T3	5
fifo_depth[13]	293167	1			T1	1		T2	1575		T3	3
fifo_depth[14]	484178	1			T1	2		T2	2496		T3	1
fifo_depth[15]	270162	1			T1	2		T2	1620		T4	2851
fifo_depth[16]	1164647	1			T2	5957		T3	1		T4	17498

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14318100

1

T1

79

T2

73838

T3

32

auto[1]

17175444

1

T1

239

T2

28290

T7

476

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30328897

1

T1

318

T2

96171

T3

31

auto[1]

1164647

1

T2

5957

T3

1

T4

17498

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1124567

1

T2

4261

T3

4

T4

7195

auto[0]

auto[0]

auto[0]

auto[1]

1097742

1

T2

6707

T3

2

T4

12882

auto[0]

auto[0]

auto[1]

auto[0]

3933730

1

T2

7179

T3

2

T4

26728

auto[0]

auto[0]

auto[1]

auto[1]

1097090

1

T2

11035

T3

6

T4

11750

auto[0]

auto[1]

auto[0]

auto[0]

1809142

1

T2

9889

T3

6

T7

38

auto[0]

auto[1]

auto[0]

auto[1]

1748444

1

T2

11382

T3

6

T4

12178

auto[0]

auto[1]

auto[1]

auto[0]

1764399

1

T2

14968

T3

3

T4

17080

auto[0]

auto[1]

auto[1]

auto[1]

1742986

1

T1

79

T2

8417

T3

3

auto[1]

auto[0]

auto[0]

auto[0]

856889

1

T2

1870

T4

2527

T9

6

auto[1]

auto[0]

auto[0]

auto[1]

827948

1

T2

2486

T4

2570

T9

28

auto[1]

auto[0]

auto[1]

auto[0]

9084835

1

T1

8

T2

2457

T4

30654

auto[1]

auto[0]

auto[1]

auto[1]

792634

1

T1

2

T2

2079

T4

5546

auto[1]

auto[1]

auto[0]

auto[0]

1415666

1

T1

194

T2

4535

T7

476

auto[1]

auto[1]

auto[0]

auto[1]

1349273

1

T2

4592

T4

3525

T9

3

auto[1]

auto[1]

auto[1]

auto[0]

1428518

1

T2

6555

T4

5329

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

1419681

1

T1

35

T2

3716

T4

4229

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1823972

1

T2

5717

T3

4

T4

7393

auto[0]

auto[0]

auto[0]

auto[1]

1788890

1

T2

9001

T3

2

T4

13764

auto[0]

auto[0]

auto[1]

auto[0]

12862113

1

T1

8

T2

8859

T3

2

auto[0]

auto[0]

auto[1]

auto[1]

1752582

1

T1

2

T2

10937

T3

5

auto[0]

auto[1]

auto[0]

auto[0]

3071885

1

T1

194

T2

14147

T3

6

auto[0]

auto[1]

auto[0]

auto[1]

2961300

1

T2

15619

T3

6

T4

14544

auto[0]

auto[1]

auto[1]

auto[0]

3045792

1

T2

20100

T3

3

T4

18408

auto[0]

auto[1]

auto[1]

auto[1]

3022363

1

T1

114

T2

11791

T3

3

auto[1]

auto[0]

auto[0]

auto[0]

157484

1

T2

414

T4

2329

T10

86

auto[1]

auto[0]

auto[0]

auto[1]

136800

1

T2

192

T4

1688

T10

133

auto[1]

auto[0]

auto[1]

auto[0]

156452

1

T2

777

T4

2740

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

137142

1

T2

2177

T3

1

T4

2306

auto[1]

auto[1]

auto[0]

auto[0]

152923

1

T2

277

T4

2543

T10

16

auto[1]

auto[1]

auto[0]

auto[1]

136417

1

T2

355

T4

1159

T10

41

auto[1]

auto[1]

auto[1]

auto[0]

147125

1

T2

1423

T4

4001

T11

3

auto[1]

auto[1]

auto[1]

auto[1]

140304

1

T2

342

T4

732

T10

201

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	856889	1			T2	1870		T4	2527		T9	6
fifo_depth[0]	auto[0]	auto[0]	auto[1]	827948	1			T2	2486		T4	2570		T9	28
fifo_depth[0]	auto[0]	auto[1]	auto[0]	9084835	1			T1	8		T2	2457		T4	30654
fifo_depth[0]	auto[0]	auto[1]	auto[1]	792634	1			T1	2		T2	2079		T4	5546
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1415666	1			T1	194		T2	4535		T7	476
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1349273	1			T2	4592		T4	3525		T9	3
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1428518	1			T2	6555		T4	5329		T9	2
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1419681	1			T1	35		T2	3716		T4	4229
fifo_depth[1]	auto[0]	auto[0]	auto[0]	81446	1			T2	336		T4	323		T12	3
fifo_depth[1]	auto[0]	auto[0]	auto[1]	79897	1			T2	473		T4	477		T10	13
fifo_depth[1]	auto[0]	auto[1]	auto[0]	689259	1			T2	445		T4	3467		T8	2469
fifo_depth[1]	auto[0]	auto[1]	auto[1]	78463	1			T2	413		T4	723		T10	22
fifo_depth[1]	auto[1]	auto[0]	auto[0]	167284	1			T2	922		T7	29		T4	399
fifo_depth[1]	auto[1]	auto[0]	auto[1]	163486	1			T2	921		T4	485		T10	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	168322	1			T2	1367		T4	986		T9	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	166605	1			T1	5		T2	778		T4	653
fifo_depth[2]	auto[0]	auto[0]	auto[0]	80060	1			T2	363		T4	357		T10	1
fifo_depth[2]	auto[0]	auto[0]	auto[1]	77006	1			T2	551		T4	613		T10	11
fifo_depth[2]	auto[0]	auto[1]	auto[0]	600361	1			T2	439		T4	3438		T8	2351
fifo_depth[2]	auto[0]	auto[1]	auto[1]	76312	1			T2	415		T4	765		T10	21
fifo_depth[2]	auto[1]	auto[0]	auto[0]	159004	1			T2	1024		T7	6		T4	423
fifo_depth[2]	auto[1]	auto[0]	auto[1]	155828	1			T2	1019		T4	538		T9	3
fifo_depth[2]	auto[1]	auto[1]	auto[0]	159769	1			T2	1417		T4	1117		T9	2
fifo_depth[2]	auto[1]	auto[1]	auto[1]	156366	1			T1	10		T2	833		T4	741
fifo_depth[3]	auto[0]	auto[0]	auto[0]	69951	1			T2	340		T3	1		T4	339
fifo_depth[3]	auto[0]	auto[0]	auto[1]	68408	1			T2	535		T4	613		T10	14
fifo_depth[3]	auto[0]	auto[1]	auto[0]	485569	1			T2	472		T4	3101		T8	2027
fifo_depth[3]	auto[0]	auto[1]	auto[1]	67817	1			T2	491		T4	640		T10	23
fifo_depth[3]	auto[1]	auto[0]	auto[0]	144515	1			T2	1033		T7	2		T4	388
fifo_depth[3]	auto[1]	auto[0]	auto[1]	141296	1			T2	1036		T4	502		T9	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	143510	1			T2	1359		T4	1113		T9	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	141952	1			T1	8		T2	819		T4	713
fifo_depth[4]	auto[0]	auto[0]	auto[0]	80862	1			T2	361		T4	401		T10	17
fifo_depth[4]	auto[0]	auto[0]	auto[1]	80733	1			T2	534		T4	662		T10	11
fifo_depth[4]	auto[0]	auto[1]	auto[0]	386178	1			T2	520		T4	2731		T8	1532
fifo_depth[4]	auto[0]	auto[1]	auto[1]	80698	1			T2	589		T3	1		T4	747
fifo_depth[4]	auto[1]	auto[0]	auto[0]	150246	1			T2	1053		T7	1		T4	566
fifo_depth[4]	auto[1]	auto[0]	auto[1]	150273	1			T2	1022		T4	616		T9	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	150737	1			T2	1473		T4	1070		T9	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	148845	1			T1	10		T2	923		T4	823
fifo_depth[5]	auto[0]	auto[0]	auto[0]	67253	1			T2	361		T4	362		T10	11
fifo_depth[5]	auto[0]	auto[0]	auto[1]	64983	1			T2	551		T4	576		T10	14
fifo_depth[5]	auto[0]	auto[1]	auto[0]	318616	1			T2	443		T4	2376		T8	1328
fifo_depth[5]	auto[0]	auto[1]	auto[1]	65109	1			T2	514		T4	609		T10	21
fifo_depth[5]	auto[1]	auto[0]	auto[0]	137186	1			T2	1003		T4	360		T9	3
fifo_depth[5]	auto[1]	auto[0]	auto[1]	136092	1			T2	1037		T4	511		T10	3
fifo_depth[5]	auto[1]	auto[1]	auto[0]	135212	1			T2	1409		T4	1040		T9	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	134287	1			T1	7		T2	913		T4	652
fifo_depth[6]	auto[0]	auto[0]	auto[0]	77518	1			T2	353		T3	1		T4	304
fifo_depth[6]	auto[0]	auto[0]	auto[1]	75297	1			T2	537		T4	836		T10	24
fifo_depth[6]	auto[0]	auto[1]	auto[0]	291376	1			T2	490		T4	2230		T8	1222
fifo_depth[6]	auto[0]	auto[1]	auto[1]	76459	1			T2	521		T4	870		T10	20
fifo_depth[6]	auto[1]	auto[0]	auto[0]	144107	1			T2	974		T3	2		T4	472
fifo_depth[6]	auto[1]	auto[0]	auto[1]	142060	1			T2	971		T3	1		T4	776
fifo_depth[6]	auto[1]	auto[1]	auto[0]	143074	1			T2	1466		T4	983		T9	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	142029	1			T1	8		T2	841		T4	963
fifo_depth[7]	auto[0]	auto[0]	auto[0]	66021	1			T2	317		T4	339		T10	16
fifo_depth[7]	auto[0]	auto[0]	auto[1]	63122	1			T2	479		T4	765		T10	25
fifo_depth[7]	auto[0]	auto[1]	auto[0]	232655	1			T2	446		T4	1735		T8	1006
fifo_depth[7]	auto[0]	auto[1]	auto[1]	63134	1			T2	447		T3	1		T4	602
fifo_depth[7]	auto[1]	auto[0]	auto[0]	129185	1			T2	965		T3	2		T4	301
fifo_depth[7]	auto[1]	auto[0]	auto[1]	126202	1			T2	957		T4	686		T9	2
fifo_depth[7]	auto[1]	auto[1]	auto[0]	125661	1			T2	1211		T4	932		T9	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	125460	1			T1	11		T2	798		T4	703
fifo_depth[8]	auto[0]	auto[0]	auto[0]	96260	1			T2	458		T4	405		T10	20
fifo_depth[8]	auto[0]	auto[0]	auto[1]	96982	1			T2	490		T3	1		T4	1004
fifo_depth[8]	auto[0]	auto[1]	auto[0]	221872	1			T2	728		T3	1		T4	1607
fifo_depth[8]	auto[0]	auto[1]	auto[1]	95156	1			T2	1698		T3	1		T4	900
fifo_depth[8]	auto[1]	auto[0]	auto[0]	157640	1			T2	805		T3	1		T4	999
fifo_depth[8]	auto[1]	auto[0]	auto[1]	147465	1			T2	841		T3	1		T4	1261
fifo_depth[8]	auto[1]	auto[1]	auto[0]	146213	1			T2	1149		T4	915		T9	2
fifo_depth[8]	auto[1]	auto[1]	auto[1]	144725	1			T1	3		T2	681		T3	1
fifo_depth[9]	auto[0]	auto[0]	auto[0]	52499	1			T2	213		T3	1		T4	214
fifo_depth[9]	auto[0]	auto[0]	auto[1]	49278	1			T2	382		T4	861		T10	96
fifo_depth[9]	auto[0]	auto[1]	auto[0]	132522	1			T2	247		T4	1056		T8	485
fifo_depth[9]	auto[0]	auto[1]	auto[1]	50099	1			T2	365		T4	657		T10	84
fifo_depth[9]	auto[1]	auto[0]	auto[0]	92002	1			T2	600		T4	210		T9	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	90395	1			T2	603		T3	1		T4	630
fifo_depth[9]	auto[1]	auto[1]	auto[0]	90552	1			T2	844		T4	755		T9	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	89227	1			T1	2		T2	541		T4	679
fifo_depth[10]	auto[0]	auto[0]	auto[0]	62223	1			T2	298		T3	1		T4	287
fifo_depth[10]	auto[0]	auto[0]	auto[1]	60977	1			T2	317		T4	874		T10	313
fifo_depth[10]	auto[0]	auto[1]	auto[0]	114006	1			T2	225		T4	752		T8	276
fifo_depth[10]	auto[0]	auto[1]	auto[1]	63480	1			T2	358		T3	1		T4	625
fifo_depth[10]	auto[1]	auto[0]	auto[0]	92981	1			T2	443		T4	455		T10	46
fifo_depth[10]	auto[1]	auto[0]	auto[1]	88853	1			T2	558		T3	1		T4	880
fifo_depth[10]	auto[1]	auto[1]	auto[0]	90362	1			T2	600		T4	731		T9	2
fifo_depth[10]	auto[1]	auto[1]	auto[1]	87317	1			T1	3		T2	337		T4	702
fifo_depth[11]	auto[0]	auto[0]	auto[0]	38616	1			T2	111		T4	257		T10	9
fifo_depth[11]	auto[0]	auto[0]	auto[1]	36006	1			T2	239		T4	666		T10	246
fifo_depth[11]	auto[0]	auto[1]	auto[0]	67351	1			T2	185		T3	1		T4	480
fifo_depth[11]	auto[0]	auto[1]	auto[1]	38357	1			T2	242		T4	382		T10	453
fifo_depth[11]	auto[1]	auto[0]	auto[0]	55244	1			T2	263		T4	151		T9	1
fifo_depth[11]	auto[1]	auto[0]	auto[1]	54108	1			T2	378		T4	623		T9	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	53025	1			T2	316		T3	1		T4	589
fifo_depth[11]	auto[1]	auto[1]	auto[1]	53838	1			T1	3		T2	242		T4	500
fifo_depth[12]	auto[0]	auto[0]	auto[0]	72969	1			T2	152		T4	337		T10	16
fifo_depth[12]	auto[0]	auto[0]	auto[1]	79153	1			T2	401		T4	1152		T10	286
fifo_depth[12]	auto[0]	auto[1]	auto[0]	96782	1			T2	708		T4	424		T8	94
fifo_depth[12]	auto[0]	auto[1]	auto[1]	75492	1			T2	1947		T3	1		T4	773
fifo_depth[12]	auto[1]	auto[0]	auto[0]	90808	1			T2	201		T4	694		T10	43
fifo_depth[12]	auto[1]	auto[0]	auto[1]	84364	1			T2	334		T3	2		T4	1717
fifo_depth[12]	auto[1]	auto[1]	auto[0]	80882	1			T2	255		T3	1		T4	778
fifo_depth[12]	auto[1]	auto[1]	auto[1]	82709	1			T1	4		T2	155		T3	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	33754	1			T2	41		T4	219		T10	29
fifo_depth[13]	auto[0]	auto[0]	auto[1]	33682	1			T2	395		T3	1		T4	619
fifo_depth[13]	auto[0]	auto[1]	auto[0]	41437	1			T2	377		T4	215		T8	38
fifo_depth[13]	auto[0]	auto[1]	auto[1]	34656	1			T2	146		T4	319		T10	416
fifo_depth[13]	auto[1]	auto[0]	auto[0]	38400	1			T2	130		T3	1		T4	109
fifo_depth[13]	auto[1]	auto[0]	auto[1]	37565	1			T2	233		T4	470		T10	52
fifo_depth[13]	auto[1]	auto[1]	auto[0]	35832	1			T2	154		T4	695		T11	12
fifo_depth[13]	auto[1]	auto[1]	auto[1]	37841	1			T1	1		T2	99		T3	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	55856	1			T2	126		T4	416		T10	146
fifo_depth[14]	auto[0]	auto[0]	auto[1]	61746	1			T2	321		T4	974		T10	203
fifo_depth[14]	auto[0]	auto[1]	auto[0]	64602	1			T2	356		T4	225		T8	21
fifo_depth[14]	auto[0]	auto[1]	auto[1]	60605	1			T2	610		T4	620		T10	400
fifo_depth[14]	auto[1]	auto[0]	auto[0]	62386	1			T2	102		T4	328		T10	43
fifo_depth[14]	auto[1]	auto[0]	auto[1]	60061	1			T2	607		T4	1016		T10	48
fifo_depth[14]	auto[1]	auto[1]	auto[0]	60635	1			T2	312		T3	1		T4	693
fifo_depth[14]	auto[1]	auto[1]	auto[1]	58287	1			T1	2		T2	62		T4	950
fifo_depth[15]	auto[0]	auto[0]	auto[0]	31795	1			T2	17		T4	306		T10	153
fifo_depth[15]	auto[0]	auto[0]	auto[1]	33672	1			T2	310		T4	502		T10	179
fifo_depth[15]	auto[0]	auto[1]	auto[0]	34692	1			T2	321		T4	151		T8	4
fifo_depth[15]	auto[0]	auto[1]	auto[1]	34111	1			T2	102		T4	212		T10	265
fifo_depth[15]	auto[1]	auto[0]	auto[0]	35231	1			T2	94		T4	90		T10	23
fifo_depth[15]	auto[1]	auto[0]	auto[1]	33979	1			T2	510		T4	308		T10	48
fifo_depth[15]	auto[1]	auto[1]	auto[0]	33488	1			T2	213		T4	682		T11	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	33194	1			T1	2		T2	53		T4	600
fifo_depth[16]	auto[0]	auto[0]	auto[0]	157484	1			T2	414		T4	2329		T10	86
fifo_depth[16]	auto[0]	auto[0]	auto[1]	136800	1			T2	192		T4	1688		T10	133
fifo_depth[16]	auto[0]	auto[1]	auto[0]	156452	1			T2	777		T4	2740		T8	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	137142	1			T2	2177		T3	1		T4	2306
fifo_depth[16]	auto[1]	auto[0]	auto[0]	152923	1			T2	277		T4	2543		T10	16
fifo_depth[16]	auto[1]	auto[0]	auto[1]	136417	1			T2	355		T4	1159		T10	41
fifo_depth[16]	auto[1]	auto[1]	auto[0]	147125	1			T2	1423		T4	4001		T11	3
fifo_depth[16]	auto[1]	auto[1]	auto[1]	140304	1			T2	342		T4	732		T10	201