Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	42693217	1			T16	8		T19	4		T20	1
all_pins[1]	42693217	1			T16	8		T19	4		T20	1
all_pins[2]	42693217	1			T16	8		T19	4		T20	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	92771911	1			T16	18		T19	11		T20	3
values[0x1]	35307740	1			T16	6		T19	1		T21	6
transitions[0x0=>0x1]	31000986	1			T16	4		T19	1		T21	3
transitions[0x1=>0x0]	31001016	1			T16	4		T19	1		T21	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	42511449	1			T16	8		T19	3		T20	1
all_pins[0]	values[0x1]	181768	1			T19	1		T21	3		T22	2
all_pins[0]	transitions[0x0=>0x1]	181492	1			T19	1		T22	1		T24	2
all_pins[0]	transitions[0x1=>0x0]	16551649	1			T16	3		T21	1		T22	3
all_pins[1]	values[0x0]	24119140	1			T16	5		T19	4		T20	1
all_pins[1]	values[0x1]	18574077	1			T16	3		T22	2		T24	1
all_pins[1]	transitions[0x0=>0x1]	18432081	1			T16	3		T22	2		T24	1
all_pins[1]	transitions[0x1=>0x0]	39772	1			T19	1		T21	3		T22	2
all_pins[2]	values[0x0]	26141322	1			T16	5		T19	4		T20	1
all_pins[2]	values[0x1]	16551895	1			T16	3		T21	3		T22	3
all_pins[2]	transitions[0x0=>0x1]	12387413	1			T16	1		T21	3		T22	2
all_pins[2]	transitions[0x1=>0x0]	14409595	1			T16	1		T22	1		T24	1