Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	4380	1			T16	7		T19	4		T21	4
all_values[1]	4380	1			T16	7		T19	4		T21	4
all_values[2]	4380	1			T16	7		T19	4		T21	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6324

1

T16

10

T19

8

T21

4

auto[1]

6816

1

T16

11

T19

4

T21

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4863

1

T16

9

T19

9

T21

1

auto[1]

8277

1

T16

12

T19

3

T21

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7433

1

T16

15

T19

9

T21

6

auto[1]

5707

1

T16

6

T19

3

T21

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

777

1

T16

3

T22

1

T24

2

all_values[0]

auto[0]

auto[0]

auto[1]

406

1

T22

1

T126

3

T127

1

all_values[0]

auto[0]

auto[1]

auto[0]

877

1

T16

3

T19

2

T22

2

all_values[0]

auto[0]

auto[1]

auto[1]

422

1

T21

2

T22

1

T24

1

all_values[0]

auto[1]

auto[0]

auto[1]

885

1

T16

1

T19

1

T24

1

all_values[0]

auto[1]

auto[1]

auto[1]

1013

1

T19

1

T21

2

T22

2

all_values[1]

auto[0]

auto[0]

auto[0]

731

1

T16

1

T19

3

T21

1

all_values[1]

auto[0]

auto[0]

auto[1]

468

1

T16

1

T21

1

T24

2

all_values[1]

auto[0]

auto[1]

auto[0]

894

1

T16

1

T22

1

T127

1

all_values[1]

auto[0]

auto[1]

auto[1]

397

1

T16

1

T22

1

T126

1

all_values[1]

auto[1]

auto[0]

auto[1]

931

1

T19

1

T21

1

T22

2

all_values[1]

auto[1]

auto[1]

auto[1]

959

1

T16

3

T21

1

T22

2

all_values[2]

auto[0]

auto[0]

auto[0]

753

1

T16

1

T19

3

T22

2

all_values[2]

auto[0]

auto[0]

auto[1]

443

1

T16

2

T24

2

T126

1

all_values[2]

auto[0]

auto[1]

auto[0]

831

1

T19

1

T127

1

T128

2

all_values[2]

auto[0]

auto[1]

auto[1]

434

1

T16

2

T21

2

T22

2

all_values[2]

auto[1]

auto[0]

auto[1]

930

1

T16

1

T21

1

T22

2

all_values[2]

auto[1]

auto[1]

auto[1]

989

1

T16

1

T21

1

T22

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal