Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126919

1

T1

4

T2

201

T3

15

auto[1]

49749

1

T1

5

T2

170

T3

17

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Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48044

1

T1

3

T2

191

T3

18

auto[1]

128624

1

T1

6

T2

180

T3

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118528

1

T1

5

T2

160

T3

14

auto[1]

58140

1

T1

4

T2

211

T3

18

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Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	10559	1			T1	1		T2	46		T3	4
auto[0]	auto[0]	auto[1]	10540	1			T2	39		T3	2		T4	57
auto[0]	auto[1]	auto[0]	87167	1			T1	2		T2	41		T3	2
auto[0]	auto[1]	auto[1]	10262	1			T1	2		T2	34		T3	6
auto[1]	auto[0]	auto[0]	13396	1			T1	1		T2	55		T3	6
auto[1]	auto[0]	auto[1]	13549	1			T1	1		T2	51		T3	6
auto[1]	auto[1]	auto[0]	15797	1			T2	59		T3	3		T4	72
auto[1]	auto[1]	auto[1]	15398	1			T1	2		T2	46		T3	3