Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116782341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

131322408

1

T14

67

T15

37

T16

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97872812	1			T14	56		T15	27		T16	11
values[0x0]	69721701	1			T14	25		T15	23		T16	8
values[0x1]	80510236	1			T14	20		T15	48		T16	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	85328442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162776307

1

T14

75

T15

57

T16

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	899898	1			T17	2		T22	6		T61	11
valid_sources[0x01]	914877	1			T17	3		T22	6		T23	1
valid_sources[0x02]	863311	1			T17	5		T22	1		T23	1
valid_sources[0x03]	920848	1			T17	2		T22	3		T61	5
valid_sources[0x04]	897222	1			T15	2		T22	2		T61	7
valid_sources[0x05]	893013	1			T22	9		T23	1		T61	8
valid_sources[0x06]	896992	1			T17	2		T22	4		T61	8
valid_sources[0x07]	917834	1			T17	3		T22	8		T61	12
valid_sources[0x08]	878759	1			T15	1		T17	3		T22	8
valid_sources[0x09]	906865	1			T22	1		T24	1		T61	4
valid_sources[0x0a]	877309	1			T17	3		T22	13		T23	2
valid_sources[0x0b]	903956	1			T15	1		T17	3		T23	2
valid_sources[0x0c]	908908	1			T15	1		T19	1		T22	6
valid_sources[0x0d]	892003	1			T22	8		T61	7		T77	4
valid_sources[0x0e]	912088	1			T15	1		T17	2		T22	4
valid_sources[0x0f]	1326539	1			T22	6		T23	2		T24	3
valid_sources[0x10]	865834	1			T17	4		T22	7		T61	9
valid_sources[0x11]	894820	1			T17	3		T22	6		T23	2
valid_sources[0x12]	885547	1			T17	1		T22	6		T61	2
valid_sources[0x13]	864655	1			T15	1		T17	2		T22	7
valid_sources[0x14]	921240	1			T15	2		T17	1		T22	8
valid_sources[0x15]	868609	1			T17	3		T22	5		T23	1
valid_sources[0x16]	872687	1			T17	1		T22	7		T23	4
valid_sources[0x17]	917182	1			T17	3		T22	5		T23	1
valid_sources[0x18]	911731	1			T17	1		T19	1		T22	10
valid_sources[0x19]	933577	1			T17	2		T19	1		T22	8
valid_sources[0x1a]	1240765	1			T17	1		T22	7		T23	2
valid_sources[0x1b]	867451	1			T17	4		T22	4		T23	2
valid_sources[0x1c]	950474	1			T17	1		T22	3		T61	4
valid_sources[0x1d]	901193	1			T17	5		T22	8		T24	1
valid_sources[0x1e]	855725	1			T15	4		T17	1		T22	5
valid_sources[0x1f]	911073	1			T15	2		T17	3		T22	13
valid_sources[0x20]	873747	1			T17	1		T21	1		T22	3
valid_sources[0x21]	888791	1			T17	3		T20	126		T22	5
valid_sources[0x22]	1291713	1			T17	3		T22	5		T23	1
valid_sources[0x23]	1249319	1			T17	1		T22	6		T23	3
valid_sources[0x24]	912773	1			T17	1		T21	2		T22	3
valid_sources[0x25]	853156	1			T22	10		T61	3		T97	5
valid_sources[0x26]	877497	1			T17	1		T22	4		T61	6
valid_sources[0x27]	878699	1			T17	3		T19	1		T22	2
valid_sources[0x28]	905009	1			T17	2		T22	7		T61	1
valid_sources[0x29]	889551	1			T15	1		T17	1		T22	9
valid_sources[0x2a]	1273825	1			T15	2		T17	3		T22	11
valid_sources[0x2b]	897661	1			T17	1		T22	7		T23	1
valid_sources[0x2c]	931955	1			T22	9		T23	2		T61	8
valid_sources[0x2d]	900103	1			T15	2		T17	2		T19	1
valid_sources[0x2e]	893914	1			T17	2		T20	108		T22	5
valid_sources[0x2f]	928244	1			T17	2		T22	7		T23	2
valid_sources[0x30]	886174	1			T17	3		T22	3		T23	1
valid_sources[0x31]	896721	1			T17	1		T19	1		T22	8
valid_sources[0x32]	937611	1			T17	3		T22	16		T23	1
valid_sources[0x33]	881073	1			T17	3		T22	6		T23	3
valid_sources[0x34]	1235795	1			T17	5		T22	11		T61	6
valid_sources[0x35]	877564	1			T17	10		T22	4		T23	1
valid_sources[0x36]	925032	1			T14	6		T17	2		T22	3
valid_sources[0x37]	912587	1			T15	1		T17	4		T19	1
valid_sources[0x38]	934883	1			T15	2		T17	4		T22	3
valid_sources[0x39]	871675	1			T17	3		T22	11		T23	1
valid_sources[0x3a]	882143	1			T14	47		T17	1		T22	8
valid_sources[0x3b]	902253	1			T17	2		T22	1		T23	2
valid_sources[0x3c]	1217641	1			T22	4		T23	1		T61	7
valid_sources[0x3d]	863373	1			T17	1		T22	10		T61	5
valid_sources[0x3e]	914120	1			T14	26		T17	4		T22	11
valid_sources[0x3f]	875665	1			T17	2		T22	7		T61	7
valid_sources[0x40]	873783	1			T22	2		T61	8		T97	5
valid_sources[0x41]	924504	1			T17	1		T22	11		T23	1
valid_sources[0x42]	1273186	1			T17	4		T22	4		T61	7
valid_sources[0x43]	950401	1			T15	1		T22	3		T61	7
valid_sources[0x44]	866647	1			T15	1		T17	3		T20	19
valid_sources[0x45]	959017	1			T22	7		T23	1		T61	9
valid_sources[0x46]	877784	1			T17	2		T22	3		T61	4
valid_sources[0x47]	895072	1			T17	2		T22	7		T61	5
valid_sources[0x48]	1241240	1			T15	11		T17	2		T22	4
valid_sources[0x49]	1295712	1			T17	1		T22	8		T23	2
valid_sources[0x4a]	864019	1			T17	2		T22	3		T61	3
valid_sources[0x4b]	916365	1			T15	1		T17	3		T22	1
valid_sources[0x4c]	883938	1			T15	1		T22	5		T23	1
valid_sources[0x4d]	866713	1			T17	4		T22	6		T23	2
valid_sources[0x4e]	858435	1			T17	2		T22	2		T61	5
valid_sources[0x4f]	914556	1			T14	1		T17	3		T22	7
valid_sources[0x50]	915115	1			T15	1		T17	3		T20	49
valid_sources[0x51]	897578	1			T22	6		T61	3		T97	3
valid_sources[0x52]	1298281	1			T17	5		T22	13		T61	9
valid_sources[0x53]	887403	1			T15	1		T17	1		T22	8
valid_sources[0x54]	1083722	1			T17	2		T21	1		T22	2
valid_sources[0x55]	903485	1			T17	3		T22	3		T23	1
valid_sources[0x56]	858035	1			T14	7		T15	1		T17	1
valid_sources[0x57]	911254	1			T17	4		T22	6		T24	1
valid_sources[0x58]	894196	1			T15	2		T22	10		T61	14
valid_sources[0x59]	886270	1			T17	3		T22	7		T61	14
valid_sources[0x5a]	1265690	1			T17	3		T22	1		T61	3
valid_sources[0x5b]	919772	1			T17	2		T19	1		T22	3
valid_sources[0x5c]	885543	1			T17	3		T21	1		T22	12
valid_sources[0x5d]	879427	1			T17	2		T22	6		T61	7
valid_sources[0x5e]	922962	1			T17	2		T19	1		T22	5
valid_sources[0x5f]	1300655	1			T17	1		T20	16		T22	4
valid_sources[0x60]	923969	1			T22	7		T23	1		T61	7
valid_sources[0x61]	915682	1			T17	1		T19	1		T22	5
valid_sources[0x62]	910461	1			T17	3		T22	9		T23	1
valid_sources[0x63]	892796	1			T17	1		T22	5		T61	4
valid_sources[0x64]	957441	1			T17	1		T19	1		T22	5
valid_sources[0x65]	866028	1			T17	1		T22	4		T23	1
valid_sources[0x66]	909285	1			T17	2		T22	8		T23	1
valid_sources[0x67]	862262	1			T17	4		T22	8		T61	11
valid_sources[0x68]	914503	1			T17	1		T19	1		T21	1
valid_sources[0x69]	1071853	1			T17	1		T20	156		T22	7
valid_sources[0x6a]	903030	1			T17	3		T22	12		T61	3
valid_sources[0x6b]	887218	1			T17	3		T22	7		T23	2
valid_sources[0x6c]	905367	1			T17	1		T22	7		T23	3
valid_sources[0x6d]	969097	1			T17	1		T21	3		T22	7
valid_sources[0x6e]	883908	1			T17	5		T19	2		T22	3
valid_sources[0x6f]	1379571	1			T17	2		T22	11		T61	5
valid_sources[0x70]	892938	1			T17	1		T22	10		T61	4
valid_sources[0x71]	978808	1			T15	2		T17	3		T22	3
valid_sources[0x72]	950120	1			T17	2		T22	3		T23	1
valid_sources[0x73]	895250	1			T22	5		T23	2		T24	1
valid_sources[0x74]	1127035	1			T17	1		T22	1		T23	1
valid_sources[0x75]	915138	1			T17	4		T22	4		T23	2
valid_sources[0x76]	881686	1			T17	1		T19	1		T22	8
valid_sources[0x77]	1233698	1			T17	5		T19	1		T22	4
valid_sources[0x78]	867688	1			T17	1		T19	1		T22	7
valid_sources[0x79]	927071	1			T17	4		T18	24		T19	1
valid_sources[0x7a]	893886	1			T17	4		T22	8		T23	2
valid_sources[0x7b]	952374	1			T15	4		T17	2		T22	4
valid_sources[0x7c]	898066	1			T15	1		T17	4		T22	13
valid_sources[0x7d]	924344	1			T17	1		T19	1		T22	6
valid_sources[0x7e]	881459	1			T22	3		T61	4		T97	3
valid_sources[0x7f]	1251341	1			T17	1		T21	1		T22	10
valid_sources[0x80]	865860	1			T17	4		T22	8		T61	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47251302

1

T14

28

T15

13

T16

7

values[0x0]

all_enables

biggest_size

43777664

1

T14

22

T15

10

T16

5

values[0x1]

all_enables

biggest_size

40293442

1

T14

17

T15

14

T16

1