Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

174453551

1

T14

34

T15

61

T16

9

full_word

135677681

1

T14

67

T15

37

T16

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	310130802	1			T14	101		T15	98		T16	22
auto[TlIntgErrCmd]	144	1			T22	10		T61	11		T62	3
auto[TlIntgErrData]	138	1			T22	10		T61	7		T62	4
auto[TlIntgErrBoth]	148	1			T22	10		T61	12		T62	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120676564

1

T14

56

T15

27

T16

11

auto[1]

189454668

1

T14

45

T15

71

T16

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	71689646	1			T14	28		T15	14		T16	4
auto[TlIntgErrNone]	partial	auto[1]	102763510	1			T14	6		T15	47		T16	5
auto[TlIntgErrNone]	full_word	auto[0]	48986726	1			T14	28		T15	13		T16	7
auto[TlIntgErrNone]	full_word	auto[1]	86690920	1			T14	39		T15	24		T16	6
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T22	2		T61	2		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T22	8		T61	9		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T73	1		T75	1		T151	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T74	1		T73	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T22	4		T61	2		T62	4
auto[TlIntgErrData]	partial	auto[1]	68	1			T22	5		T61	4		T66	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T61	1		T153	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T22	1		T74	1		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T22	2		T61	4		T62	3
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T22	6		T61	7		T66	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T22	1		T66	1		T73	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T22	1		T61	1		T73	1