Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1496502124	37648019	0	0
intr_enable_rd_A	1496502124	13583	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1496502124	37648019	0	0
T15	1929	1	0	0
T16	999	0	0	0
T17	13099	526	0	0
T18	985	0	0	0
T19	694	0	0	0
T20	15397	1194	0	0
T21	972	0	0	0
T22	14314	5	0	0
T23	8397	292	0	0
T24	973	1	0	0
T25	0	166	0	0
T26	0	2	0	0
T27	0	512	0	0
T61	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1496502124	13583	0	0
T14	1629	18	0	0
T15	1929	0	0	0
T16	999	5	0	0
T17	13099	0	0	0
T18	985	0	0	0
T19	694	0	0	0
T20	15397	0	0	0
T21	972	0	0	0
T22	14314	0	0	0
T23	8397	0	0	0
T26	0	7	0	0
T62	0	87	0	0
T67	0	29	0	0
T68	0	14	0	0
T69	0	12	0	0
T70	0	388	0	0
T71	0	7	0	0
T72	0	95	0	0