Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

181823768

1

T14

2829

T16

1

T17

24

full_word

143183707

1

T13

877

T14

6362

T15

520

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	325007105	1			T13	877		T14	9191		T15	520
auto[TlIntgErrCmd]	137	1			T20	5		T34	10		T62	4
auto[TlIntgErrData]	123	1			T20	7		T34	7		T62	4
auto[TlIntgErrBoth]	110	1			T20	8		T34	3		T62	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127177236

1

T13

447

T14

4597

T15

272

auto[1]

197830239

1

T13

430

T14

4594

T15

248

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	74904788	1			T14	2330		T16	1		T17	8
auto[TlIntgErrNone]	partial	auto[1]	106918648	1			T14	499		T17	16		T18	478
auto[TlIntgErrNone]	full_word	auto[0]	52272279	1			T13	447		T14	2267		T15	272
auto[TlIntgErrNone]	full_word	auto[1]	90911390	1			T13	430		T14	4095		T15	248
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T20	3		T34	3		T62	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T20	2		T34	6		T62	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T62	1		T64	1		T63	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T34	1		T63	2		T92	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T20	4		T34	4		T62	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T20	2		T34	3		T62	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T20	1		T62	1		T93	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T67	1		T63	1		T94	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T20	3		T67	1		T63	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T20	5		T34	3		T62	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T92	1		T95	2		T96	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T64	1		T95	2		T96	1