Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1425434976	36457273	0	0
intr_enable_rd_A	1425434976	12125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1425434976	36457273	0	0
T18	3125	447	0	0
T19	6446	0	0	0
T20	10744	6	0	0
T21	1270	0	0	0
T22	7096	442	0	0
T23	15210	847	0	0
T24	1321	0	0	0
T25	0	439	0	0
T26	0	687	0	0
T27	0	1066	0	0
T32	15992	0	0	0
T33	9441	0	0	0
T34	9438	3	0	0
T62	0	6	0	0
T64	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1425434976	12125	0	0
T14	98201	686	0	0
T15	5293	22	0	0
T16	1716	0	0	0
T17	1078	0	0	0
T18	3125	0	0	0
T19	6446	0	0	0
T20	10744	81	0	0
T21	1270	0	0	0
T22	7096	0	0	0
T24	1321	0	0	0
T26	0	3	0	0
T29	0	8	0	0
T31	0	5	0	0
T32	0	293	0	0
T48	0	5	0	0
T65	0	23	0	0
T66	0	9	0	0