Unified Coverage Report :: Module :: sha2_pad

Module : sha2_pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.50	95.70	88.89		90.91	86.49

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha2.u_pad	100.00	100.00	100.00		100.00	100.00

---

Module Instance : tb.dut.u_sha2.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00		u_sha2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : sha2_pad

	Line No.	Total	Covered	Percent
TOTAL		93	89	95.70
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	6	6	100.00
ALWAYS	71	10	10	100.00
ALWAYS	137	3	3	100.00
ALWAYS	146	65	61	93.85
ALWAYS	300	6	6	100.00
CONT_ASSIGN	310	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
			MISSING_ELSE
71	1	1
73	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
92	1	1
96	1	1
100	1	1
137	1	1
138	1	1
140	1	1
146	1	1
147	1	1
148	1	1
149	1	1
151	1	1
153	1	1
155	1	1
156	1	1
158	1	1
159	1	1
161	1	1
163	1	1
168	1	1
170	1	1
172	1	1
173	1	1
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
182	1	1
183	1	1
185	1	1
186	1	1
187	1	1
189	1	1
191	1	1
192	1	1
193	1	1
195	1	1
200	1	1
202	1	1
203	1	1
206	1	1
207	1	1
208	1	1
212	1	1
213	1	1
214	1	1
216	1	1
217	1	1
246	1	1
247	1	1
249	1	1
250	1	1
252	1	1
253	1	1
255	1	1
258	1	1
263	1	1
264	1	1
266	1	1
267	1	1
269	1	1
271	0	1
273	0	1
278	1	1
279	1	1
281	1	1
282	1	1
284	1	1
286	0	1
288	0	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
			MISSING_ELSE
310	1	1

---

Cond Coverage for Module : sha2_pad

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       48
 EXPRESSION (tx_count[8:0] == 9'h1a0)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       55
 EXPRESSION (hash_done || hash_start)
             ----1----    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       158
 EXPRESSION (sha_en && hash_start)
             ---1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       170
 EXPRESSION (fifo_partial && fifo_rvalid)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       183
 EXPRESSION (tx_count == message_length)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       203
 EXPRESSION (shaf_rready && ((|message_length[4:3])))
             -----1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       206
 EXPRESSION (shaf_rready && txcnt_eq_1a0)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T6,T8

 LINE       212
 EXPRESSION (shaf_rready && ((!txcnt_eq_1a0)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       310
 EXPRESSION (hash_process_flag && (st_q == StIdle))
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       310
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : sha2_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	161	Covered	T14
StIdle	151	Covered	T14
StLenHi	207	Covered	T14
StLenLo	267	Covered	T14
StPad00	213	Covered	T14
StPad80	176	Covered	T14

transitions	Line No.	Covered	Tests
StFifoReceive->StIdle	151	Covered	T14
StFifoReceive->StPad80	176	Covered	T14
StIdle->StFifoReceive	161	Covered	T14
StLenHi->StIdle	151	Not Covered
StLenHi->StLenLo	267	Covered	T14
StLenLo->StIdle	151	Covered	T14
StPad00->StIdle	151	Covered	T14
StPad00->StLenHi	253	Covered	T14
StPad80->StIdle	151	Covered	T14
StPad80->StLenHi	207	Covered	T14
StPad80->StPad00	213	Covered	T14

---

Branch Coverage for Module : sha2_pad

	Line No.	Total	Covered	Percent
Branches		37	32	86.49
IF	51	4	4	100.00
CASE	71	10	8	80.00
IF	137	2	2	100.00
CASE	153	17	14	82.35
IF	300	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if ((!rst_ni))
-2-:	53	if (hash_process)
-3-:	55	if ((hash_done || hash_start))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	case (sel_data)
-2-:	82	case (message_length[4:3])

Branches:

-1-	-2-	Status	Tests
FifoIn	-	Covered	T1,T2,T3
Pad80	2'b00	Covered	T1,T4,T5
Pad80	2'b01	Covered	T4,T5,T6
Pad80	2'b10	Covered	T5,T6,T8
Pad80	2'b11	Covered	T1,T2,T5
Pad80	default	Not Covered
Pad00	-	Covered	T1,T2,T4
LenHi	-	Covered	T1,T2,T4
LenLo	-	Covered	T1,T2,T4
default	-	Not Covered

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (st_q)
-2-:	158	if ((sha_en && hash_start))
-3-:	170	if ((fifo_partial && fifo_rvalid))
-4-:	177	if ((!hash_process_flag))
-5-:	183	if ((tx_count == message_length))
-6-:	206	if ((shaf_rready && txcnt_eq_1a0))
-7-:	212	if ((shaf_rready && (!txcnt_eq_1a0)))
-8-:	249	if (shaf_rready)
-9-:	252	if (txcnt_eq_1a0)
-10-:	266	if (shaf_rready)
-11-:	281	if (shaf_rready)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T1,T4,T5
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T1,T4,T5
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T5,T6,T8
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T4
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T1,T4,T5
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T4
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T4
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T5,T6,T8
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StLenHi	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StLenLo	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	300	if ((!rst_ni))
-2-:	302	if (hash_start)
-3-:	304	if (inc_txcount)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha2.u_pad

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	6	6	100.00
ALWAYS	71	10	10	100.00
ALWAYS	137	3	3	100.00
ALWAYS	146	61	61	100.00
ALWAYS	300	6	6	100.00
CONT_ASSIGN	310	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
			MISSING_ELSE
71	1	1
73	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
			Exclude Annotation: VC_COV_UNR
92	1	1
96	1	1
100	1	1
			Exclude Annotation: VC_COV_UNR
137	1	1
138	1	1
140	1	1
146	1	1
147	1	1
148	1	1
149	1	1
151	1	1
153	1	1
155	1	1
156	1	1
158	1	1
159	1	1
161	1	1
163	1	1
168	1	1
170	1	1
172	1	1
173	1	1
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
182	1	1
183	1	1
185	1	1
186	1	1
187	1	1
189	1	1
191	1	1
192	1	1
193	1	1
195	1	1
200	1	1
202	1	1
203	1	1
206	1	1
207	1	1
208	1	1
212	1	1
213	1	1
214	1	1
216	1	1
217	1	1
246	1	1
247	1	1
249	1	1
250	1	1
252	1	1
253	1	1
255	1	1
258	1	1
263	1	1
264	1	1
266	1	1
267	1	1
269	1	1
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
278	1	1
279	1	1
281	1	1
282	1	1
284	1	1
286		excluded
			Exclude Annotation: VC_COV_UNR
288		excluded
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
			MISSING_ELSE
310	1	1

---

Cond Coverage for Instance : tb.dut.u_sha2.u_pad

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       48
 EXPRESSION (tx_count[8:0] == 9'h1a0)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       55
 EXPRESSION (hash_done || hash_start)
             ----1----    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       158
 EXPRESSION (sha_en && hash_start)
             ---1--    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       170
 EXPRESSION (fifo_partial && fifo_rvalid)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       183
 EXPRESSION (tx_count == message_length)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       203
 EXPRESSION (shaf_rready && ((|message_length[4:3])))
             -----1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       206
 EXPRESSION (shaf_rready && txcnt_eq_1a0)
             -----1-----    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T6,T8

 LINE       212
 EXPRESSION (shaf_rready && ((!txcnt_eq_1a0)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T5
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       310
 EXPRESSION (hash_process_flag && (st_q == StIdle))
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       310
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha2.u_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	161	Covered	T14
StIdle	151	Covered	T14
StLenHi	207	Covered	T14
StLenLo	267	Covered	T14
StPad00	213	Covered	T14
StPad80	176	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
StFifoReceive->StIdle	151	Covered	T14
StFifoReceive->StPad80	176	Covered	T14
StIdle->StFifoReceive	161	Covered	T14
StLenHi->StIdle	151	Excluded		VC_COV_UNR
StLenHi->StLenLo	267	Covered	T14
StLenLo->StIdle	151	Covered	T14
StPad00->StIdle	151	Covered	T14
StPad00->StLenHi	253	Covered	T14
StPad80->StIdle	151	Excluded	T14	VC_COV_UNR
StPad80->StLenHi	207	Covered	T14
StPad80->StPad00	213	Covered	T14

---

Branch Coverage for Instance : tb.dut.u_sha2.u_pad

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
IF	51	4	4	100.00
CASE	71	8	8	100.00
IF	137	2	2	100.00
CASE	153	14	14	100.00
IF	300	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if ((!rst_ni))
-2-:	53	if (hash_process)
-3-:	55	if ((hash_done || hash_start))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	case (sel_data)
-2-:	82	case (message_length[4:3])

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
FifoIn	-	Covered	T1,T2,T3
Pad80	2'b00	Covered	T1,T4,T5
Pad80	2'b01	Covered	T4,T5,T6
Pad80	2'b10	Covered	T5,T6,T8
Pad80	2'b11	Covered	T1,T2,T5
Pad80	default	Excluded		VC_COV_UNR
Pad00	-	Covered	T1,T2,T4
LenHi	-	Covered	T1,T2,T4
LenLo	-	Covered	T1,T2,T4
default	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (st_q)
-2-:	158	if ((sha_en && hash_start))
-3-:	170	if ((fifo_partial && fifo_rvalid))
-4-:	177	if ((!hash_process_flag))
-5-:	183	if ((tx_count == message_length))
-6-:	206	if ((shaf_rready && txcnt_eq_1a0))
-7-:	212	if ((shaf_rready && (!txcnt_eq_1a0)))
-8-:	249	if (shaf_rready)
-9-:	252	if (txcnt_eq_1a0)
-10-:	266	if (shaf_rready)
-11-:	281	if (shaf_rready)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests	Exclude Annotation
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T1,T4,T5
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T1,T4,T5
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T5,T6,T8
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T4
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T1,T4,T5
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T4
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T4
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T5,T6,T8
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
StLenHi	-	-	-	-	-	-	-	-	0	-	Excluded		VC_COV_UNR
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StLenLo	-	-	-	-	-	-	-	-	-	0	Excluded		VC_COV_UNR
default	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	300	if ((!rst_ni))
-2-:	302	if (hash_start)
-3-:	304	if (inc_txcount)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3