Unified Coverage Report :: Module :: sha2

Module : sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.35	96.19	88.00		88.89	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha2	100.00	100.00	100.00		100.00	100.00

---

Module Instance : tb.dut.u_sha2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	100.00	100.00	100.00		100.00	100.00

Line Coverage for Module : sha2

	Line No.	Total	Covered	Percent
TOTAL		105	101	96.19
ALWAYS	58	12	12	100.00
ALWAYS	94	9	9	100.00
ALWAYS	109	13	13	100.00
ALWAYS	130	8	8	100.00
ALWAYS	145	6	6	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	3	3	100.00
ALWAYS	170	3	3	100.00
ALWAYS	178	24	22	91.67
ALWAYS	237	3	3	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	247	20	18	90.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	321	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
66	1	1
67	1	1
68	1	1
86	1	1
88	1	1
			MISSING_ELSE
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
102	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
113	1	1
115	1	1
116	1	1
117	1	1
119	1	1
120	1	1
121	1	1
122	1	1
123	1	1
			MISSING_ELSE
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
			MISSING_ELSE
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
157	2	2
158	1	1
170	1	1
171	1	1
173	1	1
178	1	1
179	1	1
180	1	1
182	1	1
184	1	1
185	1	1
187	1	1
192	1	1
193	0	1
194	0	1
195	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
210	1	1
211	1	1
213	1	1
214	1	1
215	1	1
217	1	1
237	1	1
238	1	1
240	1	1
244	1	1
247	1	1
248	1	1
250	1	1
251	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
264	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
278	1	1
279	1	1
280	0	1
281	0	1
283	1	1
294	1	1
321	1	1

---

Cond Coverage for Module : sha2

	Total	Covered	Percent
Conditions	25	22	88.00
Logical	25	22	88.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       119
 EXPRESSION (((!sha_en)) || clear_digest)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (w_index == 4'd15)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       210
 EXPRESSION (msg_feed_complete && complete_one_chunk)
             --------1--------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       255
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       279
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       294
 EXPRESSION (round == 6'd63)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       321
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_start)))
             -----------1-----------    ----------2----------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	178	Covered	T14
FifoLoadFromFifo	185	Covered	T14
FifoWait	200	Covered	T14

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	185	Covered	T14
FifoLoadFromFifo->FifoIdle	178	Covered	T14
FifoLoadFromFifo->FifoWait	200	Covered	T14
FifoWait->FifoIdle	178	Covered	T14
FifoWait->FifoLoadFromFifo	215	Covered	T14

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	3	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	257	Covered	T14
ShaIdle	259	Covered	T14
ShaUpdateDigest	271	Covered	T14

transitions	Line No.	Covered	Tests
ShaCompress->ShaUpdateDigest	271	Covered	T14
ShaIdle->ShaCompress	257	Covered	T14
ShaUpdateDigest->ShaCompress	281	Not Covered
ShaUpdateDigest->ShaIdle	283	Covered	T14

---

Branch Coverage for Module : sha2

	Line No.	Total	Covered	Percent
Branches		52	48	92.31
IF	58	7	7	100.00
IF	94	5	5	100.00
IF	109	6	6	100.00
IF	130	5	5	100.00
IF	145	4	4	100.00
IF	157	2	2	100.00
IF	170	2	2	100.00
CASE	182	10	8	80.00
IF	237	2	2	100.00
CASE	253	9	7	77.78

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (wipe_secret)
-3-:	62	if ((!sha_en))
-4-:	64	if (((!run_hash) && update_w_from_fifo))
-5-:	67	if (calculate_next_w)
-6-:	86	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T5,T6,T35
0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	1	-	Covered	T1,T2,T4
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if (wipe_secret)
-3-:	100	if (init_hash)
-4-:	102	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T5,T6,T35
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	if ((!rst_ni))
-2-:	111	if (wipe_secret)
-3-:	115	if (hash_start)
-4-:	119	if (((!sha_en) || clear_digest))
-5-:	121	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T5,T6,T35
0	0	1	-	-	Covered	T1,T2,T4
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	130	if ((!rst_ni))
-2-:	132	if ((!sha_en))
-3-:	134	if (run_hash)
-4-:	135	if ((round == 6'((unsigned'((hmac_pkg::NumRound - 1))))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T1,T2,T4
0	0	1	0	Covered	T1,T2,T4
0	0	0	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	145	if ((!rst_ni))
-2-:	147	if ((!sha_en))
-3-:	149	if (update_w_from_fifo)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	case (fifo_st_q)
-2-:	184	if (hash_start)
-3-:	192	if ((!sha_en))
-4-:	195	if ((!shaf_rvalid))
-5-:	199	if ((w_index == 4'd15))
-6-:	210	if ((msg_feed_complete && complete_one_chunk))
-7-:	214	if (complete_one_chunk)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
FifoIdle	1	-	-	-	-	-	Covered	T1,T2,T4
FifoIdle	0	-	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	-	Not Covered
FifoLoadFromFifo	-	0	1	-	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	1	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	0	-	-	Covered	T1,T2,T4
FifoWait	-	-	-	-	1	-	Covered	T1,T2,T4
FifoWait	-	-	-	-	0	1	Covered	T1,T2,T4
FifoWait	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	237	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	case (sha_st_q)
-2-:	255	if ((fifo_st_q == FifoWait))
-3-:	266	if ((round < 6'h30))
-4-:	270	if (complete_one_chunk)
-5-:	279	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T2,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T4
ShaCompress	-	0	-	-	Covered	T1,T2,T4
ShaCompress	-	-	1	-	Covered	T1,T2,T4
ShaCompress	-	-	0	-	Covered	T1,T2,T4
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_sha2

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
ALWAYS	58	12	12	100.00
ALWAYS	94	9	9	100.00
ALWAYS	109	13	13	100.00
ALWAYS	130	8	8	100.00
ALWAYS	145	6	6	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	3	3	100.00
ALWAYS	170	3	3	100.00
ALWAYS	178	22	22	100.00
ALWAYS	237	3	3	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	247	18	18	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	321	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
66	1	1
67	1	1
68	1	1
86	1	1
88	1	1
			MISSING_ELSE
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
102	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
113	1	1
115	1	1
116	1	1
117	1	1
119	1	1
120	1	1
121	1	1
122	1	1
123	1	1
			MISSING_ELSE
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
			MISSING_ELSE
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
157	2	2
158	1	1
170	1	1
171	1	1
173	1	1
178	1	1
179	1	1
180	1	1
182	1	1
184	1	1
185	1	1
187	1	1
192	1	1
193		excluded
			Exclude Annotation: VC_COV_UNR
194		excluded
			Exclude Annotation: VC_COV_UNR
195	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
210	1	1
211	1	1
213	1	1
214	1	1
215	1	1
217	1	1
			Exclude Annotation: VC_COV_UNR
237	1	1
238	1	1
240	1	1
244	1	1
247	1	1
248	1	1
250	1	1
251	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
264	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
278	1	1
279	1	1
280		excluded
			Exclude Annotation: VC_COV_UNR
281		excluded
			Exclude Annotation: VC_COV_UNR
283	1	1
			Exclude Annotation: VC_COV_UNR
294	1	1
321	1	1

---

Cond Coverage for Instance : tb.dut.u_sha2

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       119
 EXPRESSION (((!sha_en)) || clear_digest)
             -----1-----    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T4
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (w_index == 4'd15)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       210
 EXPRESSION (msg_feed_complete && complete_one_chunk)
             --------1--------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       255
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       279
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       294
 EXPRESSION (round == 6'd63)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       321
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_start)))
             -----------1-----------    ----------2----------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	178	Covered	T14
FifoLoadFromFifo	185	Covered	T14
FifoWait	200	Covered	T14

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	185	Covered	T14
FifoLoadFromFifo->FifoIdle	178	Covered	T14
FifoLoadFromFifo->FifoWait	200	Covered	T14
FifoWait->FifoIdle	178	Covered	T14
FifoWait->FifoLoadFromFifo	215	Covered	T14

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	3	3	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	257	Covered	T14
ShaIdle	259	Covered	T14
ShaUpdateDigest	271	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
ShaCompress->ShaUpdateDigest	271	Covered	T14
ShaIdle->ShaCompress	257	Covered	T14
ShaUpdateDigest->ShaCompress	281	Excluded		VC_COV_UNR
ShaUpdateDigest->ShaIdle	283	Covered	T14

---

Branch Coverage for Instance : tb.dut.u_sha2

	Line No.	Total	Covered	Percent
Branches		48	48	100.00
IF	58	7	7	100.00
IF	94	5	5	100.00
IF	109	6	6	100.00
IF	130	5	5	100.00
IF	145	4	4	100.00
IF	157	2	2	100.00
IF	170	2	2	100.00
CASE	182	8	8	100.00
IF	237	2	2	100.00
CASE	253	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (wipe_secret)
-3-:	62	if ((!sha_en))
-4-:	64	if (((!run_hash) && update_w_from_fifo))
-5-:	67	if (calculate_next_w)
-6-:	86	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T5,T6,T35
0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	1	-	Covered	T1,T2,T4
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if (wipe_secret)
-3-:	100	if (init_hash)
-4-:	102	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T5,T6,T35
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	if ((!rst_ni))
-2-:	111	if (wipe_secret)
-3-:	115	if (hash_start)
-4-:	119	if (((!sha_en) || clear_digest))
-5-:	121	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T5,T6,T35
0	0	1	-	-	Covered	T1,T2,T4
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	130	if ((!rst_ni))
-2-:	132	if ((!sha_en))
-3-:	134	if (run_hash)
-4-:	135	if ((round == 6'((unsigned'((hmac_pkg::NumRound - 1))))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T1,T2,T4
0	0	1	0	Covered	T1,T2,T4
0	0	0	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	145	if ((!rst_ni))
-2-:	147	if ((!sha_en))
-3-:	149	if (update_w_from_fifo)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	case (fifo_st_q)
-2-:	184	if (hash_start)
-3-:	192	if ((!sha_en))
-4-:	195	if ((!shaf_rvalid))
-5-:	199	if ((w_index == 4'd15))
-6-:	210	if ((msg_feed_complete && complete_one_chunk))
-7-:	214	if (complete_one_chunk)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests	Exclude Annotation
FifoIdle	1	-	-	-	-	-	Covered	T1,T2,T4
FifoIdle	0	-	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	-	Excluded		VC_COV_UNR
FifoLoadFromFifo	-	0	1	-	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	1	-	-	Covered	T1,T2,T4
FifoLoadFromFifo	-	0	0	0	-	-	Covered	T1,T2,T4
FifoWait	-	-	-	-	1	-	Covered	T1,T2,T4
FifoWait	-	-	-	-	0	1	Covered	T1,T2,T4
FifoWait	-	-	-	-	0	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	237	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	case (sha_st_q)
-2-:	255	if ((fifo_st_q == FifoWait))
-3-:	266	if ((round < 6'h30))
-4-:	270	if (complete_one_chunk)
-5-:	279	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
ShaIdle	1	-	-	-	Covered	T1,T2,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T4
ShaCompress	-	0	-	-	Covered	T1,T2,T4
ShaCompress	-	-	1	-	Covered	T1,T2,T4
ShaCompress	-	-	0	-	Covered	T1,T2,T4
ShaUpdateDigest	-	-	-	1	Excluded		VC_COV_UNR
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	Excluded		VC_COV_UNR