Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

162614710

1

T12

26

T13

1632

T14

302

full_word

126224063

1

T12

71

T13

626

T14

761

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	288838383	1			T12	97		T13	2258		T14	1043
auto[TlIntgErrCmd]	127	1			T14	6		T17	3		T60	9
auto[TlIntgErrData]	140	1			T14	4		T17	3		T60	12
auto[TlIntgErrBoth]	123	1			T14	10		T17	4		T60	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112153730

1

T12

51

T13

772

T14

570

auto[1]

176685043

1

T12

46

T13

1486

T14

493

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	66719571	1			T12	21		T13	597		T14	243
auto[TlIntgErrNone]	partial	auto[1]	95894780	1			T12	5		T13	1035		T14	41
auto[TlIntgErrNone]	full_word	auto[0]	45433971	1			T12	30		T13	175		T14	320
auto[TlIntgErrNone]	full_word	auto[1]	80790061	1			T12	41		T13	451		T14	439
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T14	2		T17	2		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T14	4		T17	1		T60	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T61	1		T120	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T60	2		T123	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T14	1		T17	1		T60	6
auto[TlIntgErrData]	partial	auto[1]	66	1			T14	3		T17	1		T60	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T60	1		T61	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T17	1		T60	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T14	4		T17	1		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T14	4		T17	3		T60	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T120	1		T126	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T14	2		T119	1		T120	1