Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

168652909

1

T12

25

T13

433

T14

28

full_word

131565211

1

T12

15

T13

1127

T14

71

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	300217720	1			T12	40		T13	1530		T14	99
auto[TlIntgErrCmd]	138	1			T13	5		T15	9		T59	9
auto[TlIntgErrData]	119	1			T13	15		T15	7		T59	5
auto[TlIntgErrBoth]	143	1			T13	10		T15	14		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116765533

1

T12

20

T13

836

T14

54

auto[1]

183452587

1

T12

20

T13

724

T14

45

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	69549949	1			T12	8		T13	344		T14	25
auto[TlIntgErrNone]	partial	auto[1]	99102594	1			T12	17		T13	61		T14	3
auto[TlIntgErrNone]	full_word	auto[0]	47215411	1			T12	12		T13	475		T14	29
auto[TlIntgErrNone]	full_word	auto[1]	84349766	1			T12	3		T13	650		T14	42
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T13	3		T15	3		T59	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T13	2		T15	5		T59	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T129	3		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T15	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T13	7		T15	3		T59	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T13	7		T15	3		T59	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T13	1		T59	1		T70	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T15	1		T67	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T13	6		T15	4		T59	4
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T13	3		T15	9		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T15	1		T67	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T13	1		T70	2		T131	1