Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1422793403	36257985	0	0
intr_enable_rd_A	1422793403	12744	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422793403	36257985	0	0
T13	13004	5	0	0
T14	917	0	0	0
T15	14860	10	0	0
T16	995142	298227	0	0
T17	1755	0	0	0
T18	1091	0	0	0
T19	97099	0	0	0
T20	1827	1	0	0
T21	12633	598	0	0
T22	2232	3	0	0
T23	0	295	0	0
T24	0	36	0	0
T25	0	669	0	0
T59	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422793403	12744	0	0
T12	915	18	0	0
T13	13004	0	0	0
T14	917	0	0	0
T15	14860	235	0	0
T16	995142	178	0	0
T17	1755	24	0	0
T18	1091	0	0	0
T19	97099	668	0	0
T20	1827	0	0	0
T21	12633	0	0	0
T62	0	1	0	0
T63	0	4	0	0
T64	0	5	0	0
T65	0	39	0	0
T66	0	42	0	0