Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	103753095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117225493

1

T12

22

T13

23

T14

1141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87045725	1			T12	28		T13	29		T14	834
values[0x0]	62192356	1			T12	15		T13	18		T14	357
values[0x1]	71740507	1			T12	13		T13	11		T14	373

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75726809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145251779

1

T12

28

T13

26

T14

1259

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	834721	1			T14	10		T15	2		T16	3
valid_sources[0x01]	1123660	1			T14	3		T15	1		T16	4
valid_sources[0x02]	808524	1			T14	2		T15	3		T16	3
valid_sources[0x03]	796824	1			T14	2		T15	3		T16	2
valid_sources[0x04]	835827	1			T14	6		T15	1		T16	4
valid_sources[0x05]	838872	1			T14	5		T15	4		T16	6
valid_sources[0x06]	843921	1			T14	9		T15	3		T16	4
valid_sources[0x07]	786577	1			T14	1		T15	4		T16	9
valid_sources[0x08]	794902	1			T14	1		T15	1		T16	6
valid_sources[0x09]	818709	1			T14	1		T16	1		T17	2
valid_sources[0x0a]	828394	1			T14	7		T15	2		T16	2
valid_sources[0x0b]	875000	1			T14	10		T15	2		T16	4
valid_sources[0x0c]	1160473	1			T14	2		T15	3		T16	5
valid_sources[0x0d]	850020	1			T14	2		T15	2		T16	4
valid_sources[0x0e]	834492	1			T14	5		T15	1		T16	3
valid_sources[0x0f]	819989	1			T14	9		T15	2		T16	6
valid_sources[0x10]	868492	1			T12	1		T14	8		T15	1
valid_sources[0x11]	846996	1			T12	1		T14	4		T15	1
valid_sources[0x12]	1196328	1			T14	6		T15	2		T16	1
valid_sources[0x13]	826207	1			T14	11		T15	2		T16	4
valid_sources[0x14]	1192291	1			T14	10		T15	3		T16	6
valid_sources[0x15]	851013	1			T14	3		T15	3		T16	2
valid_sources[0x16]	818964	1			T14	2		T15	1		T16	3
valid_sources[0x17]	810014	1			T14	7		T15	2		T16	2
valid_sources[0x18]	793673	1			T12	2		T13	2		T14	6
valid_sources[0x19]	796262	1			T14	11		T15	7		T16	1
valid_sources[0x1a]	837494	1			T13	2		T14	6		T15	2
valid_sources[0x1b]	849129	1			T14	3		T15	1		T16	4
valid_sources[0x1c]	954980	1			T14	1		T15	3		T16	3
valid_sources[0x1d]	811740	1			T14	7		T15	1		T16	4
valid_sources[0x1e]	875391	1			T14	12		T15	4		T16	3
valid_sources[0x1f]	810317	1			T14	4		T15	4		T16	2
valid_sources[0x20]	796758	1			T14	3		T15	1		T17	1
valid_sources[0x21]	933023	1			T14	8		T17	3		T20	2
valid_sources[0x22]	813501	1			T14	10		T15	2		T16	2
valid_sources[0x23]	891506	1			T14	7		T15	1		T16	5
valid_sources[0x24]	800085	1			T14	6		T15	5		T16	8
valid_sources[0x25]	817366	1			T15	3		T16	3		T17	6
valid_sources[0x26]	853999	1			T14	4		T15	3		T16	3
valid_sources[0x27]	799513	1			T14	5		T15	3		T16	4
valid_sources[0x28]	829449	1			T14	3		T15	2		T17	2
valid_sources[0x29]	1142153	1			T14	9		T15	2		T16	4
valid_sources[0x2a]	804624	1			T14	5		T15	1		T16	2
valid_sources[0x2b]	862879	1			T14	1		T15	3		T16	2
valid_sources[0x2c]	796195	1			T14	4		T16	2		T17	4
valid_sources[0x2d]	826528	1			T14	10		T15	2		T16	3
valid_sources[0x2e]	813367	1			T14	9		T16	5		T17	6
valid_sources[0x2f]	818461	1			T14	10		T15	1		T16	2
valid_sources[0x30]	814536	1			T14	4		T15	4		T16	2
valid_sources[0x31]	826728	1			T12	2		T14	9		T15	2
valid_sources[0x32]	1220632	1			T14	4		T15	3		T16	2
valid_sources[0x33]	854325	1			T14	5		T15	3		T16	4
valid_sources[0x34]	811248	1			T14	8		T15	6		T16	2
valid_sources[0x35]	824686	1			T14	6		T15	2		T16	2
valid_sources[0x36]	825632	1			T14	2		T15	2		T16	2
valid_sources[0x37]	818333	1			T14	3		T15	2		T16	2
valid_sources[0x38]	814498	1			T14	9		T15	2		T16	5
valid_sources[0x39]	830516	1			T14	2		T15	1		T16	3
valid_sources[0x3a]	791329	1			T14	5		T15	4		T16	7
valid_sources[0x3b]	788486	1			T14	4		T15	5		T16	7
valid_sources[0x3c]	766601	1			T14	3		T15	3		T16	5
valid_sources[0x3d]	814476	1			T14	2		T15	5		T16	5
valid_sources[0x3e]	821241	1			T14	7		T15	1		T16	3
valid_sources[0x3f]	834375	1			T14	5		T15	2		T16	1
valid_sources[0x40]	806442	1			T14	3		T15	2		T16	2
valid_sources[0x41]	825120	1			T14	5		T15	1		T16	3
valid_sources[0x42]	784686	1			T14	8		T16	7		T17	2
valid_sources[0x43]	803970	1			T12	1		T14	5		T15	1
valid_sources[0x44]	809044	1			T13	9		T14	12		T15	2
valid_sources[0x45]	803147	1			T14	7		T15	2		T16	4
valid_sources[0x46]	813329	1			T14	6		T15	3		T16	2
valid_sources[0x47]	831163	1			T12	1		T14	8		T16	3
valid_sources[0x48]	863307	1			T14	5		T15	4		T16	3
valid_sources[0x49]	815253	1			T12	2		T14	7		T15	4
valid_sources[0x4a]	802761	1			T12	1		T14	5		T15	2
valid_sources[0x4b]	835286	1			T15	1		T16	3		T17	2
valid_sources[0x4c]	821987	1			T14	6		T16	1		T17	3
valid_sources[0x4d]	873710	1			T12	2		T14	2		T15	5
valid_sources[0x4e]	822791	1			T14	5		T15	2		T16	3
valid_sources[0x4f]	822174	1			T14	6		T15	3		T16	1
valid_sources[0x50]	823393	1			T13	1		T14	7		T15	3
valid_sources[0x51]	803543	1			T14	1		T15	7		T16	3
valid_sources[0x52]	811032	1			T14	3		T15	2		T16	4
valid_sources[0x53]	840577	1			T14	7		T15	2		T16	5
valid_sources[0x54]	798310	1			T14	9		T15	2		T16	3
valid_sources[0x55]	837539	1			T14	9		T15	2		T16	1
valid_sources[0x56]	787340	1			T14	12		T15	1		T16	2
valid_sources[0x57]	823852	1			T14	8		T15	2		T16	1
valid_sources[0x58]	791941	1			T14	5		T15	2		T16	9
valid_sources[0x59]	816498	1			T14	11		T15	2		T16	3
valid_sources[0x5a]	1136725	1			T12	1		T14	7		T15	2
valid_sources[0x5b]	802829	1			T14	4		T16	4		T17	2
valid_sources[0x5c]	788380	1			T14	6		T15	4		T16	3
valid_sources[0x5d]	798288	1			T14	7		T15	1		T17	3
valid_sources[0x5e]	846708	1			T14	5		T15	2		T16	6
valid_sources[0x5f]	854738	1			T14	3		T15	3		T16	1
valid_sources[0x60]	1625058	1			T14	2		T15	2		T17	1
valid_sources[0x61]	828537	1			T14	5		T15	3		T16	2
valid_sources[0x62]	837500	1			T15	3		T16	3		T17	2
valid_sources[0x63]	827136	1			T14	3		T15	2		T16	7
valid_sources[0x64]	819997	1			T14	10		T15	5		T16	3
valid_sources[0x65]	796137	1			T14	4		T15	1		T16	2
valid_sources[0x66]	849683	1			T12	6		T14	2		T15	5
valid_sources[0x67]	862379	1			T14	13		T15	1		T16	2
valid_sources[0x68]	860644	1			T15	2		T16	2		T20	8
valid_sources[0x69]	809181	1			T12	1		T14	7		T15	2
valid_sources[0x6a]	872666	1			T14	8		T15	1		T16	4
valid_sources[0x6b]	853914	1			T14	2		T15	1		T16	4
valid_sources[0x6c]	852027	1			T14	5		T15	3		T16	3
valid_sources[0x6d]	822123	1			T14	13		T15	2		T16	2
valid_sources[0x6e]	828726	1			T14	10		T16	6		T17	3
valid_sources[0x6f]	869425	1			T14	7		T15	3		T16	5
valid_sources[0x70]	783637	1			T14	8		T15	1		T17	2
valid_sources[0x71]	818633	1			T14	9		T15	1		T16	1
valid_sources[0x72]	830044	1			T12	1		T14	8		T15	3
valid_sources[0x73]	1064187	1			T14	5		T15	2		T16	6
valid_sources[0x74]	783111	1			T14	2		T15	2		T16	3
valid_sources[0x75]	1538818	1			T14	7		T15	2		T16	5
valid_sources[0x76]	855699	1			T14	7		T15	2		T16	1
valid_sources[0x77]	810365	1			T14	2		T15	2		T16	2
valid_sources[0x78]	830533	1			T14	6		T15	3		T16	8
valid_sources[0x79]	851844	1			T13	5		T14	6		T15	2
valid_sources[0x7a]	804897	1			T12	1		T14	3		T15	2
valid_sources[0x7b]	839503	1			T14	17		T16	2		T17	1
valid_sources[0x7c]	1104258	1			T14	3		T15	3		T16	9
valid_sources[0x7d]	871752	1			T14	4		T15	1		T16	5
valid_sources[0x7e]	838249	1			T13	11		T14	8		T15	2
valid_sources[0x7f]	803861	1			T14	9		T15	2		T16	2
valid_sources[0x80]	833278	1			T14	5		T15	1		T16	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41862161

1

T12

13

T13

16

T14

494

values[0x0]

all_enables

biggest_size

39230624

1

T12

7

T13

4

T14

323

values[0x1]

all_enables

biggest_size

36132708

1

T12

2

T13

3

T14

324