Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

154296347

1

T12

34

T13

35

T14

429

full_word

121045391

1

T12

22

T13

23

T14

1142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	275341348	1			T12	56		T13	58		T14	1541
auto[TlIntgErrCmd]	141	1			T14	6		T63	9		T64	8
auto[TlIntgErrData]	116	1			T14	13		T63	4		T64	5
auto[TlIntgErrBoth]	133	1			T14	11		T63	7		T64	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107023514

1

T12

28

T13

29

T14

837

auto[1]

168318224

1

T12

28

T13

29

T14

734

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	63639213	1			T12	15		T13	13		T14	334
auto[TlIntgErrNone]	partial	auto[1]	90656787	1			T12	19		T13	22		T14	69
auto[TlIntgErrNone]	full_word	auto[0]	43384115	1			T12	13		T13	16		T14	492
auto[TlIntgErrNone]	full_word	auto[1]	77661233	1			T12	9		T13	7		T14	646
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T14	3		T63	4		T64	4
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T14	2		T63	4		T64	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T143	1		T145	1		T146	2
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T14	1		T63	1		T143	3
auto[TlIntgErrData]	partial	auto[0]	52	1			T14	3		T63	2		T64	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T14	9		T63	1		T64	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T14	1		T64	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T63	1		T141	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T14	3		T63	4		T64	3
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T14	6		T63	2		T64	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T14	1		T143	2		T147	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T14	1		T63	1		T148	1